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1da177e4 | 1 | /* |
fe27cb35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver ($Revision: 1.4 $) |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1da177e4 LT |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
fe27cb35 VP |
31 | #include <linux/smp.h> |
32 | #include <linux/sched.h> | |
1da177e4 | 33 | #include <linux/cpufreq.h> |
d395bf12 | 34 | #include <linux/compiler.h> |
8adcc0c6 | 35 | #include <linux/dmi.h> |
1da177e4 LT |
36 | |
37 | #include <linux/acpi.h> | |
38 | #include <acpi/processor.h> | |
39 | ||
fe27cb35 | 40 | #include <asm/io.h> |
dde9f7ba | 41 | #include <asm/msr.h> |
fe27cb35 VP |
42 | #include <asm/processor.h> |
43 | #include <asm/cpufeature.h> | |
44 | #include <asm/delay.h> | |
45 | #include <asm/uaccess.h> | |
46 | ||
1da177e4 LT |
47 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "acpi-cpufreq", msg) |
48 | ||
49 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); | |
50 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
dde9f7ba VP |
53 | enum { |
54 | UNDEFINED_CAPABLE = 0, | |
55 | SYSTEM_INTEL_MSR_CAPABLE, | |
56 | SYSTEM_IO_CAPABLE, | |
57 | }; | |
58 | ||
59 | #define INTEL_MSR_RANGE (0xffff) | |
dfde5d62 | 60 | #define CPUID_6_ECX_APERFMPERF_CAPABILITY (0x1) |
dde9f7ba | 61 | |
fe27cb35 | 62 | struct acpi_cpufreq_data { |
64be7eed VP |
63 | struct acpi_processor_performance *acpi_data; |
64 | struct cpufreq_frequency_table *freq_table; | |
dfde5d62 | 65 | unsigned int max_freq; |
64be7eed VP |
66 | unsigned int resume; |
67 | unsigned int cpu_feature; | |
1da177e4 LT |
68 | }; |
69 | ||
64be7eed VP |
70 | static struct acpi_cpufreq_data *drv_data[NR_CPUS]; |
71 | static struct acpi_processor_performance *acpi_perf_data[NR_CPUS]; | |
1da177e4 LT |
72 | |
73 | static struct cpufreq_driver acpi_cpufreq_driver; | |
74 | ||
d395bf12 VP |
75 | static unsigned int acpi_pstate_strict; |
76 | ||
dde9f7ba VP |
77 | static int check_est_cpu(unsigned int cpuid) |
78 | { | |
79 | struct cpuinfo_x86 *cpu = &cpu_data[cpuid]; | |
80 | ||
81 | if (cpu->x86_vendor != X86_VENDOR_INTEL || | |
64be7eed | 82 | !cpu_has(cpu, X86_FEATURE_EST)) |
dde9f7ba VP |
83 | return 0; |
84 | ||
85 | return 1; | |
86 | } | |
87 | ||
dde9f7ba | 88 | static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) |
fe27cb35 | 89 | { |
64be7eed VP |
90 | struct acpi_processor_performance *perf; |
91 | int i; | |
fe27cb35 VP |
92 | |
93 | perf = data->acpi_data; | |
94 | ||
95 | for (i = 0; i < perf->state_count; i++) { | |
96 | if (value == perf->states[i].status) | |
97 | return data->freq_table[i].frequency; | |
98 | } | |
99 | return 0; | |
100 | } | |
101 | ||
dde9f7ba VP |
102 | static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) |
103 | { | |
104 | int i; | |
a6f6e6e6 | 105 | struct acpi_processor_performance *perf; |
dde9f7ba VP |
106 | |
107 | msr &= INTEL_MSR_RANGE; | |
a6f6e6e6 VP |
108 | perf = data->acpi_data; |
109 | ||
dde9f7ba | 110 | for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { |
a6f6e6e6 | 111 | if (msr == perf->states[data->freq_table[i].index].status) |
dde9f7ba VP |
112 | return data->freq_table[i].frequency; |
113 | } | |
114 | return data->freq_table[0].frequency; | |
115 | } | |
116 | ||
dde9f7ba VP |
117 | static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) |
118 | { | |
119 | switch (data->cpu_feature) { | |
64be7eed | 120 | case SYSTEM_INTEL_MSR_CAPABLE: |
dde9f7ba | 121 | return extract_msr(val, data); |
64be7eed | 122 | case SYSTEM_IO_CAPABLE: |
dde9f7ba | 123 | return extract_io(val, data); |
64be7eed | 124 | default: |
dde9f7ba VP |
125 | return 0; |
126 | } | |
127 | } | |
128 | ||
fe27cb35 | 129 | static void wrport(u16 port, u8 bit_width, u32 value) |
1da177e4 LT |
130 | { |
131 | if (bit_width <= 8) { | |
132 | outb(value, port); | |
133 | } else if (bit_width <= 16) { | |
134 | outw(value, port); | |
135 | } else if (bit_width <= 32) { | |
136 | outl(value, port); | |
1da177e4 | 137 | } |
1da177e4 LT |
138 | } |
139 | ||
64be7eed | 140 | static void rdport(u16 port, u8 bit_width, u32 * ret) |
1da177e4 LT |
141 | { |
142 | *ret = 0; | |
143 | if (bit_width <= 8) { | |
144 | *ret = inb(port); | |
145 | } else if (bit_width <= 16) { | |
146 | *ret = inw(port); | |
147 | } else if (bit_width <= 32) { | |
148 | *ret = inl(port); | |
1da177e4 | 149 | } |
1da177e4 LT |
150 | } |
151 | ||
dde9f7ba VP |
152 | struct msr_addr { |
153 | u32 reg; | |
154 | }; | |
155 | ||
fe27cb35 VP |
156 | struct io_addr { |
157 | u16 port; | |
158 | u8 bit_width; | |
159 | }; | |
160 | ||
dde9f7ba VP |
161 | typedef union { |
162 | struct msr_addr msr; | |
163 | struct io_addr io; | |
164 | } drv_addr_union; | |
165 | ||
fe27cb35 | 166 | struct drv_cmd { |
dde9f7ba | 167 | unsigned int type; |
fe27cb35 | 168 | cpumask_t mask; |
dde9f7ba | 169 | drv_addr_union addr; |
fe27cb35 VP |
170 | u32 val; |
171 | }; | |
172 | ||
173 | static void do_drv_read(struct drv_cmd *cmd) | |
1da177e4 | 174 | { |
dde9f7ba VP |
175 | u32 h; |
176 | ||
177 | switch (cmd->type) { | |
64be7eed | 178 | case SYSTEM_INTEL_MSR_CAPABLE: |
dde9f7ba VP |
179 | rdmsr(cmd->addr.msr.reg, cmd->val, h); |
180 | break; | |
64be7eed | 181 | case SYSTEM_IO_CAPABLE: |
dde9f7ba VP |
182 | rdport(cmd->addr.io.port, cmd->addr.io.bit_width, &cmd->val); |
183 | break; | |
64be7eed | 184 | default: |
dde9f7ba VP |
185 | break; |
186 | } | |
fe27cb35 | 187 | } |
1da177e4 | 188 | |
fe27cb35 VP |
189 | static void do_drv_write(struct drv_cmd *cmd) |
190 | { | |
dde9f7ba VP |
191 | u32 h = 0; |
192 | ||
193 | switch (cmd->type) { | |
64be7eed | 194 | case SYSTEM_INTEL_MSR_CAPABLE: |
dde9f7ba VP |
195 | wrmsr(cmd->addr.msr.reg, cmd->val, h); |
196 | break; | |
64be7eed | 197 | case SYSTEM_IO_CAPABLE: |
dde9f7ba VP |
198 | wrport(cmd->addr.io.port, cmd->addr.io.bit_width, cmd->val); |
199 | break; | |
64be7eed | 200 | default: |
dde9f7ba VP |
201 | break; |
202 | } | |
fe27cb35 | 203 | } |
1da177e4 | 204 | |
fe27cb35 VP |
205 | static inline void drv_read(struct drv_cmd *cmd) |
206 | { | |
64be7eed | 207 | cpumask_t saved_mask = current->cpus_allowed; |
fe27cb35 VP |
208 | cmd->val = 0; |
209 | ||
210 | set_cpus_allowed(current, cmd->mask); | |
211 | do_drv_read(cmd); | |
212 | set_cpus_allowed(current, saved_mask); | |
213 | ||
214 | } | |
215 | ||
216 | static void drv_write(struct drv_cmd *cmd) | |
217 | { | |
64be7eed VP |
218 | cpumask_t saved_mask = current->cpus_allowed; |
219 | unsigned int i; | |
fe27cb35 VP |
220 | |
221 | for_each_cpu_mask(i, cmd->mask) { | |
222 | set_cpus_allowed(current, cpumask_of_cpu(i)); | |
223 | do_drv_write(cmd); | |
1da177e4 LT |
224 | } |
225 | ||
fe27cb35 VP |
226 | set_cpus_allowed(current, saved_mask); |
227 | return; | |
228 | } | |
1da177e4 | 229 | |
fe27cb35 VP |
230 | static u32 get_cur_val(cpumask_t mask) |
231 | { | |
64be7eed VP |
232 | struct acpi_processor_performance *perf; |
233 | struct drv_cmd cmd; | |
1da177e4 | 234 | |
fe27cb35 VP |
235 | if (unlikely(cpus_empty(mask))) |
236 | return 0; | |
1da177e4 | 237 | |
dde9f7ba VP |
238 | switch (drv_data[first_cpu(mask)]->cpu_feature) { |
239 | case SYSTEM_INTEL_MSR_CAPABLE: | |
240 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
241 | cmd.addr.msr.reg = MSR_IA32_PERF_STATUS; | |
242 | break; | |
243 | case SYSTEM_IO_CAPABLE: | |
244 | cmd.type = SYSTEM_IO_CAPABLE; | |
245 | perf = drv_data[first_cpu(mask)]->acpi_data; | |
246 | cmd.addr.io.port = perf->control_register.address; | |
247 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
248 | break; | |
249 | default: | |
250 | return 0; | |
251 | } | |
252 | ||
fe27cb35 | 253 | cmd.mask = mask; |
1da177e4 | 254 | |
fe27cb35 | 255 | drv_read(&cmd); |
1da177e4 | 256 | |
fe27cb35 VP |
257 | dprintk("get_cur_val = %u\n", cmd.val); |
258 | ||
259 | return cmd.val; | |
260 | } | |
1da177e4 | 261 | |
dfde5d62 VP |
262 | /* |
263 | * Return the measured active (C0) frequency on this CPU since last call | |
264 | * to this function. | |
265 | * Input: cpu number | |
266 | * Return: Average CPU frequency in terms of max frequency (zero on error) | |
267 | * | |
268 | * We use IA32_MPERF and IA32_APERF MSRs to get the measured performance | |
269 | * over a period of time, while CPU is in C0 state. | |
270 | * IA32_MPERF counts at the rate of max advertised frequency | |
271 | * IA32_APERF counts at the rate of actual CPU frequency | |
272 | * Only IA32_APERF/IA32_MPERF ratio is architecturally defined and | |
273 | * no meaning should be associated with absolute values of these MSRs. | |
274 | */ | |
275 | static unsigned int get_measured_perf(unsigned int cpu) | |
276 | { | |
277 | union { | |
278 | struct { | |
279 | u32 lo; | |
280 | u32 hi; | |
281 | } split; | |
282 | u64 whole; | |
283 | } aperf_cur, mperf_cur; | |
284 | ||
285 | cpumask_t saved_mask; | |
286 | unsigned int perf_percent; | |
287 | unsigned int retval; | |
288 | ||
289 | saved_mask = current->cpus_allowed; | |
290 | set_cpus_allowed(current, cpumask_of_cpu(cpu)); | |
291 | if (get_cpu() != cpu) { | |
292 | /* We were not able to run on requested processor */ | |
293 | put_cpu(); | |
294 | return 0; | |
295 | } | |
296 | ||
297 | rdmsr(MSR_IA32_APERF, aperf_cur.split.lo, aperf_cur.split.hi); | |
298 | rdmsr(MSR_IA32_MPERF, mperf_cur.split.lo, mperf_cur.split.hi); | |
299 | ||
300 | wrmsr(MSR_IA32_APERF, 0,0); | |
301 | wrmsr(MSR_IA32_MPERF, 0,0); | |
302 | ||
303 | #ifdef __i386__ | |
304 | /* | |
305 | * We dont want to do 64 bit divide with 32 bit kernel | |
306 | * Get an approximate value. Return failure in case we cannot get | |
307 | * an approximate value. | |
308 | */ | |
309 | if (unlikely(aperf_cur.split.hi || mperf_cur.split.hi)) { | |
310 | int shift_count; | |
311 | u32 h; | |
312 | ||
313 | h = max_t(u32, aperf_cur.split.hi, mperf_cur.split.hi); | |
314 | shift_count = fls(h); | |
315 | ||
316 | aperf_cur.whole >>= shift_count; | |
317 | mperf_cur.whole >>= shift_count; | |
318 | } | |
319 | ||
320 | if (((unsigned long)(-1) / 100) < aperf_cur.split.lo) { | |
321 | int shift_count = 7; | |
322 | aperf_cur.split.lo >>= shift_count; | |
323 | mperf_cur.split.lo >>= shift_count; | |
324 | } | |
325 | ||
326 | if (aperf_cur.split.lo && mperf_cur.split.lo) { | |
327 | perf_percent = (aperf_cur.split.lo * 100) / mperf_cur.split.lo; | |
328 | } else { | |
329 | perf_percent = 0; | |
330 | } | |
331 | ||
332 | #else | |
333 | if (unlikely(((unsigned long)(-1) / 100) < aperf_cur.whole)) { | |
334 | int shift_count = 7; | |
335 | aperf_cur.whole >>= shift_count; | |
336 | mperf_cur.whole >>= shift_count; | |
337 | } | |
338 | ||
339 | if (aperf_cur.whole && mperf_cur.whole) { | |
340 | perf_percent = (aperf_cur.whole * 100) / mperf_cur.whole; | |
341 | } else { | |
342 | perf_percent = 0; | |
343 | } | |
344 | ||
345 | #endif | |
346 | ||
347 | retval = drv_data[cpu]->max_freq * perf_percent / 100; | |
348 | ||
349 | put_cpu(); | |
350 | set_cpus_allowed(current, saved_mask); | |
351 | ||
352 | dprintk("cpu %d: performance percent %d\n", cpu, perf_percent); | |
353 | return retval; | |
354 | } | |
355 | ||
fe27cb35 VP |
356 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
357 | { | |
64be7eed VP |
358 | struct acpi_cpufreq_data *data = drv_data[cpu]; |
359 | unsigned int freq; | |
fe27cb35 VP |
360 | |
361 | dprintk("get_cur_freq_on_cpu (%d)\n", cpu); | |
362 | ||
363 | if (unlikely(data == NULL || | |
64be7eed | 364 | data->acpi_data == NULL || data->freq_table == NULL)) { |
fe27cb35 | 365 | return 0; |
1da177e4 LT |
366 | } |
367 | ||
fe27cb35 VP |
368 | freq = extract_freq(get_cur_val(cpumask_of_cpu(cpu)), data); |
369 | dprintk("cur freq = %u\n", freq); | |
1da177e4 | 370 | |
fe27cb35 | 371 | return freq; |
1da177e4 LT |
372 | } |
373 | ||
fe27cb35 | 374 | static unsigned int check_freqs(cpumask_t mask, unsigned int freq, |
64be7eed | 375 | struct acpi_cpufreq_data *data) |
fe27cb35 | 376 | { |
64be7eed VP |
377 | unsigned int cur_freq; |
378 | unsigned int i; | |
1da177e4 | 379 | |
fe27cb35 VP |
380 | for (i = 0; i < 100; i++) { |
381 | cur_freq = extract_freq(get_cur_val(mask), data); | |
382 | if (cur_freq == freq) | |
383 | return 1; | |
384 | udelay(10); | |
385 | } | |
386 | return 0; | |
387 | } | |
388 | ||
389 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
64be7eed | 390 | unsigned int target_freq, unsigned int relation) |
1da177e4 | 391 | { |
64be7eed VP |
392 | struct acpi_cpufreq_data *data = drv_data[policy->cpu]; |
393 | struct acpi_processor_performance *perf; | |
394 | struct cpufreq_freqs freqs; | |
395 | cpumask_t online_policy_cpus; | |
396 | struct drv_cmd cmd; | |
397 | unsigned int msr; | |
398 | unsigned int next_state = 0; | |
399 | unsigned int next_perf_state = 0; | |
400 | unsigned int i; | |
401 | int result = 0; | |
fe27cb35 VP |
402 | |
403 | dprintk("acpi_cpufreq_target %d (%d)\n", target_freq, policy->cpu); | |
404 | ||
405 | if (unlikely(data == NULL || | |
64be7eed | 406 | data->acpi_data == NULL || data->freq_table == NULL)) { |
fe27cb35 VP |
407 | return -ENODEV; |
408 | } | |
1da177e4 | 409 | |
fe27cb35 | 410 | perf = data->acpi_data; |
1da177e4 | 411 | result = cpufreq_frequency_table_target(policy, |
64be7eed VP |
412 | data->freq_table, |
413 | target_freq, | |
414 | relation, &next_state); | |
09b4d1ee | 415 | if (unlikely(result)) |
fe27cb35 | 416 | return -ENODEV; |
09b4d1ee | 417 | |
7e1f19e5 | 418 | #ifdef CONFIG_HOTPLUG_CPU |
09b4d1ee VP |
419 | /* cpufreq holds the hotplug lock, so we are safe from here on */ |
420 | cpus_and(online_policy_cpus, cpu_online_map, policy->cpus); | |
7e1f19e5 AM |
421 | #else |
422 | online_policy_cpus = policy->cpus; | |
423 | #endif | |
1da177e4 | 424 | |
fe27cb35 | 425 | next_perf_state = data->freq_table[next_state].index; |
7650b281 | 426 | if (perf->state == next_perf_state) { |
fe27cb35 | 427 | if (unlikely(data->resume)) { |
64be7eed VP |
428 | dprintk("Called after resume, resetting to P%d\n", |
429 | next_perf_state); | |
fe27cb35 VP |
430 | data->resume = 0; |
431 | } else { | |
64be7eed VP |
432 | dprintk("Already at target state (P%d)\n", |
433 | next_perf_state); | |
fe27cb35 VP |
434 | return 0; |
435 | } | |
09b4d1ee VP |
436 | } |
437 | ||
64be7eed VP |
438 | switch (data->cpu_feature) { |
439 | case SYSTEM_INTEL_MSR_CAPABLE: | |
440 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
441 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; | |
442 | msr = | |
443 | (u32) perf->states[next_perf_state]. | |
444 | control & INTEL_MSR_RANGE; | |
445 | cmd.val = (cmd.val & ~INTEL_MSR_RANGE) | msr; | |
446 | break; | |
447 | case SYSTEM_IO_CAPABLE: | |
448 | cmd.type = SYSTEM_IO_CAPABLE; | |
449 | cmd.addr.io.port = perf->control_register.address; | |
450 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
451 | cmd.val = (u32) perf->states[next_perf_state].control; | |
452 | break; | |
453 | default: | |
454 | return -ENODEV; | |
455 | } | |
09b4d1ee | 456 | |
fe27cb35 | 457 | cpus_clear(cmd.mask); |
09b4d1ee | 458 | |
fe27cb35 VP |
459 | if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) |
460 | cmd.mask = online_policy_cpus; | |
461 | else | |
462 | cpu_set(policy->cpu, cmd.mask); | |
09b4d1ee | 463 | |
7650b281 VP |
464 | freqs.old = data->freq_table[perf->state].frequency; |
465 | freqs.new = data->freq_table[next_perf_state].frequency; | |
fe27cb35 VP |
466 | for_each_cpu_mask(i, cmd.mask) { |
467 | freqs.cpu = i; | |
468 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
09b4d1ee | 469 | } |
1da177e4 | 470 | |
fe27cb35 | 471 | drv_write(&cmd); |
09b4d1ee | 472 | |
fe27cb35 VP |
473 | if (acpi_pstate_strict) { |
474 | if (!check_freqs(cmd.mask, freqs.new, data)) { | |
475 | dprintk("acpi_cpufreq_target failed (%d)\n", | |
64be7eed | 476 | policy->cpu); |
fe27cb35 | 477 | return -EAGAIN; |
09b4d1ee VP |
478 | } |
479 | } | |
480 | ||
fe27cb35 VP |
481 | for_each_cpu_mask(i, cmd.mask) { |
482 | freqs.cpu = i; | |
483 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
484 | } | |
485 | perf->state = next_perf_state; | |
486 | ||
487 | return result; | |
1da177e4 LT |
488 | } |
489 | ||
64be7eed | 490 | static int acpi_cpufreq_verify(struct cpufreq_policy *policy) |
1da177e4 | 491 | { |
fe27cb35 | 492 | struct acpi_cpufreq_data *data = drv_data[policy->cpu]; |
1da177e4 LT |
493 | |
494 | dprintk("acpi_cpufreq_verify\n"); | |
495 | ||
fe27cb35 | 496 | return cpufreq_frequency_table_verify(policy, data->freq_table); |
1da177e4 LT |
497 | } |
498 | ||
1da177e4 | 499 | static unsigned long |
64be7eed | 500 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 501 | { |
64be7eed | 502 | struct acpi_processor_performance *perf = data->acpi_data; |
09b4d1ee | 503 | |
1da177e4 LT |
504 | if (cpu_khz) { |
505 | /* search the closest match to cpu_khz */ | |
506 | unsigned int i; | |
507 | unsigned long freq; | |
09b4d1ee | 508 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 509 | |
09b4d1ee | 510 | for (i = 0; i < (perf->state_count - 1); i++) { |
1da177e4 | 511 | freq = freqn; |
64be7eed | 512 | freqn = perf->states[i + 1].core_frequency * 1000; |
1da177e4 | 513 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 514 | perf->state = i; |
64be7eed | 515 | return freq; |
1da177e4 LT |
516 | } |
517 | } | |
09b4d1ee | 518 | perf->state = perf->state_count - 1; |
64be7eed | 519 | return freqn; |
09b4d1ee | 520 | } else { |
1da177e4 | 521 | /* assume CPU is at P0... */ |
09b4d1ee VP |
522 | perf->state = 0; |
523 | return perf->states[0].core_frequency * 1000; | |
524 | } | |
1da177e4 LT |
525 | } |
526 | ||
09b4d1ee VP |
527 | /* |
528 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
529 | * | |
530 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
531 | * in order to determine correct frequency and voltage pairings. We can | |
532 | * do _PDC and _PSD and find out the processor dependency for the | |
533 | * actual init that will happen later... | |
534 | */ | |
fe27cb35 | 535 | static int acpi_cpufreq_early_init(void) |
09b4d1ee | 536 | { |
64be7eed VP |
537 | struct acpi_processor_performance *data; |
538 | cpumask_t covered; | |
539 | unsigned int i, j; | |
09b4d1ee VP |
540 | |
541 | dprintk("acpi_cpufreq_early_init\n"); | |
542 | ||
fb1bb34d | 543 | for_each_possible_cpu(i) { |
64be7eed VP |
544 | data = kzalloc(sizeof(struct acpi_processor_performance), |
545 | GFP_KERNEL); | |
09b4d1ee | 546 | if (!data) { |
fe27cb35 | 547 | for_each_cpu_mask(j, covered) { |
09b4d1ee VP |
548 | kfree(acpi_perf_data[j]); |
549 | acpi_perf_data[j] = NULL; | |
550 | } | |
64be7eed | 551 | return -ENOMEM; |
09b4d1ee VP |
552 | } |
553 | acpi_perf_data[i] = data; | |
fe27cb35 | 554 | cpu_set(i, covered); |
09b4d1ee VP |
555 | } |
556 | ||
557 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
558 | acpi_processor_preregister_performance(acpi_perf_data); |
559 | return 0; | |
09b4d1ee VP |
560 | } |
561 | ||
8adcc0c6 VP |
562 | /* |
563 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
564 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
565 | * detected, this has a side effect of making CPU run at a different speed | |
566 | * than OS intended it to run at. Detect it and handle it cleanly. | |
567 | */ | |
568 | static int bios_with_sw_any_bug; | |
569 | ||
0497c8ca | 570 | static int sw_any_bug_found(struct dmi_system_id *d) |
8adcc0c6 VP |
571 | { |
572 | bios_with_sw_any_bug = 1; | |
573 | return 0; | |
574 | } | |
575 | ||
0497c8ca | 576 | static struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
577 | { |
578 | .callback = sw_any_bug_found, | |
579 | .ident = "Supermicro Server X6DLP", | |
580 | .matches = { | |
581 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
582 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
583 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
584 | }, | |
585 | }, | |
586 | { } | |
587 | }; | |
588 | ||
64be7eed | 589 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 590 | { |
64be7eed VP |
591 | unsigned int i; |
592 | unsigned int valid_states = 0; | |
593 | unsigned int cpu = policy->cpu; | |
594 | struct acpi_cpufreq_data *data; | |
64be7eed VP |
595 | unsigned int result = 0; |
596 | struct cpuinfo_x86 *c = &cpu_data[policy->cpu]; | |
597 | struct acpi_processor_performance *perf; | |
1da177e4 | 598 | |
1da177e4 | 599 | dprintk("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 600 | |
09b4d1ee | 601 | if (!acpi_perf_data[cpu]) |
64be7eed | 602 | return -ENODEV; |
09b4d1ee | 603 | |
fe27cb35 | 604 | data = kzalloc(sizeof(struct acpi_cpufreq_data), GFP_KERNEL); |
1da177e4 | 605 | if (!data) |
64be7eed | 606 | return -ENOMEM; |
1da177e4 | 607 | |
09b4d1ee | 608 | data->acpi_data = acpi_perf_data[cpu]; |
fe27cb35 | 609 | drv_data[cpu] = data; |
1da177e4 | 610 | |
fe27cb35 VP |
611 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
612 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; | |
613 | } | |
1da177e4 | 614 | |
fe27cb35 | 615 | result = acpi_processor_register_performance(data->acpi_data, cpu); |
1da177e4 LT |
616 | if (result) |
617 | goto err_free; | |
618 | ||
09b4d1ee | 619 | perf = data->acpi_data; |
09b4d1ee | 620 | policy->shared_type = perf->shared_type; |
46f18e3a VP |
621 | /* |
622 | * Will let policy->cpus know about dependency only when software | |
623 | * coordination is required. | |
624 | */ | |
625 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 626 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
46f18e3a | 627 | policy->cpus = perf->shared_cpu_map; |
8adcc0c6 VP |
628 | } |
629 | ||
630 | #ifdef CONFIG_SMP | |
631 | dmi_check_system(sw_any_bug_dmi_table); | |
632 | if (bios_with_sw_any_bug && cpus_weight(policy->cpus) == 1) { | |
633 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
634 | policy->cpus = cpu_core_map[cpu]; | |
635 | } | |
636 | #endif | |
09b4d1ee | 637 | |
1da177e4 | 638 | /* capability check */ |
09b4d1ee | 639 | if (perf->state_count <= 1) { |
1da177e4 LT |
640 | dprintk("No P-States\n"); |
641 | result = -ENODEV; | |
642 | goto err_unreg; | |
643 | } | |
09b4d1ee | 644 | |
fe27cb35 VP |
645 | if (perf->control_register.space_id != perf->status_register.space_id) { |
646 | result = -ENODEV; | |
647 | goto err_unreg; | |
648 | } | |
649 | ||
650 | switch (perf->control_register.space_id) { | |
64be7eed | 651 | case ACPI_ADR_SPACE_SYSTEM_IO: |
fe27cb35 | 652 | dprintk("SYSTEM IO addr space\n"); |
dde9f7ba VP |
653 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
654 | break; | |
64be7eed | 655 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
dde9f7ba VP |
656 | dprintk("HARDWARE addr space\n"); |
657 | if (!check_est_cpu(cpu)) { | |
658 | result = -ENODEV; | |
659 | goto err_unreg; | |
660 | } | |
661 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
fe27cb35 | 662 | break; |
64be7eed | 663 | default: |
fe27cb35 | 664 | dprintk("Unknown addr space %d\n", |
64be7eed | 665 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
666 | result = -ENODEV; |
667 | goto err_unreg; | |
668 | } | |
669 | ||
64be7eed VP |
670 | data->freq_table = |
671 | kmalloc(sizeof(struct cpufreq_frequency_table) * | |
672 | (perf->state_count + 1), GFP_KERNEL); | |
1da177e4 LT |
673 | if (!data->freq_table) { |
674 | result = -ENOMEM; | |
675 | goto err_unreg; | |
676 | } | |
677 | ||
678 | /* detect transition latency */ | |
679 | policy->cpuinfo.transition_latency = 0; | |
64be7eed VP |
680 | for (i = 0; i < perf->state_count; i++) { |
681 | if ((perf->states[i].transition_latency * 1000) > | |
682 | policy->cpuinfo.transition_latency) | |
683 | policy->cpuinfo.transition_latency = | |
684 | perf->states[i].transition_latency * 1000; | |
1da177e4 LT |
685 | } |
686 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | |
687 | ||
dfde5d62 | 688 | data->max_freq = perf->states[0].core_frequency * 1000; |
1da177e4 | 689 | /* table init */ |
64be7eed VP |
690 | for (i = 0; i < perf->state_count; i++) { |
691 | if (i > 0 && perf->states[i].core_frequency == | |
692 | perf->states[i - 1].core_frequency) | |
fe27cb35 VP |
693 | continue; |
694 | ||
695 | data->freq_table[valid_states].index = i; | |
696 | data->freq_table[valid_states].frequency = | |
64be7eed | 697 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 698 | valid_states++; |
1da177e4 | 699 | } |
fe27cb35 | 700 | data->freq_table[perf->state_count].frequency = CPUFREQ_TABLE_END; |
1da177e4 LT |
701 | |
702 | result = cpufreq_frequency_table_cpuinfo(policy, data->freq_table); | |
703 | if (result) { | |
704 | goto err_freqfree; | |
705 | } | |
706 | ||
dde9f7ba | 707 | switch (data->cpu_feature) { |
64be7eed | 708 | case ACPI_ADR_SPACE_SYSTEM_IO: |
dde9f7ba VP |
709 | /* Current speed is unknown and not detectable by IO port */ |
710 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); | |
711 | break; | |
64be7eed | 712 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 713 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba VP |
714 | get_cur_freq_on_cpu(cpu); |
715 | break; | |
64be7eed | 716 | default: |
dde9f7ba VP |
717 | break; |
718 | } | |
719 | ||
1da177e4 LT |
720 | /* notify BIOS that we exist */ |
721 | acpi_processor_notify_smm(THIS_MODULE); | |
722 | ||
dfde5d62 VP |
723 | /* Check for APERF/MPERF support in hardware */ |
724 | if (c->x86_vendor == X86_VENDOR_INTEL && c->cpuid_level >= 6) { | |
725 | unsigned int ecx; | |
726 | ecx = cpuid_ecx(6); | |
727 | if (ecx & CPUID_6_ECX_APERFMPERF_CAPABILITY) { | |
728 | acpi_cpufreq_driver.getavg = get_measured_perf; | |
729 | } | |
730 | } | |
731 | ||
fe27cb35 | 732 | dprintk("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 733 | for (i = 0; i < perf->state_count; i++) |
1da177e4 | 734 | dprintk(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 735 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
736 | (u32) perf->states[i].core_frequency, |
737 | (u32) perf->states[i].power, | |
738 | (u32) perf->states[i].transition_latency); | |
1da177e4 LT |
739 | |
740 | cpufreq_frequency_table_get_attr(data->freq_table, policy->cpu); | |
64be7eed | 741 | |
4b31e774 DB |
742 | /* |
743 | * the first call to ->target() should result in us actually | |
744 | * writing something to the appropriate registers. | |
745 | */ | |
746 | data->resume = 1; | |
64be7eed | 747 | |
fe27cb35 | 748 | return result; |
1da177e4 | 749 | |
64be7eed | 750 | err_freqfree: |
1da177e4 | 751 | kfree(data->freq_table); |
64be7eed | 752 | err_unreg: |
09b4d1ee | 753 | acpi_processor_unregister_performance(perf, cpu); |
64be7eed | 754 | err_free: |
1da177e4 | 755 | kfree(data); |
fe27cb35 | 756 | drv_data[cpu] = NULL; |
1da177e4 | 757 | |
64be7eed | 758 | return result; |
1da177e4 LT |
759 | } |
760 | ||
64be7eed | 761 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 762 | { |
fe27cb35 | 763 | struct acpi_cpufreq_data *data = drv_data[policy->cpu]; |
1da177e4 | 764 | |
1da177e4 LT |
765 | dprintk("acpi_cpufreq_cpu_exit\n"); |
766 | ||
767 | if (data) { | |
768 | cpufreq_frequency_table_put_attr(policy->cpu); | |
fe27cb35 | 769 | drv_data[policy->cpu] = NULL; |
64be7eed VP |
770 | acpi_processor_unregister_performance(data->acpi_data, |
771 | policy->cpu); | |
1da177e4 LT |
772 | kfree(data); |
773 | } | |
774 | ||
64be7eed | 775 | return 0; |
1da177e4 LT |
776 | } |
777 | ||
64be7eed | 778 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 779 | { |
fe27cb35 | 780 | struct acpi_cpufreq_data *data = drv_data[policy->cpu]; |
1da177e4 | 781 | |
1da177e4 LT |
782 | dprintk("acpi_cpufreq_resume\n"); |
783 | ||
784 | data->resume = 1; | |
785 | ||
64be7eed | 786 | return 0; |
1da177e4 LT |
787 | } |
788 | ||
64be7eed | 789 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 LT |
790 | &cpufreq_freq_attr_scaling_available_freqs, |
791 | NULL, | |
792 | }; | |
793 | ||
794 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
64be7eed VP |
795 | .verify = acpi_cpufreq_verify, |
796 | .target = acpi_cpufreq_target, | |
64be7eed VP |
797 | .init = acpi_cpufreq_cpu_init, |
798 | .exit = acpi_cpufreq_cpu_exit, | |
799 | .resume = acpi_cpufreq_resume, | |
800 | .name = "acpi-cpufreq", | |
801 | .owner = THIS_MODULE, | |
802 | .attr = acpi_cpufreq_attr, | |
1da177e4 LT |
803 | }; |
804 | ||
64be7eed | 805 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 806 | { |
1da177e4 LT |
807 | dprintk("acpi_cpufreq_init\n"); |
808 | ||
fe27cb35 | 809 | acpi_cpufreq_early_init(); |
09b4d1ee | 810 | |
64be7eed | 811 | return cpufreq_register_driver(&acpi_cpufreq_driver); |
1da177e4 LT |
812 | } |
813 | ||
64be7eed | 814 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 815 | { |
64be7eed | 816 | unsigned int i; |
1da177e4 LT |
817 | dprintk("acpi_cpufreq_exit\n"); |
818 | ||
819 | cpufreq_unregister_driver(&acpi_cpufreq_driver); | |
820 | ||
fb1bb34d | 821 | for_each_possible_cpu(i) { |
09b4d1ee VP |
822 | kfree(acpi_perf_data[i]); |
823 | acpi_perf_data[i] = NULL; | |
824 | } | |
1da177e4 LT |
825 | return; |
826 | } | |
827 | ||
d395bf12 | 828 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed VP |
829 | MODULE_PARM_DESC(acpi_pstate_strict, |
830 | "value 0 or non-zero. non-zero -> strict ACPI checks are performed during frequency changes."); | |
1da177e4 LT |
831 | |
832 | late_initcall(acpi_cpufreq_init); | |
833 | module_exit(acpi_cpufreq_exit); | |
834 | ||
835 | MODULE_ALIAS("acpi"); |