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1da177e4 LT |
1 | /* |
2 | * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> | |
3 | * | |
4 | * Licensed under the terms of the GNU GPL License version 2. | |
5 | * | |
6 | * Library for common functions for Intel SpeedStep v.1 and v.2 support | |
7 | * | |
8 | * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/cpufreq.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/slab.h> | |
18 | ||
19 | #include <asm/msr.h> | |
20 | #include "speedstep-lib.h" | |
21 | ||
22 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg) | |
23 | ||
24 | #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK | |
25 | static int relaxed_check = 0; | |
26 | #else | |
27 | #define relaxed_check 0 | |
28 | #endif | |
29 | ||
30 | /********************************************************************* | |
31 | * GET PROCESSOR CORE SPEED IN KHZ * | |
32 | *********************************************************************/ | |
33 | ||
34 | static unsigned int pentium3_get_frequency (unsigned int processor) | |
35 | { | |
36 | /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ | |
37 | struct { | |
38 | unsigned int ratio; /* Frequency Multiplier (x10) */ | |
39 | u8 bitmap; /* power on configuration bits | |
40 | [27, 25:22] (in MSR 0x2a) */ | |
41 | } msr_decode_mult [] = { | |
42 | { 30, 0x01 }, | |
43 | { 35, 0x05 }, | |
44 | { 40, 0x02 }, | |
45 | { 45, 0x06 }, | |
46 | { 50, 0x00 }, | |
47 | { 55, 0x04 }, | |
48 | { 60, 0x0b }, | |
49 | { 65, 0x0f }, | |
50 | { 70, 0x09 }, | |
51 | { 75, 0x0d }, | |
52 | { 80, 0x0a }, | |
53 | { 85, 0x26 }, | |
54 | { 90, 0x20 }, | |
55 | { 100, 0x2b }, | |
56 | { 0, 0xff } /* error or unknown value */ | |
57 | }; | |
58 | ||
59 | /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ | |
60 | struct { | |
61 | unsigned int value; /* Front Side Bus speed in MHz */ | |
62 | u8 bitmap; /* power on configuration bits [18: 19] | |
63 | (in MSR 0x2a) */ | |
64 | } msr_decode_fsb [] = { | |
65 | { 66, 0x0 }, | |
66 | { 100, 0x2 }, | |
67 | { 133, 0x1 }, | |
68 | { 0, 0xff} | |
69 | }; | |
70 | ||
71 | u32 msr_lo, msr_tmp; | |
72 | int i = 0, j = 0; | |
73 | ||
74 | /* read MSR 0x2a - we only need the low 32 bits */ | |
75 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
76 | dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); | |
77 | msr_tmp = msr_lo; | |
78 | ||
79 | /* decode the FSB */ | |
80 | msr_tmp &= 0x00c0000; | |
81 | msr_tmp >>= 18; | |
82 | while (msr_tmp != msr_decode_fsb[i].bitmap) { | |
83 | if (msr_decode_fsb[i].bitmap == 0xff) | |
84 | return 0; | |
85 | i++; | |
86 | } | |
87 | ||
88 | /* decode the multiplier */ | |
89 | if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) { | |
90 | dprintk("workaround for early PIIIs\n"); | |
91 | msr_lo &= 0x03c00000; | |
92 | } else | |
93 | msr_lo &= 0x0bc00000; | |
94 | msr_lo >>= 22; | |
95 | while (msr_lo != msr_decode_mult[j].bitmap) { | |
96 | if (msr_decode_mult[j].bitmap == 0xff) | |
97 | return 0; | |
98 | j++; | |
99 | } | |
100 | ||
101 | dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100)); | |
102 | ||
103 | return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100); | |
104 | } | |
105 | ||
106 | ||
107 | static unsigned int pentiumM_get_frequency(void) | |
108 | { | |
109 | u32 msr_lo, msr_tmp; | |
110 | ||
111 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
112 | dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); | |
113 | ||
114 | /* see table B-2 of 24547212.pdf */ | |
115 | if (msr_lo & 0x00040000) { | |
116 | printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | msr_tmp = (msr_lo >> 22) & 0x1f; | |
121 | dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000)); | |
122 | ||
123 | return (msr_tmp * 100 * 1000); | |
124 | } | |
125 | ||
126 | ||
127 | static unsigned int pentium4_get_frequency(void) | |
128 | { | |
129 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
130 | u32 msr_lo, msr_hi, mult; | |
131 | unsigned int fsb = 0; | |
132 | ||
133 | rdmsr(0x2c, msr_lo, msr_hi); | |
134 | ||
135 | dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); | |
136 | ||
137 | /* decode the FSB: see IA-32 Intel (C) Architecture Software | |
138 | * Developer's Manual, Volume 3: System Prgramming Guide, | |
139 | * revision #12 in Table B-1: MSRs in the Pentium 4 and | |
140 | * Intel Xeon Processors, on page B-4 and B-5. | |
141 | */ | |
142 | if (c->x86_model < 2) | |
143 | fsb = 100 * 1000; | |
144 | else { | |
145 | u8 fsb_code = (msr_lo >> 16) & 0x7; | |
146 | switch (fsb_code) { | |
147 | case 0: | |
148 | fsb = 100 * 1000; | |
149 | break; | |
150 | case 1: | |
151 | fsb = 13333 * 10; | |
152 | break; | |
153 | case 2: | |
154 | fsb = 200 * 1000; | |
155 | break; | |
156 | } | |
157 | } | |
158 | ||
159 | if (!fsb) | |
160 | printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n"); | |
161 | ||
162 | /* Multiplier. */ | |
163 | if (c->x86_model < 2) | |
164 | mult = msr_lo >> 27; | |
165 | else | |
166 | mult = msr_lo >> 24; | |
167 | ||
168 | dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult)); | |
169 | ||
170 | return (fsb * mult); | |
171 | } | |
172 | ||
173 | ||
174 | unsigned int speedstep_get_processor_frequency(unsigned int processor) | |
175 | { | |
176 | switch (processor) { | |
177 | case SPEEDSTEP_PROCESSOR_PM: | |
178 | return pentiumM_get_frequency(); | |
179 | case SPEEDSTEP_PROCESSOR_P4D: | |
180 | case SPEEDSTEP_PROCESSOR_P4M: | |
181 | return pentium4_get_frequency(); | |
182 | case SPEEDSTEP_PROCESSOR_PIII_T: | |
183 | case SPEEDSTEP_PROCESSOR_PIII_C: | |
184 | case SPEEDSTEP_PROCESSOR_PIII_C_EARLY: | |
185 | return pentium3_get_frequency(processor); | |
186 | default: | |
187 | return 0; | |
188 | }; | |
189 | return 0; | |
190 | } | |
191 | EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency); | |
192 | ||
193 | ||
194 | /********************************************************************* | |
195 | * DETECT SPEEDSTEP-CAPABLE PROCESSOR * | |
196 | *********************************************************************/ | |
197 | ||
198 | unsigned int speedstep_detect_processor (void) | |
199 | { | |
200 | struct cpuinfo_x86 *c = cpu_data; | |
201 | u32 ebx, msr_lo, msr_hi; | |
202 | ||
203 | dprintk("x86: %x, model: %x\n", c->x86, c->x86_model); | |
204 | ||
205 | if ((c->x86_vendor != X86_VENDOR_INTEL) || | |
206 | ((c->x86 != 6) && (c->x86 != 0xF))) | |
207 | return 0; | |
208 | ||
209 | if (c->x86 == 0xF) { | |
210 | /* Intel Mobile Pentium 4-M | |
211 | * or Intel Mobile Pentium 4 with 533 MHz FSB */ | |
212 | if (c->x86_model != 2) | |
213 | return 0; | |
214 | ||
215 | ebx = cpuid_ebx(0x00000001); | |
216 | ebx &= 0x000000FF; | |
217 | ||
218 | dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask); | |
219 | ||
220 | switch (c->x86_mask) { | |
221 | case 4: | |
222 | /* | |
223 | * B-stepping [M-P4-M] | |
224 | * sample has ebx = 0x0f, production has 0x0e. | |
225 | */ | |
226 | if ((ebx == 0x0e) || (ebx == 0x0f)) | |
227 | return SPEEDSTEP_PROCESSOR_P4M; | |
228 | break; | |
229 | case 7: | |
230 | /* | |
231 | * C-stepping [M-P4-M] | |
232 | * needs to have ebx=0x0e, else it's a celeron: | |
233 | * cf. 25130917.pdf / page 7, footnote 5 even | |
234 | * though 25072120.pdf / page 7 doesn't say | |
235 | * samples are only of B-stepping... | |
236 | */ | |
237 | if (ebx == 0x0e) | |
238 | return SPEEDSTEP_PROCESSOR_P4M; | |
239 | break; | |
240 | case 9: | |
241 | /* | |
242 | * D-stepping [M-P4-M or M-P4/533] | |
243 | * | |
244 | * this is totally strange: CPUID 0x0F29 is | |
245 | * used by M-P4-M, M-P4/533 and(!) Celeron CPUs. | |
246 | * The latter need to be sorted out as they don't | |
247 | * support speedstep. | |
248 | * Celerons with CPUID 0x0F29 may have either | |
249 | * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything | |
250 | * specific. | |
251 | * M-P4-Ms may have either ebx=0xe or 0xf [see above] | |
252 | * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf] | |
253 | * also, M-P4M HTs have ebx=0x8, too | |
254 | * For now, they are distinguished by the model_id string | |
255 | */ | |
256 | if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL)) | |
257 | return SPEEDSTEP_PROCESSOR_P4M; | |
258 | break; | |
259 | default: | |
260 | break; | |
261 | } | |
262 | return 0; | |
263 | } | |
264 | ||
265 | switch (c->x86_model) { | |
266 | case 0x0B: /* Intel PIII [Tualatin] */ | |
267 | /* cpuid_ebx(1) is 0x04 for desktop PIII, | |
268 | 0x06 for mobile PIII-M */ | |
269 | ebx = cpuid_ebx(0x00000001); | |
270 | dprintk("ebx is %x\n", ebx); | |
271 | ||
272 | ebx &= 0x000000FF; | |
273 | ||
274 | if (ebx != 0x06) | |
275 | return 0; | |
276 | ||
277 | /* So far all PIII-M processors support SpeedStep. See | |
278 | * Intel's 24540640.pdf of June 2003 | |
279 | */ | |
280 | ||
281 | return SPEEDSTEP_PROCESSOR_PIII_T; | |
282 | ||
283 | case 0x08: /* Intel PIII [Coppermine] */ | |
284 | ||
285 | /* all mobile PIII Coppermines have FSB 100 MHz | |
286 | * ==> sort out a few desktop PIIIs. */ | |
287 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); | |
288 | dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi); | |
289 | msr_lo &= 0x00c0000; | |
290 | if (msr_lo != 0x0080000) | |
291 | return 0; | |
292 | ||
293 | /* | |
294 | * If the processor is a mobile version, | |
295 | * platform ID has bit 50 set | |
296 | * it has SpeedStep technology if either | |
297 | * bit 56 or 57 is set | |
298 | */ | |
299 | rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); | |
300 | dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi); | |
301 | if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) { | |
302 | if (c->x86_mask == 0x01) { | |
303 | dprintk("early PIII version\n"); | |
304 | return SPEEDSTEP_PROCESSOR_PIII_C_EARLY; | |
305 | } else | |
306 | return SPEEDSTEP_PROCESSOR_PIII_C; | |
307 | } | |
308 | ||
309 | default: | |
310 | return 0; | |
311 | } | |
312 | } | |
313 | EXPORT_SYMBOL_GPL(speedstep_detect_processor); | |
314 | ||
315 | ||
316 | /********************************************************************* | |
317 | * DETECT SPEEDSTEP SPEEDS * | |
318 | *********************************************************************/ | |
319 | ||
320 | unsigned int speedstep_get_freqs(unsigned int processor, | |
321 | unsigned int *low_speed, | |
322 | unsigned int *high_speed, | |
1a10760c | 323 | unsigned int *transition_latency, |
1da177e4 LT |
324 | void (*set_state) (unsigned int state)) |
325 | { | |
326 | unsigned int prev_speed; | |
327 | unsigned int ret = 0; | |
328 | unsigned long flags; | |
1a10760c | 329 | struct timeval tv1, tv2; |
1da177e4 LT |
330 | |
331 | if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) | |
332 | return -EINVAL; | |
333 | ||
334 | dprintk("trying to determine both speeds\n"); | |
335 | ||
336 | /* get current speed */ | |
337 | prev_speed = speedstep_get_processor_frequency(processor); | |
338 | if (!prev_speed) | |
339 | return -EIO; | |
340 | ||
f94ea640 | 341 | dprintk("previous speed is %u\n", prev_speed); |
1a10760c | 342 | |
1da177e4 LT |
343 | local_irq_save(flags); |
344 | ||
345 | /* switch to low state */ | |
346 | set_state(SPEEDSTEP_LOW); | |
347 | *low_speed = speedstep_get_processor_frequency(processor); | |
348 | if (!*low_speed) { | |
349 | ret = -EIO; | |
350 | goto out; | |
351 | } | |
352 | ||
f94ea640 | 353 | dprintk("low speed is %u\n", *low_speed); |
1da177e4 | 354 | |
1a10760c MD |
355 | /* start latency measurement */ |
356 | if (transition_latency) | |
357 | do_gettimeofday(&tv1); | |
358 | ||
1da177e4 LT |
359 | /* switch to high state */ |
360 | set_state(SPEEDSTEP_HIGH); | |
1a10760c MD |
361 | |
362 | /* end latency measurement */ | |
363 | if (transition_latency) | |
364 | do_gettimeofday(&tv2); | |
365 | ||
1da177e4 LT |
366 | *high_speed = speedstep_get_processor_frequency(processor); |
367 | if (!*high_speed) { | |
368 | ret = -EIO; | |
369 | goto out; | |
370 | } | |
371 | ||
f94ea640 | 372 | dprintk("high speed is %u\n", *high_speed); |
1da177e4 LT |
373 | |
374 | if (*low_speed == *high_speed) { | |
375 | ret = -ENODEV; | |
376 | goto out; | |
377 | } | |
378 | ||
379 | /* switch to previous state, if necessary */ | |
380 | if (*high_speed != prev_speed) | |
381 | set_state(SPEEDSTEP_LOW); | |
382 | ||
1a10760c MD |
383 | if (transition_latency) { |
384 | *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC + | |
385 | tv2.tv_usec - tv1.tv_usec; | |
386 | dprintk("transition latency is %u uSec\n", *transition_latency); | |
387 | ||
388 | /* convert uSec to nSec and add 20% for safety reasons */ | |
389 | *transition_latency *= 1200; | |
390 | ||
391 | /* check if the latency measurement is too high or too low | |
392 | * and set it to a safe value (500uSec) in that case | |
393 | */ | |
394 | if (*transition_latency > 10000000 || *transition_latency < 50000) { | |
395 | printk (KERN_WARNING "speedstep: frequency transition measured seems out of " | |
396 | "range (%u nSec), falling back to a safe one of %u nSec.\n", | |
397 | *transition_latency, 500000); | |
398 | *transition_latency = 500000; | |
399 | } | |
400 | } | |
401 | ||
1da177e4 LT |
402 | out: |
403 | local_irq_restore(flags); | |
404 | return (ret); | |
405 | } | |
406 | EXPORT_SYMBOL_GPL(speedstep_get_freqs); | |
407 | ||
408 | #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK | |
409 | module_param(relaxed_check, int, 0444); | |
410 | MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability."); | |
411 | #endif | |
412 | ||
413 | MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>"); | |
414 | MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers."); | |
415 | MODULE_LICENSE ("GPL"); |