[deliverable/linux.git] / arch / i386 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/thread_info.h>
#include <linux/module.h>

#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/uaccess.h>

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
#endif

extern int trap_init_f00f_bug(void);

#ifdef CONFIG_X86_INTEL_USERCOPY
/*
 * Alignment at which movsl is preferred for bulk memory copies.
 */
struct movsl_mask movsl_mask __read_mostly;
#endif

void __cpuinit early_intel_workaround(struct cpuinfo_x86 *c)
{
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return;
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
}

/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */
 
int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}
	

/*
 * P4 Xeon errata 037 workaround.
 * Hardware prefetcher may cause stale data to be loaded into the cache.
 */
static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & (1<<9)) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= (1<<9);	/* Disable hw prefetching */
			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}
}


/*
 * find out the number of processor cores on the die
 */
static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return ((eax >> 26) + 1);
	else
		return 1;
}

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;
	char *p = NULL;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if ( c->x86 == 5 ) {
		static int f00f_workaround_enabled = 0;

		c->f00f_bug = 1;
		if ( !f00f_workaround_enabled ) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	select_idle_routine(c);
	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9 ) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
	}

	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_bit(X86_FEATURE_SEP, c->x86_capability);

	/* Names for the Pentium II/Celeron processors 
	   detectable only by also checking the cache size.
	   Dixon is NOT a Celeron. */
	if (c->x86 == 6) {
		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;
			
		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;
			
		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}
	}

	if ( p )
		strcpy(c->x86_model_id, p);
	
	c->x86_max_cores = num_cpu_cores(c);

	detect_ht(c);

	/* Work around errata */
	Intel_errata_workarounds(c);

#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

	if (c->x86 == 15)
		set_bit(X86_FEATURE_P4, c->x86_capability);
	if (c->x86 == 6) 
		set_bit(X86_FEATURE_P3, c->x86_capability);
	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
}


static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
	/* Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}

static struct cpu_dev intel_cpu_dev __cpuinitdata = {
	.c_vendor	= "Intel",
	.c_ident 	= { "GenuineIntel" },
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 
		  { 
			  [0] = "486 DX-25/33", 
			  [1] = "486 DX-50", 
			  [2] = "486 SX", 
			  [3] = "486 DX/2", 
			  [4] = "486 SL", 
			  [5] = "486 SX/2", 
			  [7] = "486 DX/2-WB", 
			  [8] = "486 DX/4", 
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  { 
			  [0] = "Pentium 60/66 A-step", 
			  [1] = "Pentium 60/66", 
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83", 
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200", 
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  { 
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro", 
			  [3] = "Pentium II (Klamath)", 
			  [4] = "Pentium II (Deschutes)", 
			  [5] = "Pentium II (Deschutes)", 
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)", 
			  [8] = "Pentium III (Coppermine)", 
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_init		= init_intel,
	.c_size_cache	= intel_size_cache,
};

__init int intel_cpu_init(void)
{
	cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
	return 0;
}

#ifndef CONFIG_X86_CMPXCHG
unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
{
	u8 prev;
	unsigned long flags;

	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	local_irq_save(flags);
	prev = *(u8 *)ptr;
	if (prev == old)
		*(u8 *)ptr = new;
	local_irq_restore(flags);
	return prev;
}
EXPORT_SYMBOL(cmpxchg_386_u8);

unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
{
	u16 prev;
	unsigned long flags;

	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	local_irq_save(flags);
	prev = *(u16 *)ptr;
	if (prev == old)
		*(u16 *)ptr = new;
	local_irq_restore(flags);
	return prev;
}
EXPORT_SYMBOL(cmpxchg_386_u16);

unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
{
	u32 prev;
	unsigned long flags;

	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	local_irq_save(flags);
	prev = *(u32 *)ptr;
	if (prev == old)
		*(u32 *)ptr = new;
	local_irq_restore(flags);
	return prev;
}
EXPORT_SYMBOL(cmpxchg_386_u32);
#endif

// arch_initcall(intel_cpu_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
	7	#include <linux/thread_info.h>
53e86b91	8	#include <linux/module.h>
1da177e4 LT	9
	10	#include <asm/processor.h>
	11	#include <asm/msr.h>
	12	#include <asm/uaccess.h>
	13
	14	#include "cpu.h"
	15
	16	#ifdef CONFIG_X86_LOCAL_APIC
	17	#include <asm/mpspec.h>
	18	#include <asm/apic.h>
	19	#include <mach_apic.h>
	20	#endif
	21
	22	extern int trap_init_f00f_bug(void);
	23
	24	#ifdef CONFIG_X86_INTEL_USERCOPY
	25	/*
	26	* Alignment at which movsl is preferred for bulk memory copies.
	27	*/
6c036527	28	struct movsl_mask movsl_mask __read_mostly;
1da177e4 LT	29	#endif
1da177e4 LT	30
3bc9b76b	31	void __cpuinit early_intel_workaround(struct cpuinfo_x86 *c)
1da177e4 LT	32	{
	33	if (c->x86_vendor != X86_VENDOR_INTEL)
	34	return;
	35	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	36	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	37	c->x86_cache_alignment = 128;
	38	}
	39
	40	/*
	41	* Early probe support logic for ppro memory erratum #50
	42	*
	43	* This is called before we do cpu ident work
	44	*/
	45
3bc9b76b	46	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	47	{
	48	/* Uses data from early_cpu_detect now */
	49	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	50	boot_cpu_data.x86 == 6 &&
	51	boot_cpu_data.x86_model == 1 &&
	52	boot_cpu_data.x86_mask < 8) {
	53	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	54	return 1;
	55	}
	56	return 0;
	57	}
	58
	59
	60	/*
	61	* P4 Xeon errata 037 workaround.
	62	* Hardware prefetcher may cause stale data to be loaded into the cache.
	63	*/
3bc9b76b	64	static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	65	{
	66	unsigned long lo, hi;
	67
	68	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
	69	rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	70	if ((lo & (1<<9)) == 0) {
	71	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
	72	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
	73	lo \|= (1<<9); /* Disable hw prefetching */
	74	wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	75	}
	76	}
	77	}
	78
	79
3dd9d514 AK	80	/*
	81	* find out the number of processor cores on the die
	82	*/
3bc9b76b	83	static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	84	{
f2ab4461	85	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	86
	87	if (c->cpuid_level < 4)
	88	return 1;
	89
f2ab4461 ZA	90	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	91	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 AK	92	if (eax & 0x1f)
	93	return ((eax >> 26) + 1);
	94	else
	95	return 1;
	96	}
	97
3bc9b76b	98	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	99	{
	100	unsigned int l2 = 0;
	101	char *p = NULL;
	102
	103	#ifdef CONFIG_X86_F00F_BUG
	104	/*
	105	* All current models of Pentium and Pentium with MMX technology CPUs
	106	* have the F0 0F bug, which lets nonprivileged users lock up the system.
	107	* Note that the workaround only should be initialized once...
	108	*/
	109	c->f00f_bug = 0;
	110	if ( c->x86 == 5 ) {
	111	static int f00f_workaround_enabled = 0;
	112
	113	c->f00f_bug = 1;
	114	if ( !f00f_workaround_enabled ) {
	115	trap_init_f00f_bug();
	116	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	117	f00f_workaround_enabled = 1;
	118	}
	119	}
	120	#endif
	121
	122	select_idle_routine(c);
	123	l2 = init_intel_cacheinfo(c);
0080e667 VP	124	if (c->cpuid_level > 9 ) {
	125	unsigned eax = cpuid_eax(10);
	126	/* Check for version and the number of counters */
	127	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
	128	set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
	129	}
1da177e4 LT	130
	131	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
	132	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	133	clear_bit(X86_FEATURE_SEP, c->x86_capability);
	134
	135	/* Names for the Pentium II/Celeron processors
	136	detectable only by also checking the cache size.
	137	Dixon is NOT a Celeron. */
	138	if (c->x86 == 6) {
	139	switch (c->x86_model) {
	140	case 5:
	141	if (c->x86_mask == 0) {
	142	if (l2 == 0)
	143	p = "Celeron (Covington)";
	144	else if (l2 == 256)
	145	p = "Mobile Pentium II (Dixon)";
	146	}
	147	break;
	148
	149	case 6:
	150	if (l2 == 128)
	151	p = "Celeron (Mendocino)";
	152	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	153	p = "Celeron-A";
	154	break;
	155
	156	case 8:
	157	if (l2 == 128)
	158	p = "Celeron (Coppermine)";
	159	break;
	160	}
	161	}
	162
	163	if ( p )
	164	strcpy(c->x86_model_id, p);
	165
94605eff	166	c->x86_max_cores = num_cpu_cores(c);
3dd9d514	167
1da177e4 LT	168	detect_ht(c);
	169
	170	/* Work around errata */
	171	Intel_errata_workarounds(c);
	172
	173	#ifdef CONFIG_X86_INTEL_USERCOPY
	174	/*
	175	* Set up the preferred alignment for movsl bulk memory moves
	176	*/
	177	switch (c->x86) {
	178	case 4: /* 486: untested */
	179	break;
	180	case 5: /* Old Pentia: untested */
	181	break;
	182	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	183	movsl_mask.mask = 7;
	184	break;
	185	case 15: /* P4 is OK down to 8-byte alignment */
	186	movsl_mask.mask = 7;
	187	break;
	188	}
	189	#endif
	190
39b3a791	191	if (c->x86 == 15)
1da177e4 LT	192	set_bit(X86_FEATURE_P4, c->x86_capability);
	193	if (c->x86 == 6)
	194	set_bit(X86_FEATURE_P3, c->x86_capability);
39b3a791 AK	195	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	196	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	197	set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
1da177e4 LT	198	}
	199
	200
	201	static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
	202	{
	203	/* Intel PIII Tualatin. This comes in two flavours.
	204	* One has 256kb of cache, the other 512. We have no way
	205	* to determine which, so we use a boottime override
	206	* for the 512kb model, and assume 256 otherwise.
	207	*/
	208	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	209	size = 256;
	210	return size;
	211	}
	212
3bc9b76b	213	static struct cpu_dev intel_cpu_dev __cpuinitdata = {
1da177e4 LT	214	.c_vendor = "Intel",
	215	.c_ident = { "GenuineIntel" },
	216	.c_models = {
	217	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	218	{
	219	[0] = "486 DX-25/33",
	220	[1] = "486 DX-50",
	221	[2] = "486 SX",
	222	[3] = "486 DX/2",
	223	[4] = "486 SL",
	224	[5] = "486 SX/2",
	225	[7] = "486 DX/2-WB",
	226	[8] = "486 DX/4",
	227	[9] = "486 DX/4-WB"
	228	}
	229	},
	230	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
	231	{
	232	[0] = "Pentium 60/66 A-step",
	233	[1] = "Pentium 60/66",
	234	[2] = "Pentium 75 - 200",
	235	[3] = "OverDrive PODP5V83",
	236	[4] = "Pentium MMX",
	237	[7] = "Mobile Pentium 75 - 200",
	238	[8] = "Mobile Pentium MMX"
	239	}
	240	},
	241	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
	242	{
	243	[0] = "Pentium Pro A-step",
	244	[1] = "Pentium Pro",
	245	[3] = "Pentium II (Klamath)",
	246	[4] = "Pentium II (Deschutes)",
	247	[5] = "Pentium II (Deschutes)",
	248	[6] = "Mobile Pentium II",
	249	[7] = "Pentium III (Katmai)",
	250	[8] = "Pentium III (Coppermine)",
	251	[10] = "Pentium III (Cascades)",
	252	[11] = "Pentium III (Tualatin)",
	253	}
	254	},
	255	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	256	{
	257	[0] = "Pentium 4 (Unknown)",
	258	[1] = "Pentium 4 (Willamette)",
	259	[2] = "Pentium 4 (Northwood)",
	260	[4] = "Pentium 4 (Foster)",
	261	[5] = "Pentium 4 (Foster)",
	262	}
	263	},
	264	},
	265	.c_init = init_intel,
1da177e4 LT	266	.c_size_cache = intel_size_cache,
	267	};
	268
	269	__init int intel_cpu_init(void)
	270	{
	271	cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
	272	return 0;
	273	}
	274
53e86b91 NP	275	#ifndef CONFIG_X86_CMPXCHG
	276	unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
	277	{
	278	u8 prev;
	279	unsigned long flags;
	280
	281	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	282	local_irq_save(flags);
	283	prev = (u8 )ptr;
	284	if (prev == old)
	285	(u8 )ptr = new;
	286	local_irq_restore(flags);
	287	return prev;
	288	}
	289	EXPORT_SYMBOL(cmpxchg_386_u8);
	290
	291	unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
	292	{
	293	u16 prev;
	294	unsigned long flags;
	295
	296	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	297	local_irq_save(flags);
	298	prev = (u16 )ptr;
	299	if (prev == old)
	300	(u16 )ptr = new;
	301	local_irq_restore(flags);
	302	return prev;
	303	}
	304	EXPORT_SYMBOL(cmpxchg_386_u16);
	305
	306	unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
	307	{
	308	u32 prev;
	309	unsigned long flags;
	310
	311	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	312	local_irq_save(flags);
	313	prev = (u32 )ptr;
	314	if (prev == old)
	315	(u32 )ptr = new;
	316	local_irq_restore(flags);
	317	return prev;
	318	}
	319	EXPORT_SYMBOL(cmpxchg_386_u32);
	320	#endif
	321
1da177e4 LT	322	// arch_initcall(intel_cpu_init);
1da177e4 LT	323