[deliverable/linux.git] / arch / i386 / kernel / cpu / intel.c

#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/thread_info.h>
#include <linux/module.h>

#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/uaccess.h>

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
#endif

extern int trap_init_f00f_bug(void);

#ifdef CONFIG_X86_INTEL_USERCOPY
/*
 * Alignment at which movsl is preferred for bulk memory copies.
 */
struct movsl_mask movsl_mask __read_mostly;
#endif

void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
{
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return;
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
}

/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */
 
int __devinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}
	

/*
 * P4 Xeon errata 037 workaround.
 * Hardware prefetcher may cause stale data to be loaded into the cache.
 */
static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & (1<<9)) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= (1<<9);	/* Disable hw prefetching */
			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}
}


/*
 * find out the number of processor cores on the die
 */
static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return ((eax >> 26) + 1);
	else
		return 1;
}

static void __devinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;
	char *p = NULL;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if ( c->x86 == 5 ) {
		static int f00f_workaround_enabled = 0;

		c->f00f_bug = 1;
		if ( !f00f_workaround_enabled ) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	select_idle_routine(c);
	l2 = init_intel_cacheinfo(c);

	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_bit(X86_FEATURE_SEP, c->x86_capability);

	/* Names for the Pentium II/Celeron processors 
	   detectable only by also checking the cache size.
	   Dixon is NOT a Celeron. */
	if (c->x86 == 6) {
		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;
			
		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;
			
		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}
	}

	if ( p )
		strcpy(c->x86_model_id, p);
	
	c->x86_max_cores = num_cpu_cores(c);

	detect_ht(c);

	/* Work around errata */
	Intel_errata_workarounds(c);

#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

	if (c->x86 == 15)
		set_bit(X86_FEATURE_P4, c->x86_capability);
	if (c->x86 == 6) 
		set_bit(X86_FEATURE_P3, c->x86_capability);
	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
}


static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
	/* Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}

static struct cpu_dev intel_cpu_dev __devinitdata = {
	.c_vendor	= "Intel",
	.c_ident 	= { "GenuineIntel" },
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 
		  { 
			  [0] = "486 DX-25/33", 
			  [1] = "486 DX-50", 
			  [2] = "486 SX", 
			  [3] = "486 DX/2", 
			  [4] = "486 SL", 
			  [5] = "486 SX/2", 
			  [7] = "486 DX/2-WB", 
			  [8] = "486 DX/4", 
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  { 
			  [0] = "Pentium 60/66 A-step", 
			  [1] = "Pentium 60/66", 
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83", 
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200", 
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  { 
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro", 
			  [3] = "Pentium II (Klamath)", 
			  [4] = "Pentium II (Deschutes)", 
			  [5] = "Pentium II (Deschutes)", 
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)", 
			  [8] = "Pentium III (Coppermine)", 
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_init		= init_intel,
	.c_identify	= generic_identify,
	.c_size_cache	= intel_size_cache,
};

__init int intel_cpu_init(void)
{
	cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
	return 0;
}

#ifndef CONFIG_X86_CMPXCHG
unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
{
	u8 prev;
	unsigned long flags;

	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	local_irq_save(flags);
	prev = *(u8 *)ptr;
	if (prev == old)
		*(u8 *)ptr = new;
	local_irq_restore(flags);
	return prev;
}
EXPORT_SYMBOL(cmpxchg_386_u8);

unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
{
	u16 prev;
	unsigned long flags;

	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	local_irq_save(flags);
	prev = *(u16 *)ptr;
	if (prev == old)
		*(u16 *)ptr = new;
	local_irq_restore(flags);
	return prev;
}
EXPORT_SYMBOL(cmpxchg_386_u16);

unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
{
	u32 prev;
	unsigned long flags;

	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	local_irq_save(flags);
	prev = *(u32 *)ptr;
	if (prev == old)
		*(u32 *)ptr = new;
	local_irq_restore(flags);
	return prev;
}
EXPORT_SYMBOL(cmpxchg_386_u32);
#endif

// arch_initcall(intel_cpu_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/config.h>
	2	#include <linux/init.h>
	3	#include <linux/kernel.h>
	4
	5	#include <linux/string.h>
	6	#include <linux/bitops.h>
	7	#include <linux/smp.h>
	8	#include <linux/thread_info.h>
53e86b91	9	#include <linux/module.h>
1da177e4 LT	10
	11	#include <asm/processor.h>
	12	#include <asm/msr.h>
	13	#include <asm/uaccess.h>
	14
	15	#include "cpu.h"
	16
	17	#ifdef CONFIG_X86_LOCAL_APIC
	18	#include <asm/mpspec.h>
	19	#include <asm/apic.h>
	20	#include <mach_apic.h>
	21	#endif
	22
	23	extern int trap_init_f00f_bug(void);
	24
	25	#ifdef CONFIG_X86_INTEL_USERCOPY
	26	/*
	27	* Alignment at which movsl is preferred for bulk memory copies.
	28	*/
6c036527	29	struct movsl_mask movsl_mask __read_mostly;
1da177e4 LT	30	#endif
1da177e4 LT	31
0bb3184d	32	void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
1da177e4 LT	33	{
	34	if (c->x86_vendor != X86_VENDOR_INTEL)
	35	return;
	36	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	37	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	38	c->x86_cache_alignment = 128;
	39	}
	40
	41	/*
	42	* Early probe support logic for ppro memory erratum #50
	43	*
	44	* This is called before we do cpu ident work
	45	*/
	46
0bb3184d	47	int __devinit ppro_with_ram_bug(void)
1da177e4 LT	48	{
	49	/* Uses data from early_cpu_detect now */
	50	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	51	boot_cpu_data.x86 == 6 &&
	52	boot_cpu_data.x86_model == 1 &&
	53	boot_cpu_data.x86_mask < 8) {
	54	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	55	return 1;
	56	}
	57	return 0;
	58	}
	59
	60
	61	/*
	62	* P4 Xeon errata 037 workaround.
	63	* Hardware prefetcher may cause stale data to be loaded into the cache.
	64	*/
0bb3184d	65	static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	66	{
	67	unsigned long lo, hi;
	68
	69	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
	70	rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	71	if ((lo & (1<<9)) == 0) {
	72	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
	73	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
	74	lo \|= (1<<9); /* Disable hw prefetching */
	75	wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	76	}
	77	}
	78	}
	79
	80
3dd9d514 AK	81	/*
	82	* find out the number of processor cores on the die
	83	*/
0bb3184d	84	static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	85	{
f2ab4461	86	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	87
	88	if (c->cpuid_level < 4)
	89	return 1;
	90
f2ab4461 ZA	91	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	92	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 AK	93	if (eax & 0x1f)
	94	return ((eax >> 26) + 1);
	95	else
	96	return 1;
	97	}
	98
0bb3184d	99	static void __devinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	100	{
	101	unsigned int l2 = 0;
	102	char *p = NULL;
	103
	104	#ifdef CONFIG_X86_F00F_BUG
	105	/*
	106	* All current models of Pentium and Pentium with MMX technology CPUs
	107	* have the F0 0F bug, which lets nonprivileged users lock up the system.
	108	* Note that the workaround only should be initialized once...
	109	*/
	110	c->f00f_bug = 0;
	111	if ( c->x86 == 5 ) {
	112	static int f00f_workaround_enabled = 0;
	113
	114	c->f00f_bug = 1;
	115	if ( !f00f_workaround_enabled ) {
	116	trap_init_f00f_bug();
	117	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	118	f00f_workaround_enabled = 1;
	119	}
	120	}
	121	#endif
	122
	123	select_idle_routine(c);
	124	l2 = init_intel_cacheinfo(c);
	125
	126	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
	127	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	128	clear_bit(X86_FEATURE_SEP, c->x86_capability);
	129
	130	/* Names for the Pentium II/Celeron processors
	131	detectable only by also checking the cache size.
	132	Dixon is NOT a Celeron. */
	133	if (c->x86 == 6) {
	134	switch (c->x86_model) {
	135	case 5:
	136	if (c->x86_mask == 0) {
	137	if (l2 == 0)
	138	p = "Celeron (Covington)";
	139	else if (l2 == 256)
	140	p = "Mobile Pentium II (Dixon)";
	141	}
	142	break;
	143
	144	case 6:
	145	if (l2 == 128)
	146	p = "Celeron (Mendocino)";
	147	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	148	p = "Celeron-A";
	149	break;
	150
	151	case 8:
	152	if (l2 == 128)
	153	p = "Celeron (Coppermine)";
	154	break;
	155	}
	156	}
	157
	158	if ( p )
	159	strcpy(c->x86_model_id, p);
	160
94605eff	161	c->x86_max_cores = num_cpu_cores(c);
3dd9d514	162
1da177e4 LT	163	detect_ht(c);
	164
	165	/* Work around errata */
	166	Intel_errata_workarounds(c);
	167
	168	#ifdef CONFIG_X86_INTEL_USERCOPY
	169	/*
	170	* Set up the preferred alignment for movsl bulk memory moves
	171	*/
	172	switch (c->x86) {
	173	case 4: /* 486: untested */
	174	break;
	175	case 5: /* Old Pentia: untested */
	176	break;
	177	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	178	movsl_mask.mask = 7;
	179	break;
	180	case 15: /* P4 is OK down to 8-byte alignment */
	181	movsl_mask.mask = 7;
	182	break;
	183	}
	184	#endif
	185
39b3a791	186	if (c->x86 == 15)
1da177e4 LT	187	set_bit(X86_FEATURE_P4, c->x86_capability);
	188	if (c->x86 == 6)
	189	set_bit(X86_FEATURE_P3, c->x86_capability);
39b3a791 AK	190	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	191	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	192	set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
1da177e4 LT	193	}
	194
	195
	196	static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
	197	{
	198	/* Intel PIII Tualatin. This comes in two flavours.
	199	* One has 256kb of cache, the other 512. We have no way
	200	* to determine which, so we use a boottime override
	201	* for the 512kb model, and assume 256 otherwise.
	202	*/
	203	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	204	size = 256;
	205	return size;
	206	}
	207
0bb3184d	208	static struct cpu_dev intel_cpu_dev __devinitdata = {
1da177e4 LT	209	.c_vendor = "Intel",
	210	.c_ident = { "GenuineIntel" },
	211	.c_models = {
	212	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	213	{
	214	[0] = "486 DX-25/33",
	215	[1] = "486 DX-50",
	216	[2] = "486 SX",
	217	[3] = "486 DX/2",
	218	[4] = "486 SL",
	219	[5] = "486 SX/2",
	220	[7] = "486 DX/2-WB",
	221	[8] = "486 DX/4",
	222	[9] = "486 DX/4-WB"
	223	}
	224	},
	225	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
	226	{
	227	[0] = "Pentium 60/66 A-step",
	228	[1] = "Pentium 60/66",
	229	[2] = "Pentium 75 - 200",
	230	[3] = "OverDrive PODP5V83",
	231	[4] = "Pentium MMX",
	232	[7] = "Mobile Pentium 75 - 200",
	233	[8] = "Mobile Pentium MMX"
	234	}
	235	},
	236	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
	237	{
	238	[0] = "Pentium Pro A-step",
	239	[1] = "Pentium Pro",
	240	[3] = "Pentium II (Klamath)",
	241	[4] = "Pentium II (Deschutes)",
	242	[5] = "Pentium II (Deschutes)",
	243	[6] = "Mobile Pentium II",
	244	[7] = "Pentium III (Katmai)",
	245	[8] = "Pentium III (Coppermine)",
	246	[10] = "Pentium III (Cascades)",
	247	[11] = "Pentium III (Tualatin)",
	248	}
	249	},
	250	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	251	{
	252	[0] = "Pentium 4 (Unknown)",
	253	[1] = "Pentium 4 (Willamette)",
	254	[2] = "Pentium 4 (Northwood)",
	255	[4] = "Pentium 4 (Foster)",
	256	[5] = "Pentium 4 (Foster)",
	257	}
	258	},
	259	},
	260	.c_init = init_intel,
	261	.c_identify = generic_identify,
	262	.c_size_cache = intel_size_cache,
	263	};
	264
	265	__init int intel_cpu_init(void)
	266	{
	267	cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
	268	return 0;
	269	}
	270
53e86b91 NP	271	#ifndef CONFIG_X86_CMPXCHG
	272	unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
	273	{
	274	u8 prev;
	275	unsigned long flags;
	276
	277	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	278	local_irq_save(flags);
	279	prev = (u8 )ptr;
	280	if (prev == old)
	281	(u8 )ptr = new;
	282	local_irq_restore(flags);
	283	return prev;
	284	}
	285	EXPORT_SYMBOL(cmpxchg_386_u8);
	286
	287	unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
	288	{
	289	u16 prev;
	290	unsigned long flags;
	291
	292	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	293	local_irq_save(flags);
	294	prev = (u16 )ptr;
	295	if (prev == old)
	296	(u16 )ptr = new;
	297	local_irq_restore(flags);
	298	return prev;
	299	}
	300	EXPORT_SYMBOL(cmpxchg_386_u16);
	301
	302	unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
	303	{
	304	u32 prev;
	305	unsigned long flags;
	306
	307	/* Poor man's cmpxchg for 386. Unsuitable for SMP */
	308	local_irq_save(flags);
	309	prev = (u32 )ptr;
	310	if (prev == old)
	311	(u32 )ptr = new;
	312	local_irq_restore(flags);
	313	return prev;
	314	}
	315	EXPORT_SYMBOL(cmpxchg_386_u32);
	316	#endif
	317
1da177e4 LT	318	// arch_initcall(intel_cpu_init);
1da177e4 LT	319