projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Athlon/Hammer specific Machine Check Exception Reporting | |
| 3 | * (C) Copyright 2002 Dave Jones <davej@codemonkey.org.uk> | |
| 4 | */ | |
| 5 | ||
| 6 | #include <linux/init.h> | |
| 7 | #include <linux/types.h> | |
| 8 | #include <linux/kernel.h> | |
| 9 | #include <linux/config.h> | |
| 1da177e4 LT |
10 | #include <linux/interrupt.h> |
| 11 | #include <linux/smp.h> | |
| 12 | ||
| 13 | #include <asm/processor.h> | |
| 14 | #include <asm/system.h> | |
| 15 | #include <asm/msr.h> | |
| 16 | ||
| 17 | #include "mce.h" | |
| 18 | ||
| 19 | /* Machine Check Handler For AMD Athlon/Duron */ | |
| 20 | static fastcall void k7_machine_check(struct pt_regs * regs, long error_code) | |
| 21 | { | |
| 22 | int recover=1; | |
| 23 | u32 alow, ahigh, high, low; | |
| 24 | u32 mcgstl, mcgsth; | |
| 25 | int i; | |
| 26 | ||
| 27 | rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth); | |
| 28 | if (mcgstl & (1<<0)) /* Recoverable ? */ | |
| 29 | recover=0; | |
| 30 | ||
| 31 | printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", | |
| 32 | smp_processor_id(), mcgsth, mcgstl); | |
| 33 | ||
| 34 | for (i=1; i<nr_mce_banks; i++) { | |
| 35 | rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high); | |
| 36 | if (high&(1<<31)) { | |
| 37 | if (high & (1<<29)) | |
| 38 | recover |= 1; | |
| 39 | if (high & (1<<25)) | |
| 40 | recover |= 2; | |
| 41 | printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low); | |
| 42 | high &= ~(1<<31); | |
| 43 | if (high & (1<<27)) { | |
| 44 | rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh); | |
| 45 | printk ("[%08x%08x]", ahigh, alow); | |
| 46 | } | |
| 47 | if (high & (1<<26)) { | |
| 48 | rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh); | |
| 49 | printk (" at %08x%08x", ahigh, alow); | |
| 50 | } | |
| 51 | printk ("\n"); | |
| 52 | /* Clear it */ | |
| 53 | wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL); | |
| 54 | /* Serialize */ | |
| 55 | wmb(); | |
| 56 | add_taint(TAINT_MACHINE_CHECK); | |
| 57 | } | |
| 58 | } | |
| 59 | ||
| 60 | if (recover&2) | |
| 61 | panic ("CPU context corrupt"); | |
| 62 | if (recover&1) | |
| 63 | panic ("Unable to continue"); | |
| 64 | printk (KERN_EMERG "Attempting to continue.\n"); | |
| 65 | mcgstl &= ~(1<<2); | |
| 66 | wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth); | |
| 67 | } | |
| 68 | ||
| 69 | ||
| 70 | /* AMD K7 machine check is Intel like */ | |
| 5a72e04d | 71 | void __devinit amd_mcheck_init(struct cpuinfo_x86 *c) |
| 1da177e4 LT |
72 | { |
| 73 | u32 l, h; | |
| 74 | int i; | |
| 75 | ||
| 76 | machine_check_vector = k7_machine_check; | |
| 77 | wmb(); | |
| 78 | ||
| 79 | printk (KERN_INFO "Intel machine check architecture supported.\n"); | |
| 80 | rdmsr (MSR_IA32_MCG_CAP, l, h); | |
| 81 | if (l & (1<<8)) /* Control register present ? */ | |
| 82 | wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
| 83 | nr_mce_banks = l & 0xff; | |
| 84 | ||
| 85 | /* Clear status for MC index 0 separately, we don't touch CTL, | |
| 86 | * as some Athlons cause spurious MCEs when its enabled. */ | |
| 87 | wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0); | |
| 88 | for (i=1; i<nr_mce_banks; i++) { | |
| 89 | wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); | |
| 90 | wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); | |
| 91 | } | |
| 92 | ||
| 93 | set_in_cr4 (X86_CR4_MCE); | |
| 94 | printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", | |
| 95 | smp_processor_id()); | |
| 96 | } |