[deliverable/linux.git] / arch / i386 / kernel / i8259.c

#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/smp_lock.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/bitops.h>

#include <asm/8253pit.h>
#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/timer.h>
#include <asm/pgtable.h>
#include <asm/delay.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/arch_hooks.h>
#include <asm/i8259.h>

#include <io_ports.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 * this file should become arch/i386/kernel/irq.c when the old irq.c
 * moves to arch independent land
 */

DEFINE_SPINLOCK(i8259A_lock);

static void end_8259A_irq (unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
							irq_desc[irq].action)
		enable_8259A_irq(irq);
}

#define shutdown_8259A_irq	disable_8259A_irq

static int i8259A_auto_eoi;

static void mask_and_ack_8259A(unsigned int);

unsigned int startup_8259A_irq(unsigned int irq)
{ 
	enable_8259A_irq(irq);
	return 0; /* never anything pending */
}

static struct hw_interrupt_type i8259A_irq_type = {
	.typename = "XT-PIC",
	.startup = startup_8259A_irq,
	.shutdown = shutdown_8259A_irq,
	.enable = enable_8259A_irq,
	.disable = disable_8259A_irq,
	.ack = mask_and_ack_8259A,
	.end = end_8259A_irq,
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

void disable_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	spin_unlock_irqrestore(&i8259A_lock, flags);
}

void enable_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	spin_unlock_irqrestore(&i8259A_lock, flags);
}

int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	irq_desc[irq].chip = &i8259A_irq_type;
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B,PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A,PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B,PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A,PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(unsigned int irq)
{
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
		outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq,PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static int i8259A_resume(struct sys_device *dev)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
	return 0;
}

static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
{
	save_ELCR(irq_trigger);
	return 0;
}

static int i8259A_shutdown(struct sys_device *dev)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-1 */
	return 0;
}

static struct sysdev_class i8259_sysdev_class = {
	set_kset_name("i8259"),
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static struct sys_device device_i8259A = {
	.id	= 0,
	.cls	= &i8259_sysdev_class,
};

static int __init i8259A_init_sysfs(void)
{
	int error = sysdev_class_register(&i8259_sysdev_class);
	if (!error)
		error = sysdev_register(&device_i8259A);
	return error;
}

device_initcall(i8259A_init_sysfs);

void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_p - this has to work on a wide range of PC hardware.
	 */
	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */
	outb_p(0x20 + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */
	if (auto_eoi)	/* master does Auto EOI */
		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */
	outb_p(0x20 + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */
	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	if (auto_eoi)
		/*
		 * in AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_irq_type.ack = disable_8259A_irq;
	else
		i8259A_irq_type.ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * Note that on a 486, we don't want to do a SIGFPE on an irq13
 * as the irq is unreliable, and exception 16 works correctly
 * (ie as explained in the intel literature). On a 386, you
 * can't use exception 16 due to bad IBM design, so we have to
 * rely on the less exact irq13.
 *
 * Careful.. Not only is IRQ13 unreliable, but it is also
 * leads to races. IBM designers who came up with it should
 * be shot.
 */
 

static irqreturn_t math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
{
	extern void math_error(void __user *);
	outb(0,0xF0);
	if (ignore_fpu_irq || !boot_cpu_data.hard_math)
		return IRQ_NONE;
	math_error((void __user *)regs->eip);
	return IRQ_HANDLED;
}

/*
 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
 * so allow interrupt sharing.
 */
static struct irqaction fpu_irq = { math_error_irq, 0, CPU_MASK_NONE, "fpu", NULL, NULL };

void __init init_ISA_irqs (void)
{
	int i;

#ifdef CONFIG_X86_LOCAL_APIC
	init_bsp_APIC();
#endif
	init_8259A(0);

	for (i = 0; i < NR_IRQS; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;

		if (i < 16) {
			/*
			 * 16 old-style INTA-cycle interrupts:
			 */
			irq_desc[i].chip = &i8259A_irq_type;
		} else {
			/*
			 * 'high' PCI IRQs filled in on demand
			 */
			irq_desc[i].chip = &no_irq_type;
		}
	}
}

void __init init_IRQ(void)
{
	int i;

	/* all the set up before the call gates are initialised */
	pre_intr_init_hook();

	/*
	 * Cover the whole vector space, no vector can escape
	 * us. (some of these will be overridden and become
	 * 'special' SMP interrupts)
	 */
	for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
		int vector = FIRST_EXTERNAL_VECTOR + i;
		if (i >= NR_IRQS)
			break;
		if (vector != SYSCALL_VECTOR) 
			set_intr_gate(vector, interrupt[i]);
	}

	/* setup after call gates are initialised (usually add in
	 * the architecture specific gates)
	 */
	intr_init_hook();

	/*
	 * Set the clock to HZ Hz, we already have a valid
	 * vector now:
	 */
	setup_pit_timer();

	/*
	 * External FPU? Set up irq13 if so, for
	 * original braindamaged IBM FERR coupling.
	 */
	if (boot_cpu_data.hard_math && !cpu_has_fpu)
		setup_irq(FPU_IRQ, &fpu_irq);

	irq_ctx_init(smp_processor_id());
}
Commit	Line	Data
1da177e4 LT	1	#include <linux/errno.h>
	2	#include <linux/signal.h>
	3	#include <linux/sched.h>
	4	#include <linux/ioport.h>
	5	#include <linux/interrupt.h>
	6	#include <linux/slab.h>
	7	#include <linux/random.h>
	8	#include <linux/smp_lock.h>
	9	#include <linux/init.h>
	10	#include <linux/kernel_stat.h>
	11	#include <linux/sysdev.h>
	12	#include <linux/bitops.h>
	13
	14	#include <asm/8253pit.h>
	15	#include <asm/atomic.h>
	16	#include <asm/system.h>
	17	#include <asm/io.h>
1da177e4 LT	18	#include <asm/timer.h>
	19	#include <asm/pgtable.h>
	20	#include <asm/delay.h>
	21	#include <asm/desc.h>
	22	#include <asm/apic.h>
	23	#include <asm/arch_hooks.h>
	24	#include <asm/i8259.h>
	25
1da177e4 LT	26	#include <io_ports.h>
	27
	28	/*
	29	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	30	* present in the majority of PC/AT boxes.
	31	* plus some generic x86 specific things if generic specifics makes
	32	* any sense at all.
	33	* this file should become arch/i386/kernel/irq.c when the old irq.c
	34	* moves to arch independent land
	35	*/
	36
	37	DEFINE_SPINLOCK(i8259A_lock);
	38
	39	static void end_8259A_irq (unsigned int irq)
	40	{
	41	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)) &&
	42	irq_desc[irq].action)
	43	enable_8259A_irq(irq);
	44	}
	45
	46	#define shutdown_8259A_irq disable_8259A_irq
	47
35d534a3 MG	48	static int i8259A_auto_eoi;
35d534a3 MG	49
1da177e4 LT	50	static void mask_and_ack_8259A(unsigned int);
	51
	52	unsigned int startup_8259A_irq(unsigned int irq)
	53	{
	54	enable_8259A_irq(irq);
	55	return 0; /* never anything pending */
	56	}
	57
	58	static struct hw_interrupt_type i8259A_irq_type = {
	59	.typename = "XT-PIC",
	60	.startup = startup_8259A_irq,
	61	.shutdown = shutdown_8259A_irq,
	62	.enable = enable_8259A_irq,
	63	.disable = disable_8259A_irq,
	64	.ack = mask_and_ack_8259A,
	65	.end = end_8259A_irq,
	66	};
	67
	68	/*
	69	* 8259A PIC functions to handle ISA devices:
	70	*/
	71
	72	/*
	73	* This contains the irq mask for both 8259A irq controllers,
	74	*/
	75	unsigned int cached_irq_mask = 0xffff;
	76
	77	/*
	78	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	79	* boards the timer interrupt is not really connected to any IO-APIC pin,
	80	* it's fed to the master 8259A's IR0 line only.
	81	*
	82	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	83	* this 'mixed mode' IRQ handling costs nothing because it's only used
	84	* at IRQ setup time.
	85	*/
	86	unsigned long io_apic_irqs;
	87
	88	void disable_8259A_irq(unsigned int irq)
	89	{
	90	unsigned int mask = 1 << irq;
	91	unsigned long flags;
	92
	93	spin_lock_irqsave(&i8259A_lock, flags);
	94	cached_irq_mask \|= mask;
	95	if (irq & 8)
	96	outb(cached_slave_mask, PIC_SLAVE_IMR);
	97	else
	98	outb(cached_master_mask, PIC_MASTER_IMR);
	99	spin_unlock_irqrestore(&i8259A_lock, flags);
	100	}
	101
	102	void enable_8259A_irq(unsigned int irq)
	103	{
	104	unsigned int mask = ~(1 << irq);
	105	unsigned long flags;
	106
	107	spin_lock_irqsave(&i8259A_lock, flags);
	108	cached_irq_mask &= mask;
	109	if (irq & 8)
	110	outb(cached_slave_mask, PIC_SLAVE_IMR);
	111	else
	112	outb(cached_master_mask, PIC_MASTER_IMR);
	113	spin_unlock_irqrestore(&i8259A_lock, flags);
114	}
115
116	int i8259A_irq_pending(unsigned int irq)
117	{
118	unsigned int mask = 1<<irq;
119	unsigned long flags;
120	int ret;
121
122	spin_lock_irqsave(&i8259A_lock, flags);
123	if (irq < 8)
124	ret = inb(PIC_MASTER_CMD) & mask;
125	else
126	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
127	spin_unlock_irqrestore(&i8259A_lock, flags);
128
129	return ret;
130	}
131
132	void make_8259A_irq(unsigned int irq)
133	{
134	disable_irq_nosync(irq);
135	io_apic_irqs &= ~(1<<irq);
d1bef4ed	136	irq_desc[irq].chip = &i8259A_irq_type;
1da177e4 LT	137	enable_irq(irq);
	138	}
	139
	140	/*
	141	* This function assumes to be called rarely. Switching between
	142	* 8259A registers is slow.
	143	* This has to be protected by the irq controller spinlock
	144	* before being called.
	145	*/
	146	static inline int i8259A_irq_real(unsigned int irq)
	147	{
	148	int value;
	149	int irqmask = 1<<irq;
	150
	151	if (irq < 8) {
	152	outb(0x0B,PIC_MASTER_CMD); /* ISR register */
	153	value = inb(PIC_MASTER_CMD) & irqmask;
	154	outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
	155	return value;
	156	}
	157	outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
	158	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	159	outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
	160	return value;
	161	}
	162
	163	/*
	164	* Careful! The 8259A is a fragile beast, it pretty
	165	* much _has_ to be done exactly like this (mask it
	166	* first, _then_ send the EOI, and the order of EOI
	167	* to the two 8259s is important!
	168	*/
	169	static void mask_and_ack_8259A(unsigned int irq)
	170	{
	171	unsigned int irqmask = 1 << irq;
	172	unsigned long flags;
	173
	174	spin_lock_irqsave(&i8259A_lock, flags);
	175	/*
	176	* Lightweight spurious IRQ detection. We do not want
	177	* to overdo spurious IRQ handling - it's usually a sign
	178	* of hardware problems, so we only do the checks we can
d6e05edc	179	* do without slowing down good hardware unnecessarily.
1da177e4 LT	180	*
	181	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	182	* usually resulting from the 8259A-1\|2 PICs) occur
	183	* even if the IRQ is masked in the 8259A. Thus we
	184	* can check spurious 8259A IRQs without doing the
	185	* quite slow i8259A_irq_real() call for every IRQ.
	186	* This does not cover 100% of spurious interrupts,
	187	* but should be enough to warn the user that there
	188	* is something bad going on ...
	189	*/
	190	if (cached_irq_mask & irqmask)
	191	goto spurious_8259A_irq;
	192	cached_irq_mask \|= irqmask;
	193
	194	handle_real_irq:
	195	if (irq & 8) {
	196	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	197	outb(cached_slave_mask, PIC_SLAVE_IMR);
	198	outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
	199	outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	200	} else {
	201	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	202	outb(cached_master_mask, PIC_MASTER_IMR);
	203	outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
	204	}
	205	spin_unlock_irqrestore(&i8259A_lock, flags);
	206	return;
	207
	208	spurious_8259A_irq:
	209	/*
	210	* this is the slow path - should happen rarely.
	211	*/
	212	if (i8259A_irq_real(irq))
	213	/*
	214	* oops, the IRQ _is_ in service according to the
	215	* 8259A - not spurious, go handle it.
	216	*/
	217	goto handle_real_irq;
	218
	219	{
	220	static int spurious_irq_mask;
	221	/*
	222	* At this point we can be sure the IRQ is spurious,
	223	* lets ACK and report it. [once per IRQ]
	224	*/
	225	if (!(spurious_irq_mask & irqmask)) {
	226	printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
	227	spurious_irq_mask \|= irqmask;
	228	}
	229	atomic_inc(&irq_err_count);
	230	/*
	231	* Theoretically we do not have to handle this IRQ,
	232	* but in Linux this does not cause problems and is
	233	* simpler for us.
	234	*/
	235	goto handle_real_irq;
	236	}
	237	}
	238
	239	static char irq_trigger[2];
	240	/**
	241	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	242	*/
	243	static void restore_ELCR(char *trigger)
244	{
245	outb(trigger[0], 0x4d0);
246	outb(trigger[1], 0x4d1);
247	}
248
249	static void save_ELCR(char *trigger)
250	{
251	/* IRQ 0,1,2,8,13 are marked as reserved */
252	trigger[0] = inb(0x4d0) & 0xF8;
253	trigger[1] = inb(0x4d1) & 0xDE;
254	}
255
256	static int i8259A_resume(struct sys_device *dev)
257	{
35d534a3	258	init_8259A(i8259A_auto_eoi);
1da177e4 LT	259	restore_ELCR(irq_trigger);
	260	return 0;
	261	}
	262
438510f6	263	static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	264	{
	265	save_ELCR(irq_trigger);
	266	return 0;
	267	}
	268
cee5dab4 EB	269	static int i8259A_shutdown(struct sys_device *dev)
	270	{
	271	/* Put the i8259A into a quiescent state that
	272	* the kernel initialization code can get it
	273	* out of.
	274	*/
110cb1d2 AM	275	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
110cb1d2 AM	276	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
cee5dab4 EB	277	return 0;
	278	}
	279
1da177e4 LT	280	static struct sysdev_class i8259_sysdev_class = {
	281	set_kset_name("i8259"),
	282	.suspend = i8259A_suspend,
	283	.resume = i8259A_resume,
cee5dab4	284	.shutdown = i8259A_shutdown,
1da177e4 LT	285	};
	286
	287	static struct sys_device device_i8259A = {
	288	.id = 0,
	289	.cls = &i8259_sysdev_class,
	290	};
	291
	292	static int __init i8259A_init_sysfs(void)
	293	{
	294	int error = sysdev_class_register(&i8259_sysdev_class);
	295	if (!error)
	296	error = sysdev_register(&device_i8259A);
	297	return error;
	298	}
	299
	300	device_initcall(i8259A_init_sysfs);
	301
	302	void init_8259A(int auto_eoi)
	303	{
	304	unsigned long flags;
	305
35d534a3 MG	306	i8259A_auto_eoi = auto_eoi;
35d534a3 MG	307
1da177e4 LT	308	spin_lock_irqsave(&i8259A_lock, flags);
	309
	310	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	311	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	312
	313	/*
	314	* outb_p - this has to work on a wide range of PC hardware.
	315	*/
	316	outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
	317	outb_p(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
	318	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
	319	if (auto_eoi) /* master does Auto EOI */
	320	outb_p(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	321	else /* master expects normal EOI */
	322	outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	323
	324	outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
	325	outb_p(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
	326	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
	327	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	328	if (auto_eoi)
	329	/*
	330	* in AEOI mode we just have to mask the interrupt
	331	* when acking.
	332	*/
	333	i8259A_irq_type.ack = disable_8259A_irq;
	334	else
	335	i8259A_irq_type.ack = mask_and_ack_8259A;
	336
	337	udelay(100); /* wait for 8259A to initialize */
	338
	339	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	340	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	341
	342	spin_unlock_irqrestore(&i8259A_lock, flags);
	343	}
	344
	345	/*
	346	* Note that on a 486, we don't want to do a SIGFPE on an irq13
	347	* as the irq is unreliable, and exception 16 works correctly
	348	* (ie as explained in the intel literature). On a 386, you
	349	* can't use exception 16 due to bad IBM design, so we have to
	350	* rely on the less exact irq13.
	351	*
	352	* Careful.. Not only is IRQ13 unreliable, but it is also
	353	* leads to races. IBM designers who came up with it should
	354	* be shot.
	355	*/
	356
	357
	358	static irqreturn_t math_error_irq(int cpl, void dev_id, struct pt_regs regs)
	359	{
	360	extern void math_error(void __user *);
	361	outb(0,0xF0);
	362	if (ignore_fpu_irq \|\| !boot_cpu_data.hard_math)
	363	return IRQ_NONE;
	364	math_error((void __user *)regs->eip);
	365	return IRQ_HANDLED;
	366	}
	367
	368	/*
	369	* New motherboards sometimes make IRQ 13 be a PCI interrupt,
	370	* so allow interrupt sharing.
	371	*/
372	static struct irqaction fpu_irq = { math_error_irq, 0, CPU_MASK_NONE, "fpu", NULL, NULL };
373
374	void __init init_ISA_irqs (void)
375	{
376	int i;
377
378	#ifdef CONFIG_X86_LOCAL_APIC
379	init_bsp_APIC();
380	#endif
381	init_8259A(0);
382
383	for (i = 0; i < NR_IRQS; i++) {
384	irq_desc[i].status = IRQ_DISABLED;
385	irq_desc[i].action = NULL;
386	irq_desc[i].depth = 1;
387
388	if (i < 16) {
389	/*
390	* 16 old-style INTA-cycle interrupts:
391	*/
d1bef4ed	392	irq_desc[i].chip = &i8259A_irq_type;
1da177e4 LT	393	} else {
	394	/*
	395	* 'high' PCI IRQs filled in on demand
	396	*/
d1bef4ed	397	irq_desc[i].chip = &no_irq_type;
1da177e4 LT	398	}
	399	}
	400	}
	401
	402	void __init init_IRQ(void)
	403	{
	404	int i;
	405
	406	/* all the set up before the call gates are initialised */
	407	pre_intr_init_hook();
	408
	409	/*
	410	* Cover the whole vector space, no vector can escape
	411	* us. (some of these will be overridden and become
	412	* 'special' SMP interrupts)
	413	*/
	414	for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
	415	int vector = FIRST_EXTERNAL_VECTOR + i;
	416	if (i >= NR_IRQS)
	417	break;
	418	if (vector != SYSCALL_VECTOR)
	419	set_intr_gate(vector, interrupt[i]);
	420	}
	421
	422	/* setup after call gates are initialised (usually add in
	423	* the architecture specific gates)
	424	*/
	425	intr_init_hook();
	426
	427	/*
	428	* Set the clock to HZ Hz, we already have a valid
	429	* vector now:
	430	*/
	431	setup_pit_timer();
	432
	433	/*
	434	* External FPU? Set up irq13 if so, for
	435	* original braindamaged IBM FERR coupling.
	436	*/
	437	if (boot_cpu_data.hard_math && !cpu_has_fpu)
	438	setup_irq(FPU_IRQ, &fpu_irq);
	439
	440	irq_ctx_init(smp_processor_id());
	441	}