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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/smp_lock.h> |
29 | #include <linux/mc146818rtc.h> | |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
54d5d424 | 38 | |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/smp.h> | |
41 | #include <asm/desc.h> | |
42 | #include <asm/timer.h> | |
306e440d | 43 | #include <asm/i8259.h> |
3e4ff115 | 44 | #include <asm/nmi.h> |
2d3fcc1c | 45 | #include <asm/msidef.h> |
8b955b0d | 46 | #include <asm/hypertransport.h> |
1da177e4 LT |
47 | |
48 | #include <mach_apic.h> | |
874c4fe3 | 49 | #include <mach_apicdef.h> |
1da177e4 LT |
50 | |
51 | #include "io_ports.h" | |
52 | ||
53 | int (*ioapic_renumber_irq)(int ioapic, int irq); | |
54 | atomic_t irq_mis_count; | |
55 | ||
fcfd636a EB |
56 | /* Where if anywhere is the i8259 connect in external int mode */ |
57 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
58 | ||
1da177e4 | 59 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 60 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 61 | |
f9262c12 AK |
62 | int timer_over_8254 __initdata = 1; |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Is the SiS APIC rmw bug present ? | |
66 | * -1 = don't know, 0 = no, 1 = yes | |
67 | */ | |
68 | int sis_apic_bug = -1; | |
69 | ||
70 | /* | |
71 | * # of IRQ routing registers | |
72 | */ | |
73 | int nr_ioapic_registers[MAX_IO_APICS]; | |
74 | ||
1a3f239d | 75 | static int disable_timer_pin_1 __initdata; |
66759a01 | 76 | |
1da177e4 LT |
77 | /* |
78 | * Rough estimation of how many shared IRQs there are, can | |
79 | * be changed anytime. | |
80 | */ | |
81 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
82 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
83 | ||
84 | /* | |
85 | * This is performance-critical, we want to do it O(1) | |
86 | * | |
87 | * the indexing order of this array favors 1:1 mappings | |
88 | * between pins and IRQs. | |
89 | */ | |
90 | ||
91 | static struct irq_pin_list { | |
92 | int apic, pin, next; | |
93 | } irq_2_pin[PIN_MAP_SIZE]; | |
94 | ||
130fe05d LT |
95 | struct io_apic { |
96 | unsigned int index; | |
97 | unsigned int unused[3]; | |
98 | unsigned int data; | |
99 | }; | |
100 | ||
101 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
102 | { | |
103 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
104 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); | |
105 | } | |
106 | ||
107 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
108 | { | |
109 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
110 | writel(reg, &io_apic->index); | |
111 | return readl(&io_apic->data); | |
112 | } | |
113 | ||
114 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
115 | { | |
116 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
117 | writel(reg, &io_apic->index); | |
118 | writel(value, &io_apic->data); | |
119 | } | |
120 | ||
121 | /* | |
122 | * Re-write a value: to be used for read-modify-write | |
123 | * cycles where the read already set up the index register. | |
124 | * | |
125 | * Older SiS APIC requires we rewrite the index register | |
126 | */ | |
127 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
128 | { | |
129 | volatile struct io_apic *io_apic = io_apic_base(apic); | |
130 | if (sis_apic_bug) | |
131 | writel(reg, &io_apic->index); | |
132 | writel(value, &io_apic->data); | |
133 | } | |
134 | ||
cf4c6a2f AK |
135 | union entry_union { |
136 | struct { u32 w1, w2; }; | |
137 | struct IO_APIC_route_entry entry; | |
138 | }; | |
139 | ||
140 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
141 | { | |
142 | union entry_union eu; | |
143 | unsigned long flags; | |
144 | spin_lock_irqsave(&ioapic_lock, flags); | |
145 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
146 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
147 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
148 | return eu.entry; | |
149 | } | |
150 | ||
f9dadfa7 LT |
151 | /* |
152 | * When we write a new IO APIC routing entry, we need to write the high | |
153 | * word first! If the mask bit in the low word is clear, we will enable | |
154 | * the interrupt, and we need to make sure the entry is fully populated | |
155 | * before that happens. | |
156 | */ | |
cf4c6a2f AK |
157 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
158 | { | |
159 | unsigned long flags; | |
160 | union entry_union eu; | |
161 | eu.entry = e; | |
f9dadfa7 LT |
162 | spin_lock_irqsave(&ioapic_lock, flags); |
163 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
164 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
165 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
166 | } | |
167 | ||
168 | /* | |
169 | * When we mask an IO APIC routing entry, we need to write the low | |
170 | * word first, in order to set the mask bit before we change the | |
171 | * high bits! | |
172 | */ | |
173 | static void ioapic_mask_entry(int apic, int pin) | |
174 | { | |
175 | unsigned long flags; | |
176 | union entry_union eu = { .entry.mask = 1 }; | |
177 | ||
cf4c6a2f AK |
178 | spin_lock_irqsave(&ioapic_lock, flags); |
179 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
180 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
181 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
182 | } | |
183 | ||
1da177e4 LT |
184 | /* |
185 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
186 | * shared ISA-space IRQs, so we have to support them. We are super | |
187 | * fast in the common case, and fast for shared ISA-space IRQs. | |
188 | */ | |
189 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
190 | { | |
191 | static int first_free_entry = NR_IRQS; | |
192 | struct irq_pin_list *entry = irq_2_pin + irq; | |
193 | ||
194 | while (entry->next) | |
195 | entry = irq_2_pin + entry->next; | |
196 | ||
197 | if (entry->pin != -1) { | |
198 | entry->next = first_free_entry; | |
199 | entry = irq_2_pin + entry->next; | |
200 | if (++first_free_entry >= PIN_MAP_SIZE) | |
201 | panic("io_apic.c: whoops"); | |
202 | } | |
203 | entry->apic = apic; | |
204 | entry->pin = pin; | |
205 | } | |
206 | ||
207 | /* | |
208 | * Reroute an IRQ to a different pin. | |
209 | */ | |
210 | static void __init replace_pin_at_irq(unsigned int irq, | |
211 | int oldapic, int oldpin, | |
212 | int newapic, int newpin) | |
213 | { | |
214 | struct irq_pin_list *entry = irq_2_pin + irq; | |
215 | ||
216 | while (1) { | |
217 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
218 | entry->apic = newapic; | |
219 | entry->pin = newpin; | |
220 | } | |
221 | if (!entry->next) | |
222 | break; | |
223 | entry = irq_2_pin + entry->next; | |
224 | } | |
225 | } | |
226 | ||
227 | static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) | |
228 | { | |
229 | struct irq_pin_list *entry = irq_2_pin + irq; | |
230 | unsigned int pin, reg; | |
231 | ||
232 | for (;;) { | |
233 | pin = entry->pin; | |
234 | if (pin == -1) | |
235 | break; | |
236 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
237 | reg &= ~disable; | |
238 | reg |= enable; | |
239 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
240 | if (!entry->next) | |
241 | break; | |
242 | entry = irq_2_pin + entry->next; | |
243 | } | |
244 | } | |
245 | ||
246 | /* mask = 1 */ | |
247 | static void __mask_IO_APIC_irq (unsigned int irq) | |
248 | { | |
249 | __modify_IO_APIC_irq(irq, 0x00010000, 0); | |
250 | } | |
251 | ||
252 | /* mask = 0 */ | |
253 | static void __unmask_IO_APIC_irq (unsigned int irq) | |
254 | { | |
255 | __modify_IO_APIC_irq(irq, 0, 0x00010000); | |
256 | } | |
257 | ||
258 | /* mask = 1, trigger = 0 */ | |
259 | static void __mask_and_edge_IO_APIC_irq (unsigned int irq) | |
260 | { | |
261 | __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); | |
262 | } | |
263 | ||
264 | /* mask = 0, trigger = 1 */ | |
265 | static void __unmask_and_level_IO_APIC_irq (unsigned int irq) | |
266 | { | |
267 | __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); | |
268 | } | |
269 | ||
270 | static void mask_IO_APIC_irq (unsigned int irq) | |
271 | { | |
272 | unsigned long flags; | |
273 | ||
274 | spin_lock_irqsave(&ioapic_lock, flags); | |
275 | __mask_IO_APIC_irq(irq); | |
276 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
277 | } | |
278 | ||
279 | static void unmask_IO_APIC_irq (unsigned int irq) | |
280 | { | |
281 | unsigned long flags; | |
282 | ||
283 | spin_lock_irqsave(&ioapic_lock, flags); | |
284 | __unmask_IO_APIC_irq(irq); | |
285 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
286 | } | |
287 | ||
288 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
289 | { | |
290 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
291 | |
292 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
cf4c6a2f | 293 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
294 | if (entry.delivery_mode == dest_SMI) |
295 | return; | |
296 | ||
297 | /* | |
298 | * Disable it in the IO-APIC irq-routing table: | |
299 | */ | |
f9dadfa7 | 300 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
301 | } |
302 | ||
303 | static void clear_IO_APIC (void) | |
304 | { | |
305 | int apic, pin; | |
306 | ||
307 | for (apic = 0; apic < nr_ioapics; apic++) | |
308 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
309 | clear_IO_APIC_pin(apic, pin); | |
310 | } | |
311 | ||
54d5d424 | 312 | #ifdef CONFIG_SMP |
1da177e4 LT |
313 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
314 | { | |
315 | unsigned long flags; | |
316 | int pin; | |
317 | struct irq_pin_list *entry = irq_2_pin + irq; | |
318 | unsigned int apicid_value; | |
54d5d424 | 319 | cpumask_t tmp; |
1da177e4 | 320 | |
54d5d424 AR |
321 | cpus_and(tmp, cpumask, cpu_online_map); |
322 | if (cpus_empty(tmp)) | |
323 | tmp = TARGET_CPUS; | |
324 | ||
325 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
326 | ||
1da177e4 LT |
327 | apicid_value = cpu_mask_to_apicid(cpumask); |
328 | /* Prepare to do the io_apic_write */ | |
329 | apicid_value = apicid_value << 24; | |
330 | spin_lock_irqsave(&ioapic_lock, flags); | |
331 | for (;;) { | |
332 | pin = entry->pin; | |
333 | if (pin == -1) | |
334 | break; | |
335 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
336 | if (!entry->next) | |
337 | break; | |
338 | entry = irq_2_pin + entry->next; | |
339 | } | |
ace80ab7 | 340 | set_native_irq_info(irq, cpumask); |
1da177e4 LT |
341 | spin_unlock_irqrestore(&ioapic_lock, flags); |
342 | } | |
343 | ||
344 | #if defined(CONFIG_IRQBALANCE) | |
345 | # include <asm/processor.h> /* kernel_thread() */ | |
346 | # include <linux/kernel_stat.h> /* kstat */ | |
347 | # include <linux/slab.h> /* kmalloc() */ | |
348 | # include <linux/timer.h> /* time_after() */ | |
349 | ||
1b61b910 | 350 | #ifdef CONFIG_BALANCED_IRQ_DEBUG |
1da177e4 LT |
351 | # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0) |
352 | # define Dprintk(x...) do { TDprintk(x); } while (0) | |
353 | # else | |
354 | # define TDprintk(x...) | |
355 | # define Dprintk(x...) | |
356 | # endif | |
357 | ||
1da177e4 | 358 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
359 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
360 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
361 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
362 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
363 | ||
364 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
365 | static int physical_balance __read_mostly; | |
366 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
367 | |
368 | static struct irq_cpu_info { | |
369 | unsigned long * last_irq; | |
370 | unsigned long * irq_delta; | |
371 | unsigned long irq; | |
372 | } irq_cpu_data[NR_CPUS]; | |
373 | ||
374 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
375 | #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) | |
376 | #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
377 | ||
378 | #define IDLE_ENOUGH(cpu,now) \ | |
379 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
380 | ||
381 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
382 | ||
383 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i])) | |
384 | ||
1b61b910 ZY |
385 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
386 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
387 | }; | |
1da177e4 | 388 | |
1b61b910 ZY |
389 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
390 | { | |
391 | balance_irq_affinity[irq] = mask; | |
392 | } | |
1da177e4 LT |
393 | |
394 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
395 | unsigned long now, int direction) | |
396 | { | |
397 | int search_idle = 1; | |
398 | int cpu = curr_cpu; | |
399 | ||
400 | goto inside; | |
401 | ||
402 | do { | |
403 | if (unlikely(cpu == curr_cpu)) | |
404 | search_idle = 0; | |
405 | inside: | |
406 | if (direction == 1) { | |
407 | cpu++; | |
408 | if (cpu >= NR_CPUS) | |
409 | cpu = 0; | |
410 | } else { | |
411 | cpu--; | |
412 | if (cpu == -1) | |
413 | cpu = NR_CPUS-1; | |
414 | } | |
415 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || | |
416 | (search_idle && !IDLE_ENOUGH(cpu,now))); | |
417 | ||
418 | return cpu; | |
419 | } | |
420 | ||
421 | static inline void balance_irq(int cpu, int irq) | |
422 | { | |
423 | unsigned long now = jiffies; | |
424 | cpumask_t allowed_mask; | |
425 | unsigned int new_cpu; | |
426 | ||
427 | if (irqbalance_disabled) | |
428 | return; | |
429 | ||
1b61b910 | 430 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 LT |
431 | new_cpu = move(cpu, allowed_mask, now, 1); |
432 | if (cpu != new_cpu) { | |
54d5d424 | 433 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
434 | } |
435 | } | |
436 | ||
437 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
438 | { | |
439 | int i, j; | |
440 | Dprintk("Rotating IRQs among CPUs.\n"); | |
394e3902 AM |
441 | for_each_online_cpu(i) { |
442 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
443 | if (!irq_desc[j].action) |
444 | continue; | |
445 | /* Is it a significant load ? */ | |
446 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < | |
447 | useful_load_threshold) | |
448 | continue; | |
449 | balance_irq(i, j); | |
450 | } | |
451 | } | |
452 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
453 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
454 | return; | |
455 | } | |
456 | ||
457 | static void do_irq_balance(void) | |
458 | { | |
459 | int i, j; | |
460 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
461 | unsigned long move_this_load = 0; | |
462 | int max_loaded = 0, min_loaded = 0; | |
463 | int load; | |
464 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
465 | int selected_irq; | |
466 | int tmp_loaded, first_attempt = 1; | |
467 | unsigned long tmp_cpu_irq; | |
468 | unsigned long imbalance = 0; | |
469 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
470 | ||
c8912599 | 471 | for_each_possible_cpu(i) { |
1da177e4 LT |
472 | int package_index; |
473 | CPU_IRQ(i) = 0; | |
474 | if (!cpu_online(i)) | |
475 | continue; | |
476 | package_index = CPU_TO_PACKAGEINDEX(i); | |
477 | for (j = 0; j < NR_IRQS; j++) { | |
478 | unsigned long value_now, delta; | |
479 | /* Is this an active IRQ? */ | |
480 | if (!irq_desc[j].action) | |
481 | continue; | |
482 | if ( package_index == i ) | |
483 | IRQ_DELTA(package_index,j) = 0; | |
484 | /* Determine the total count per processor per IRQ */ | |
485 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
486 | ||
487 | /* Determine the activity per processor per IRQ */ | |
488 | delta = value_now - LAST_CPU_IRQ(i,j); | |
489 | ||
490 | /* Update last_cpu_irq[][] for the next time */ | |
491 | LAST_CPU_IRQ(i,j) = value_now; | |
492 | ||
493 | /* Ignore IRQs whose rate is less than the clock */ | |
494 | if (delta < useful_load_threshold) | |
495 | continue; | |
496 | /* update the load for the processor or package total */ | |
497 | IRQ_DELTA(package_index,j) += delta; | |
498 | ||
499 | /* Keep track of the higher numbered sibling as well */ | |
500 | if (i != package_index) | |
501 | CPU_IRQ(i) += delta; | |
502 | /* | |
503 | * We have sibling A and sibling B in the package | |
504 | * | |
505 | * cpu_irq[A] = load for cpu A + load for cpu B | |
506 | * cpu_irq[B] = load for cpu B | |
507 | */ | |
508 | CPU_IRQ(package_index) += delta; | |
509 | } | |
510 | } | |
511 | /* Find the least loaded processor package */ | |
394e3902 | 512 | for_each_online_cpu(i) { |
1da177e4 LT |
513 | if (i != CPU_TO_PACKAGEINDEX(i)) |
514 | continue; | |
515 | if (min_cpu_irq > CPU_IRQ(i)) { | |
516 | min_cpu_irq = CPU_IRQ(i); | |
517 | min_loaded = i; | |
518 | } | |
519 | } | |
520 | max_cpu_irq = ULONG_MAX; | |
521 | ||
522 | tryanothercpu: | |
523 | /* Look for heaviest loaded processor. | |
524 | * We may come back to get the next heaviest loaded processor. | |
525 | * Skip processors with trivial loads. | |
526 | */ | |
527 | tmp_cpu_irq = 0; | |
528 | tmp_loaded = -1; | |
394e3902 | 529 | for_each_online_cpu(i) { |
1da177e4 LT |
530 | if (i != CPU_TO_PACKAGEINDEX(i)) |
531 | continue; | |
532 | if (max_cpu_irq <= CPU_IRQ(i)) | |
533 | continue; | |
534 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
535 | tmp_cpu_irq = CPU_IRQ(i); | |
536 | tmp_loaded = i; | |
537 | } | |
538 | } | |
539 | ||
540 | if (tmp_loaded == -1) { | |
541 | /* In the case of small number of heavy interrupt sources, | |
542 | * loading some of the cpus too much. We use Ingo's original | |
543 | * approach to rotate them around. | |
544 | */ | |
545 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
546 | rotate_irqs_among_cpus(useful_load_threshold); | |
547 | return; | |
548 | } | |
549 | goto not_worth_the_effort; | |
550 | } | |
551 | ||
552 | first_attempt = 0; /* heaviest search */ | |
553 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
554 | max_loaded = tmp_loaded; /* processor */ | |
555 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
556 | ||
557 | Dprintk("max_loaded cpu = %d\n", max_loaded); | |
558 | Dprintk("min_loaded cpu = %d\n", min_loaded); | |
559 | Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq); | |
560 | Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq); | |
561 | Dprintk("load imbalance = %lu\n", imbalance); | |
562 | ||
563 | /* if imbalance is less than approx 10% of max load, then | |
564 | * observe diminishing returns action. - quit | |
565 | */ | |
566 | if (imbalance < (max_cpu_irq >> 3)) { | |
567 | Dprintk("Imbalance too trivial\n"); | |
568 | goto not_worth_the_effort; | |
569 | } | |
570 | ||
571 | tryanotherirq: | |
572 | /* if we select an IRQ to move that can't go where we want, then | |
573 | * see if there is another one to try. | |
574 | */ | |
575 | move_this_load = 0; | |
576 | selected_irq = -1; | |
577 | for (j = 0; j < NR_IRQS; j++) { | |
578 | /* Is this an active IRQ? */ | |
579 | if (!irq_desc[j].action) | |
580 | continue; | |
581 | if (imbalance <= IRQ_DELTA(max_loaded,j)) | |
582 | continue; | |
583 | /* Try to find the IRQ that is closest to the imbalance | |
584 | * without going over. | |
585 | */ | |
586 | if (move_this_load < IRQ_DELTA(max_loaded,j)) { | |
587 | move_this_load = IRQ_DELTA(max_loaded,j); | |
588 | selected_irq = j; | |
589 | } | |
590 | } | |
591 | if (selected_irq == -1) { | |
592 | goto tryanothercpu; | |
593 | } | |
594 | ||
595 | imbalance = move_this_load; | |
596 | ||
597 | /* For physical_balance case, we accumlated both load | |
598 | * values in the one of the siblings cpu_irq[], | |
599 | * to use the same code for physical and logical processors | |
600 | * as much as possible. | |
601 | * | |
602 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
603 | * sibling A and sibling B in the slot for the lowest numbered | |
604 | * sibling (A), _AND_ the load for sibling B in the slot for | |
605 | * the higher numbered sibling. | |
606 | * | |
607 | * We seek the least loaded sibling by making the comparison | |
608 | * (A+B)/2 vs B | |
609 | */ | |
610 | load = CPU_IRQ(min_loaded) >> 1; | |
611 | for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) { | |
612 | if (load > CPU_IRQ(j)) { | |
613 | /* This won't change cpu_sibling_map[min_loaded] */ | |
614 | load = CPU_IRQ(j); | |
615 | min_loaded = j; | |
616 | } | |
617 | } | |
618 | ||
1b61b910 ZY |
619 | cpus_and(allowed_mask, |
620 | cpu_online_map, | |
621 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
622 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
623 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
624 | ||
625 | if (!cpus_empty(tmp)) { | |
1da177e4 LT |
626 | |
627 | Dprintk("irq = %d moved to cpu = %d\n", | |
628 | selected_irq, min_loaded); | |
629 | /* mark for change destination */ | |
54d5d424 AR |
630 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
631 | ||
1da177e4 LT |
632 | /* Since we made a change, come back sooner to |
633 | * check for more variation. | |
634 | */ | |
635 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
636 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
637 | return; | |
638 | } | |
639 | goto tryanotherirq; | |
640 | ||
641 | not_worth_the_effort: | |
642 | /* | |
643 | * if we did not find an IRQ to move, then adjust the time interval | |
644 | * upward | |
645 | */ | |
646 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
647 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); | |
648 | Dprintk("IRQ worth rotating not found\n"); | |
649 | return; | |
650 | } | |
651 | ||
652 | static int balanced_irq(void *unused) | |
653 | { | |
654 | int i; | |
655 | unsigned long prev_balance_time = jiffies; | |
656 | long time_remaining = balanced_irq_interval; | |
657 | ||
658 | daemonize("kirqd"); | |
659 | ||
660 | /* push everything to CPU 0 to give us a starting point. */ | |
661 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 662 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 663 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
664 | } |
665 | ||
666 | for ( ; ; ) { | |
52e6e630 | 667 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 668 | try_to_freeze(); |
1da177e4 LT |
669 | if (time_after(jiffies, |
670 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 671 | preempt_disable(); |
1da177e4 LT |
672 | do_irq_balance(); |
673 | prev_balance_time = jiffies; | |
674 | time_remaining = balanced_irq_interval; | |
f3705136 | 675 | preempt_enable(); |
1da177e4 LT |
676 | } |
677 | } | |
678 | return 0; | |
679 | } | |
680 | ||
681 | static int __init balanced_irq_init(void) | |
682 | { | |
683 | int i; | |
684 | struct cpuinfo_x86 *c; | |
685 | cpumask_t tmp; | |
686 | ||
687 | cpus_shift_right(tmp, cpu_online_map, 2); | |
688 | c = &boot_cpu_data; | |
689 | /* When not overwritten by the command line ask subarchitecture. */ | |
690 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
691 | irqbalance_disabled = NO_BALANCE_IRQ; | |
692 | if (irqbalance_disabled) | |
693 | return 0; | |
694 | ||
695 | /* disable irqbalance completely if there is only one processor online */ | |
696 | if (num_online_cpus() < 2) { | |
697 | irqbalance_disabled = 1; | |
698 | return 0; | |
699 | } | |
700 | /* | |
701 | * Enable physical balance only if more than 1 physical processor | |
702 | * is present | |
703 | */ | |
704 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
705 | physical_balance = 1; | |
706 | ||
394e3902 | 707 | for_each_online_cpu(i) { |
1da177e4 LT |
708 | irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
709 | irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
710 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { | |
711 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
712 | goto failed; | |
713 | } | |
714 | memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS); | |
715 | memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS); | |
716 | } | |
717 | ||
718 | printk(KERN_INFO "Starting balanced_irq\n"); | |
719 | if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) | |
720 | return 0; | |
721 | else | |
722 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); | |
723 | failed: | |
c8912599 | 724 | for_each_possible_cpu(i) { |
4ae6673e | 725 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 726 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 727 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 728 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
729 | } |
730 | return 0; | |
731 | } | |
732 | ||
733 | int __init irqbalance_disable(char *str) | |
734 | { | |
735 | irqbalance_disabled = 1; | |
9b41046c | 736 | return 1; |
1da177e4 LT |
737 | } |
738 | ||
739 | __setup("noirqbalance", irqbalance_disable); | |
740 | ||
1da177e4 | 741 | late_initcall(balanced_irq_init); |
1da177e4 | 742 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 743 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
744 | |
745 | #ifndef CONFIG_SMP | |
746 | void fastcall send_IPI_self(int vector) | |
747 | { | |
748 | unsigned int cfg; | |
749 | ||
750 | /* | |
751 | * Wait for idle. | |
752 | */ | |
753 | apic_wait_icr_idle(); | |
754 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
755 | /* | |
756 | * Send the IPI. The write to APIC_ICR fires this off. | |
757 | */ | |
758 | apic_write_around(APIC_ICR, cfg); | |
759 | } | |
760 | #endif /* !CONFIG_SMP */ | |
761 | ||
762 | ||
763 | /* | |
764 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
765 | * specific CPU-side IRQs. | |
766 | */ | |
767 | ||
768 | #define MAX_PIRQS 8 | |
769 | static int pirq_entries [MAX_PIRQS]; | |
770 | static int pirqs_enabled; | |
771 | int skip_ioapic_setup; | |
772 | ||
773 | static int __init ioapic_setup(char *str) | |
774 | { | |
775 | skip_ioapic_setup = 1; | |
776 | return 1; | |
777 | } | |
778 | ||
779 | __setup("noapic", ioapic_setup); | |
780 | ||
781 | static int __init ioapic_pirq_setup(char *str) | |
782 | { | |
783 | int i, max; | |
784 | int ints[MAX_PIRQS+1]; | |
785 | ||
786 | get_options(str, ARRAY_SIZE(ints), ints); | |
787 | ||
788 | for (i = 0; i < MAX_PIRQS; i++) | |
789 | pirq_entries[i] = -1; | |
790 | ||
791 | pirqs_enabled = 1; | |
792 | apic_printk(APIC_VERBOSE, KERN_INFO | |
793 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
794 | max = MAX_PIRQS; | |
795 | if (ints[0] < MAX_PIRQS) | |
796 | max = ints[0]; | |
797 | ||
798 | for (i = 0; i < max; i++) { | |
799 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
800 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
801 | /* | |
802 | * PIRQs are mapped upside down, usually. | |
803 | */ | |
804 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
805 | } | |
806 | return 1; | |
807 | } | |
808 | ||
809 | __setup("pirq=", ioapic_pirq_setup); | |
810 | ||
811 | /* | |
812 | * Find the IRQ entry number of a certain pin. | |
813 | */ | |
814 | static int find_irq_entry(int apic, int pin, int type) | |
815 | { | |
816 | int i; | |
817 | ||
818 | for (i = 0; i < mp_irq_entries; i++) | |
819 | if (mp_irqs[i].mpc_irqtype == type && | |
820 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
821 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
822 | mp_irqs[i].mpc_dstirq == pin) | |
823 | return i; | |
824 | ||
825 | return -1; | |
826 | } | |
827 | ||
828 | /* | |
829 | * Find the pin to which IRQ[irq] (ISA) is connected | |
830 | */ | |
fcfd636a | 831 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
832 | { |
833 | int i; | |
834 | ||
835 | for (i = 0; i < mp_irq_entries; i++) { | |
836 | int lbus = mp_irqs[i].mpc_srcbus; | |
837 | ||
838 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
839 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
840 | mp_bus_id_to_type[lbus] == MP_BUS_MCA || | |
841 | mp_bus_id_to_type[lbus] == MP_BUS_NEC98 | |
842 | ) && | |
843 | (mp_irqs[i].mpc_irqtype == type) && | |
844 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
845 | ||
846 | return mp_irqs[i].mpc_dstirq; | |
847 | } | |
848 | return -1; | |
849 | } | |
850 | ||
fcfd636a EB |
851 | static int __init find_isa_irq_apic(int irq, int type) |
852 | { | |
853 | int i; | |
854 | ||
855 | for (i = 0; i < mp_irq_entries; i++) { | |
856 | int lbus = mp_irqs[i].mpc_srcbus; | |
857 | ||
858 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
859 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
860 | mp_bus_id_to_type[lbus] == MP_BUS_MCA || | |
861 | mp_bus_id_to_type[lbus] == MP_BUS_NEC98 | |
862 | ) && | |
863 | (mp_irqs[i].mpc_irqtype == type) && | |
864 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
865 | break; | |
866 | } | |
867 | if (i < mp_irq_entries) { | |
868 | int apic; | |
869 | for(apic = 0; apic < nr_ioapics; apic++) { | |
870 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
871 | return apic; | |
872 | } | |
873 | } | |
874 | ||
875 | return -1; | |
876 | } | |
877 | ||
1da177e4 LT |
878 | /* |
879 | * Find a specific PCI IRQ entry. | |
880 | * Not an __init, possibly needed by modules | |
881 | */ | |
882 | static int pin_2_irq(int idx, int apic, int pin); | |
883 | ||
884 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
885 | { | |
886 | int apic, i, best_guess = -1; | |
887 | ||
888 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
889 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
890 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
891 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
892 | return -1; | |
893 | } | |
894 | for (i = 0; i < mp_irq_entries; i++) { | |
895 | int lbus = mp_irqs[i].mpc_srcbus; | |
896 | ||
897 | for (apic = 0; apic < nr_ioapics; apic++) | |
898 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
899 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
900 | break; | |
901 | ||
902 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && | |
903 | !mp_irqs[i].mpc_irqtype && | |
904 | (bus == lbus) && | |
905 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
906 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
907 | ||
908 | if (!(apic || IO_APIC_IRQ(irq))) | |
909 | continue; | |
910 | ||
911 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
912 | return irq; | |
913 | /* | |
914 | * Use the first all-but-pin matching entry as a | |
915 | * best-guess fuzzy result for broken mptables. | |
916 | */ | |
917 | if (best_guess < 0) | |
918 | best_guess = irq; | |
919 | } | |
920 | } | |
921 | return best_guess; | |
922 | } | |
129f6946 | 923 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
924 | |
925 | /* | |
926 | * This function currently is only a helper for the i386 smp boot process where | |
927 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
928 | * so mask in all cases should simply be TARGET_CPUS | |
929 | */ | |
54d5d424 | 930 | #ifdef CONFIG_SMP |
1da177e4 LT |
931 | void __init setup_ioapic_dest(void) |
932 | { | |
933 | int pin, ioapic, irq, irq_entry; | |
934 | ||
935 | if (skip_ioapic_setup == 1) | |
936 | return; | |
937 | ||
938 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
939 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
940 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
941 | if (irq_entry == -1) | |
942 | continue; | |
943 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
944 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
945 | } | |
946 | ||
947 | } | |
948 | } | |
54d5d424 | 949 | #endif |
1da177e4 LT |
950 | |
951 | /* | |
952 | * EISA Edge/Level control register, ELCR | |
953 | */ | |
954 | static int EISA_ELCR(unsigned int irq) | |
955 | { | |
956 | if (irq < 16) { | |
957 | unsigned int port = 0x4d0 + (irq >> 3); | |
958 | return (inb(port) >> (irq & 7)) & 1; | |
959 | } | |
960 | apic_printk(APIC_VERBOSE, KERN_INFO | |
961 | "Broken MPtable reports ISA irq %d\n", irq); | |
962 | return 0; | |
963 | } | |
964 | ||
965 | /* EISA interrupts are always polarity zero and can be edge or level | |
966 | * trigger depending on the ELCR value. If an interrupt is listed as | |
967 | * EISA conforming in the MP table, that means its trigger type must | |
968 | * be read in from the ELCR */ | |
969 | ||
970 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) | |
971 | #define default_EISA_polarity(idx) (0) | |
972 | ||
973 | /* ISA interrupts are always polarity zero edge triggered, | |
974 | * when listed as conforming in the MP table. */ | |
975 | ||
976 | #define default_ISA_trigger(idx) (0) | |
977 | #define default_ISA_polarity(idx) (0) | |
978 | ||
979 | /* PCI interrupts are always polarity one level triggered, | |
980 | * when listed as conforming in the MP table. */ | |
981 | ||
982 | #define default_PCI_trigger(idx) (1) | |
983 | #define default_PCI_polarity(idx) (1) | |
984 | ||
985 | /* MCA interrupts are always polarity zero level triggered, | |
986 | * when listed as conforming in the MP table. */ | |
987 | ||
988 | #define default_MCA_trigger(idx) (1) | |
989 | #define default_MCA_polarity(idx) (0) | |
990 | ||
991 | /* NEC98 interrupts are always polarity zero edge triggered, | |
992 | * when listed as conforming in the MP table. */ | |
993 | ||
994 | #define default_NEC98_trigger(idx) (0) | |
995 | #define default_NEC98_polarity(idx) (0) | |
996 | ||
997 | static int __init MPBIOS_polarity(int idx) | |
998 | { | |
999 | int bus = mp_irqs[idx].mpc_srcbus; | |
1000 | int polarity; | |
1001 | ||
1002 | /* | |
1003 | * Determine IRQ line polarity (high active or low active): | |
1004 | */ | |
1005 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
1006 | { | |
1007 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
1008 | { | |
1009 | switch (mp_bus_id_to_type[bus]) | |
1010 | { | |
1011 | case MP_BUS_ISA: /* ISA pin */ | |
1012 | { | |
1013 | polarity = default_ISA_polarity(idx); | |
1014 | break; | |
1015 | } | |
1016 | case MP_BUS_EISA: /* EISA pin */ | |
1017 | { | |
1018 | polarity = default_EISA_polarity(idx); | |
1019 | break; | |
1020 | } | |
1021 | case MP_BUS_PCI: /* PCI pin */ | |
1022 | { | |
1023 | polarity = default_PCI_polarity(idx); | |
1024 | break; | |
1025 | } | |
1026 | case MP_BUS_MCA: /* MCA pin */ | |
1027 | { | |
1028 | polarity = default_MCA_polarity(idx); | |
1029 | break; | |
1030 | } | |
1031 | case MP_BUS_NEC98: /* NEC 98 pin */ | |
1032 | { | |
1033 | polarity = default_NEC98_polarity(idx); | |
1034 | break; | |
1035 | } | |
1036 | default: | |
1037 | { | |
1038 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1039 | polarity = 1; | |
1040 | break; | |
1041 | } | |
1042 | } | |
1043 | break; | |
1044 | } | |
1045 | case 1: /* high active */ | |
1046 | { | |
1047 | polarity = 0; | |
1048 | break; | |
1049 | } | |
1050 | case 2: /* reserved */ | |
1051 | { | |
1052 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1053 | polarity = 1; | |
1054 | break; | |
1055 | } | |
1056 | case 3: /* low active */ | |
1057 | { | |
1058 | polarity = 1; | |
1059 | break; | |
1060 | } | |
1061 | default: /* invalid */ | |
1062 | { | |
1063 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1064 | polarity = 1; | |
1065 | break; | |
1066 | } | |
1067 | } | |
1068 | return polarity; | |
1069 | } | |
1070 | ||
1071 | static int MPBIOS_trigger(int idx) | |
1072 | { | |
1073 | int bus = mp_irqs[idx].mpc_srcbus; | |
1074 | int trigger; | |
1075 | ||
1076 | /* | |
1077 | * Determine IRQ trigger mode (edge or level sensitive): | |
1078 | */ | |
1079 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
1080 | { | |
1081 | case 0: /* conforms, ie. bus-type dependent */ | |
1082 | { | |
1083 | switch (mp_bus_id_to_type[bus]) | |
1084 | { | |
1085 | case MP_BUS_ISA: /* ISA pin */ | |
1086 | { | |
1087 | trigger = default_ISA_trigger(idx); | |
1088 | break; | |
1089 | } | |
1090 | case MP_BUS_EISA: /* EISA pin */ | |
1091 | { | |
1092 | trigger = default_EISA_trigger(idx); | |
1093 | break; | |
1094 | } | |
1095 | case MP_BUS_PCI: /* PCI pin */ | |
1096 | { | |
1097 | trigger = default_PCI_trigger(idx); | |
1098 | break; | |
1099 | } | |
1100 | case MP_BUS_MCA: /* MCA pin */ | |
1101 | { | |
1102 | trigger = default_MCA_trigger(idx); | |
1103 | break; | |
1104 | } | |
1105 | case MP_BUS_NEC98: /* NEC 98 pin */ | |
1106 | { | |
1107 | trigger = default_NEC98_trigger(idx); | |
1108 | break; | |
1109 | } | |
1110 | default: | |
1111 | { | |
1112 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1113 | trigger = 1; | |
1114 | break; | |
1115 | } | |
1116 | } | |
1117 | break; | |
1118 | } | |
1119 | case 1: /* edge */ | |
1120 | { | |
1121 | trigger = 0; | |
1122 | break; | |
1123 | } | |
1124 | case 2: /* reserved */ | |
1125 | { | |
1126 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1127 | trigger = 1; | |
1128 | break; | |
1129 | } | |
1130 | case 3: /* level */ | |
1131 | { | |
1132 | trigger = 1; | |
1133 | break; | |
1134 | } | |
1135 | default: /* invalid */ | |
1136 | { | |
1137 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1138 | trigger = 0; | |
1139 | break; | |
1140 | } | |
1141 | } | |
1142 | return trigger; | |
1143 | } | |
1144 | ||
1145 | static inline int irq_polarity(int idx) | |
1146 | { | |
1147 | return MPBIOS_polarity(idx); | |
1148 | } | |
1149 | ||
1150 | static inline int irq_trigger(int idx) | |
1151 | { | |
1152 | return MPBIOS_trigger(idx); | |
1153 | } | |
1154 | ||
1155 | static int pin_2_irq(int idx, int apic, int pin) | |
1156 | { | |
1157 | int irq, i; | |
1158 | int bus = mp_irqs[idx].mpc_srcbus; | |
1159 | ||
1160 | /* | |
1161 | * Debugging check, we are in big trouble if this message pops up! | |
1162 | */ | |
1163 | if (mp_irqs[idx].mpc_dstirq != pin) | |
1164 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
1165 | ||
1166 | switch (mp_bus_id_to_type[bus]) | |
1167 | { | |
1168 | case MP_BUS_ISA: /* ISA pin */ | |
1169 | case MP_BUS_EISA: | |
1170 | case MP_BUS_MCA: | |
1171 | case MP_BUS_NEC98: | |
1172 | { | |
1173 | irq = mp_irqs[idx].mpc_srcbusirq; | |
1174 | break; | |
1175 | } | |
1176 | case MP_BUS_PCI: /* PCI pin */ | |
1177 | { | |
1178 | /* | |
1179 | * PCI IRQs are mapped in order | |
1180 | */ | |
1181 | i = irq = 0; | |
1182 | while (i < apic) | |
1183 | irq += nr_ioapic_registers[i++]; | |
1184 | irq += pin; | |
1185 | ||
1186 | /* | |
1187 | * For MPS mode, so far only needed by ES7000 platform | |
1188 | */ | |
1189 | if (ioapic_renumber_irq) | |
1190 | irq = ioapic_renumber_irq(apic, irq); | |
1191 | ||
1192 | break; | |
1193 | } | |
1194 | default: | |
1195 | { | |
1196 | printk(KERN_ERR "unknown bus type %d.\n",bus); | |
1197 | irq = 0; | |
1198 | break; | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | /* | |
1203 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1204 | */ | |
1205 | if ((pin >= 16) && (pin <= 23)) { | |
1206 | if (pirq_entries[pin-16] != -1) { | |
1207 | if (!pirq_entries[pin-16]) { | |
1208 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1209 | "disabling PIRQ%d\n", pin-16); | |
1210 | } else { | |
1211 | irq = pirq_entries[pin-16]; | |
1212 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1213 | "using PIRQ%d -> IRQ %d\n", | |
1214 | pin-16, irq); | |
1215 | } | |
1216 | } | |
1217 | } | |
1218 | return irq; | |
1219 | } | |
1220 | ||
1221 | static inline int IO_APIC_irq_trigger(int irq) | |
1222 | { | |
1223 | int apic, idx, pin; | |
1224 | ||
1225 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1226 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1227 | idx = find_irq_entry(apic,pin,mp_INT); | |
1228 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
1229 | return irq_trigger(idx); | |
1230 | } | |
1231 | } | |
1232 | /* | |
1233 | * nonexistent IRQs are edge default | |
1234 | */ | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
6c231b7b | 1239 | u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1240 | |
ace80ab7 | 1241 | static int __assign_irq_vector(int irq) |
1da177e4 LT |
1242 | { |
1243 | static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; | |
0a1ad60d | 1244 | int vector; |
1da177e4 | 1245 | |
ace80ab7 | 1246 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1247 | |
b940d22d EB |
1248 | if (irq_vector[irq] > 0) |
1249 | return irq_vector[irq]; | |
ace80ab7 | 1250 | |
1da177e4 LT |
1251 | current_vector += 8; |
1252 | if (current_vector == SYSCALL_VECTOR) | |
ace80ab7 | 1253 | current_vector += 8; |
1da177e4 LT |
1254 | |
1255 | if (current_vector >= FIRST_SYSTEM_VECTOR) { | |
1256 | offset++; | |
ace80ab7 | 1257 | if (!(offset % 8)) |
1da177e4 LT |
1258 | return -ENOSPC; |
1259 | current_vector = FIRST_DEVICE_VECTOR + offset; | |
1260 | } | |
1261 | ||
0a1ad60d | 1262 | vector = current_vector; |
b940d22d | 1263 | irq_vector[irq] = vector; |
ace80ab7 EB |
1264 | |
1265 | return vector; | |
1266 | } | |
0a1ad60d | 1267 | |
ace80ab7 EB |
1268 | static int assign_irq_vector(int irq) |
1269 | { | |
1270 | unsigned long flags; | |
1271 | int vector; | |
1272 | ||
1273 | spin_lock_irqsave(&vector_lock, flags); | |
1274 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1275 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1276 | |
0a1ad60d | 1277 | return vector; |
1da177e4 | 1278 | } |
f5b9ed7a | 1279 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1280 | |
1281 | #define IOAPIC_AUTO -1 | |
1282 | #define IOAPIC_EDGE 0 | |
1283 | #define IOAPIC_LEVEL 1 | |
1284 | ||
d1bef4ed | 1285 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1286 | { |
6ebcc00e JB |
1287 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1288 | trigger == IOAPIC_LEVEL) | |
a460e745 IM |
1289 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1290 | handle_fasteoi_irq, "fasteoi"); | |
45c99533 EB |
1291 | else { |
1292 | irq_desc[irq].status |= IRQ_DELAYED_DISABLE; | |
a460e745 IM |
1293 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1294 | handle_edge_irq, "edge"); | |
45c99533 | 1295 | } |
ace80ab7 | 1296 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1297 | } |
1298 | ||
1299 | static void __init setup_IO_APIC_irqs(void) | |
1300 | { | |
1301 | struct IO_APIC_route_entry entry; | |
1302 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1303 | unsigned long flags; | |
1304 | ||
1305 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1306 | ||
1307 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1308 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1309 | ||
1310 | /* | |
1311 | * add it to the IO-APIC irq-routing table: | |
1312 | */ | |
1313 | memset(&entry,0,sizeof(entry)); | |
1314 | ||
1315 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1316 | entry.dest_mode = INT_DEST_MODE; | |
1317 | entry.mask = 0; /* enable IRQ */ | |
1318 | entry.dest.logical.logical_dest = | |
1319 | cpu_mask_to_apicid(TARGET_CPUS); | |
1320 | ||
1321 | idx = find_irq_entry(apic,pin,mp_INT); | |
1322 | if (idx == -1) { | |
1323 | if (first_notcon) { | |
1324 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1325 | " IO-APIC (apicid-pin) %d-%d", | |
1326 | mp_ioapics[apic].mpc_apicid, | |
1327 | pin); | |
1328 | first_notcon = 0; | |
1329 | } else | |
1330 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
1331 | mp_ioapics[apic].mpc_apicid, pin); | |
1332 | continue; | |
1333 | } | |
1334 | ||
1335 | entry.trigger = irq_trigger(idx); | |
1336 | entry.polarity = irq_polarity(idx); | |
1337 | ||
1338 | if (irq_trigger(idx)) { | |
1339 | entry.trigger = 1; | |
1340 | entry.mask = 1; | |
1341 | } | |
1342 | ||
1343 | irq = pin_2_irq(idx, apic, pin); | |
1344 | /* | |
1345 | * skip adding the timer int on secondary nodes, which causes | |
1346 | * a small but painful rift in the time-space continuum | |
1347 | */ | |
1348 | if (multi_timer_check(apic, irq)) | |
1349 | continue; | |
1350 | else | |
1351 | add_pin_to_irq(irq, apic, pin); | |
1352 | ||
1353 | if (!apic && !IO_APIC_IRQ(irq)) | |
1354 | continue; | |
1355 | ||
1356 | if (IO_APIC_IRQ(irq)) { | |
1357 | vector = assign_irq_vector(irq); | |
1358 | entry.vector = vector; | |
1359 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
1360 | ||
1361 | if (!apic && (irq < 16)) | |
1362 | disable_8259A_irq(irq); | |
1363 | } | |
cf4c6a2f | 1364 | ioapic_write_entry(apic, pin, entry); |
1da177e4 | 1365 | spin_lock_irqsave(&ioapic_lock, flags); |
54d5d424 | 1366 | set_native_irq_info(irq, TARGET_CPUS); |
1da177e4 LT |
1367 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1368 | } | |
1369 | } | |
1370 | ||
1371 | if (!first_notcon) | |
1372 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1373 | } | |
1374 | ||
1375 | /* | |
1376 | * Set up the 8259A-master output pin: | |
1377 | */ | |
fcfd636a | 1378 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
1379 | { |
1380 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
1381 | |
1382 | memset(&entry,0,sizeof(entry)); | |
1383 | ||
1384 | disable_8259A_irq(0); | |
1385 | ||
1386 | /* mask LVT0 */ | |
1387 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
1388 | ||
1389 | /* | |
1390 | * We use logical delivery to get the timer IRQ | |
1391 | * to the first CPU. | |
1392 | */ | |
1393 | entry.dest_mode = INT_DEST_MODE; | |
1394 | entry.mask = 0; /* unmask IRQ now */ | |
1395 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
1396 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1397 | entry.polarity = 0; | |
1398 | entry.trigger = 0; | |
1399 | entry.vector = vector; | |
1400 | ||
1401 | /* | |
1402 | * The timer IRQ doesn't have to know that behind the | |
1403 | * scene we have a 8259A-master in AEOI mode ... | |
1404 | */ | |
f5b9ed7a IM |
1405 | irq_desc[0].chip = &ioapic_chip; |
1406 | set_irq_handler(0, handle_edge_irq); | |
1da177e4 LT |
1407 | |
1408 | /* | |
1409 | * Add it to the IO-APIC irq-routing table: | |
1410 | */ | |
cf4c6a2f | 1411 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1412 | |
1413 | enable_8259A_irq(0); | |
1414 | } | |
1415 | ||
1416 | static inline void UNEXPECTED_IO_APIC(void) | |
1417 | { | |
1418 | } | |
1419 | ||
1420 | void __init print_IO_APIC(void) | |
1421 | { | |
1422 | int apic, i; | |
1423 | union IO_APIC_reg_00 reg_00; | |
1424 | union IO_APIC_reg_01 reg_01; | |
1425 | union IO_APIC_reg_02 reg_02; | |
1426 | union IO_APIC_reg_03 reg_03; | |
1427 | unsigned long flags; | |
1428 | ||
1429 | if (apic_verbosity == APIC_QUIET) | |
1430 | return; | |
1431 | ||
1432 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
1433 | for (i = 0; i < nr_ioapics; i++) | |
1434 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
1435 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
1436 | ||
1437 | /* | |
1438 | * We are a bit conservative about what we expect. We have to | |
1439 | * know about every hardware change ASAP. | |
1440 | */ | |
1441 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1442 | ||
1443 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1444 | ||
1445 | spin_lock_irqsave(&ioapic_lock, flags); | |
1446 | reg_00.raw = io_apic_read(apic, 0); | |
1447 | reg_01.raw = io_apic_read(apic, 1); | |
1448 | if (reg_01.bits.version >= 0x10) | |
1449 | reg_02.raw = io_apic_read(apic, 2); | |
1450 | if (reg_01.bits.version >= 0x20) | |
1451 | reg_03.raw = io_apic_read(apic, 3); | |
1452 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1453 | ||
1454 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
1455 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
1456 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1457 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1458 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1459 | if (reg_00.bits.ID >= get_physical_broadcast()) | |
1460 | UNEXPECTED_IO_APIC(); | |
1461 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) | |
1462 | UNEXPECTED_IO_APIC(); | |
1463 | ||
1464 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1465 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1466 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ | |
1467 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ | |
1468 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ | |
1469 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ | |
1470 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ | |
1471 | (reg_01.bits.entries != 0x2E) && | |
1472 | (reg_01.bits.entries != 0x3F) | |
1473 | ) | |
1474 | UNEXPECTED_IO_APIC(); | |
1475 | ||
1476 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1477 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1478 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ | |
1479 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ | |
1480 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ | |
1481 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ | |
1482 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ | |
1483 | ) | |
1484 | UNEXPECTED_IO_APIC(); | |
1485 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) | |
1486 | UNEXPECTED_IO_APIC(); | |
1487 | ||
1488 | /* | |
1489 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1490 | * but the value of reg_02 is read as the previous read register | |
1491 | * value, so ignore it if reg_02 == reg_01. | |
1492 | */ | |
1493 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1494 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1495 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1496 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) | |
1497 | UNEXPECTED_IO_APIC(); | |
1498 | } | |
1499 | ||
1500 | /* | |
1501 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1502 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1503 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1504 | */ | |
1505 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1506 | reg_03.raw != reg_01.raw) { | |
1507 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1508 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1509 | if (reg_03.bits.__reserved_1) | |
1510 | UNEXPECTED_IO_APIC(); | |
1511 | } | |
1512 | ||
1513 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1514 | ||
1515 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1516 | " Stat Dest Deli Vect: \n"); | |
1517 | ||
1518 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1519 | struct IO_APIC_route_entry entry; | |
1520 | ||
cf4c6a2f | 1521 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1522 | |
1523 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1524 | i, | |
1525 | entry.dest.logical.logical_dest, | |
1526 | entry.dest.physical.physical_dest | |
1527 | ); | |
1528 | ||
1529 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1530 | entry.mask, | |
1531 | entry.trigger, | |
1532 | entry.irr, | |
1533 | entry.polarity, | |
1534 | entry.delivery_status, | |
1535 | entry.dest_mode, | |
1536 | entry.delivery_mode, | |
1537 | entry.vector | |
1538 | ); | |
1539 | } | |
1540 | } | |
1da177e4 LT |
1541 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1542 | for (i = 0; i < NR_IRQS; i++) { | |
1543 | struct irq_pin_list *entry = irq_2_pin + i; | |
1544 | if (entry->pin < 0) | |
1545 | continue; | |
ace80ab7 | 1546 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1547 | for (;;) { |
1548 | printk("-> %d:%d", entry->apic, entry->pin); | |
1549 | if (!entry->next) | |
1550 | break; | |
1551 | entry = irq_2_pin + entry->next; | |
1552 | } | |
1553 | printk("\n"); | |
1554 | } | |
1555 | ||
1556 | printk(KERN_INFO ".................................... done.\n"); | |
1557 | ||
1558 | return; | |
1559 | } | |
1560 | ||
1561 | #if 0 | |
1562 | ||
1563 | static void print_APIC_bitfield (int base) | |
1564 | { | |
1565 | unsigned int v; | |
1566 | int i, j; | |
1567 | ||
1568 | if (apic_verbosity == APIC_QUIET) | |
1569 | return; | |
1570 | ||
1571 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1572 | for (i = 0; i < 8; i++) { | |
1573 | v = apic_read(base + i*0x10); | |
1574 | for (j = 0; j < 32; j++) { | |
1575 | if (v & (1<<j)) | |
1576 | printk("1"); | |
1577 | else | |
1578 | printk("0"); | |
1579 | } | |
1580 | printk("\n"); | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | void /*__init*/ print_local_APIC(void * dummy) | |
1585 | { | |
1586 | unsigned int v, ver, maxlvt; | |
1587 | ||
1588 | if (apic_verbosity == APIC_QUIET) | |
1589 | return; | |
1590 | ||
1591 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1592 | smp_processor_id(), hard_smp_processor_id()); | |
1593 | v = apic_read(APIC_ID); | |
1594 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); | |
1595 | v = apic_read(APIC_LVR); | |
1596 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1597 | ver = GET_APIC_VERSION(v); | |
1598 | maxlvt = get_maxlvt(); | |
1599 | ||
1600 | v = apic_read(APIC_TASKPRI); | |
1601 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1602 | ||
1603 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1604 | v = apic_read(APIC_ARBPRI); | |
1605 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1606 | v & APIC_ARBPRI_MASK); | |
1607 | v = apic_read(APIC_PROCPRI); | |
1608 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1609 | } | |
1610 | ||
1611 | v = apic_read(APIC_EOI); | |
1612 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1613 | v = apic_read(APIC_RRR); | |
1614 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1615 | v = apic_read(APIC_LDR); | |
1616 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1617 | v = apic_read(APIC_DFR); | |
1618 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1619 | v = apic_read(APIC_SPIV); | |
1620 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1621 | ||
1622 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1623 | print_APIC_bitfield(APIC_ISR); | |
1624 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1625 | print_APIC_bitfield(APIC_TMR); | |
1626 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1627 | print_APIC_bitfield(APIC_IRR); | |
1628 | ||
1629 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1630 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1631 | apic_write(APIC_ESR, 0); | |
1632 | v = apic_read(APIC_ESR); | |
1633 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1634 | } | |
1635 | ||
1636 | v = apic_read(APIC_ICR); | |
1637 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1638 | v = apic_read(APIC_ICR2); | |
1639 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1640 | ||
1641 | v = apic_read(APIC_LVTT); | |
1642 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1643 | ||
1644 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1645 | v = apic_read(APIC_LVTPC); | |
1646 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1647 | } | |
1648 | v = apic_read(APIC_LVT0); | |
1649 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1650 | v = apic_read(APIC_LVT1); | |
1651 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1652 | ||
1653 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1654 | v = apic_read(APIC_LVTERR); | |
1655 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1656 | } | |
1657 | ||
1658 | v = apic_read(APIC_TMICT); | |
1659 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1660 | v = apic_read(APIC_TMCCT); | |
1661 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1662 | v = apic_read(APIC_TDCR); | |
1663 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1664 | printk("\n"); | |
1665 | } | |
1666 | ||
1667 | void print_all_local_APICs (void) | |
1668 | { | |
1669 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1670 | } | |
1671 | ||
1672 | void /*__init*/ print_PIC(void) | |
1673 | { | |
1da177e4 LT |
1674 | unsigned int v; |
1675 | unsigned long flags; | |
1676 | ||
1677 | if (apic_verbosity == APIC_QUIET) | |
1678 | return; | |
1679 | ||
1680 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1681 | ||
1682 | spin_lock_irqsave(&i8259A_lock, flags); | |
1683 | ||
1684 | v = inb(0xa1) << 8 | inb(0x21); | |
1685 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1686 | ||
1687 | v = inb(0xa0) << 8 | inb(0x20); | |
1688 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1689 | ||
1690 | outb(0x0b,0xa0); | |
1691 | outb(0x0b,0x20); | |
1692 | v = inb(0xa0) << 8 | inb(0x20); | |
1693 | outb(0x0a,0xa0); | |
1694 | outb(0x0a,0x20); | |
1695 | ||
1696 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1697 | ||
1698 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1699 | ||
1700 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1701 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1702 | } | |
1703 | ||
1704 | #endif /* 0 */ | |
1705 | ||
1706 | static void __init enable_IO_APIC(void) | |
1707 | { | |
1708 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1709 | int i8259_apic, i8259_pin; |
1710 | int i, apic; | |
1da177e4 LT |
1711 | unsigned long flags; |
1712 | ||
1713 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1714 | irq_2_pin[i].pin = -1; | |
1715 | irq_2_pin[i].next = 0; | |
1716 | } | |
1717 | if (!pirqs_enabled) | |
1718 | for (i = 0; i < MAX_PIRQS; i++) | |
1719 | pirq_entries[i] = -1; | |
1720 | ||
1721 | /* | |
1722 | * The number of IO-APIC IRQ registers (== #pins): | |
1723 | */ | |
fcfd636a | 1724 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1725 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1726 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1727 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1728 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1729 | } | |
1730 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1731 | int pin; | |
1732 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1733 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1734 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1735 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1736 | |
1737 | ||
1738 | /* If the interrupt line is enabled and in ExtInt mode | |
1739 | * I have found the pin where the i8259 is connected. | |
1740 | */ | |
1741 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1742 | ioapic_i8259.apic = apic; | |
1743 | ioapic_i8259.pin = pin; | |
1744 | goto found_i8259; | |
1745 | } | |
1746 | } | |
1747 | } | |
1748 | found_i8259: | |
1749 | /* Look to see what if the MP table has reported the ExtINT */ | |
1750 | /* If we could not find the appropriate pin by looking at the ioapic | |
1751 | * the i8259 probably is not connected the ioapic but give the | |
1752 | * mptable a chance anyway. | |
1753 | */ | |
1754 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1755 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1756 | /* Trust the MP table if nothing is setup in the hardware */ | |
1757 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1758 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1759 | ioapic_i8259.pin = i8259_pin; | |
1760 | ioapic_i8259.apic = i8259_apic; | |
1761 | } | |
1762 | /* Complain if the MP table and the hardware disagree */ | |
1763 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1764 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1765 | { | |
1766 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1767 | } |
1768 | ||
1769 | /* | |
1770 | * Do not trust the IO-APIC being empty at bootup | |
1771 | */ | |
1772 | clear_IO_APIC(); | |
1773 | } | |
1774 | ||
1775 | /* | |
1776 | * Not an __init, needed by the reboot code | |
1777 | */ | |
1778 | void disable_IO_APIC(void) | |
1779 | { | |
1780 | /* | |
1781 | * Clear the IO-APIC before rebooting: | |
1782 | */ | |
1783 | clear_IO_APIC(); | |
1784 | ||
650927ef | 1785 | /* |
0b968d23 | 1786 | * If the i8259 is routed through an IOAPIC |
650927ef | 1787 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1788 | * so legacy interrupts can be delivered. |
650927ef | 1789 | */ |
fcfd636a | 1790 | if (ioapic_i8259.pin != -1) { |
650927ef | 1791 | struct IO_APIC_route_entry entry; |
650927ef EB |
1792 | |
1793 | memset(&entry, 0, sizeof(entry)); | |
1794 | entry.mask = 0; /* Enabled */ | |
1795 | entry.trigger = 0; /* Edge */ | |
1796 | entry.irr = 0; | |
1797 | entry.polarity = 0; /* High */ | |
1798 | entry.delivery_status = 0; | |
1799 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1800 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1801 | entry.vector = 0; |
76865c3f VG |
1802 | entry.dest.physical.physical_dest = |
1803 | GET_APIC_ID(apic_read(APIC_ID)); | |
650927ef EB |
1804 | |
1805 | /* | |
1806 | * Add it to the IO-APIC irq-routing table: | |
1807 | */ | |
cf4c6a2f | 1808 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1809 | } |
fcfd636a | 1810 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1811 | } |
1812 | ||
1813 | /* | |
1814 | * function to set the IO-APIC physical IDs based on the | |
1815 | * values stored in the MPC table. | |
1816 | * | |
1817 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1818 | */ | |
1819 | ||
1820 | #ifndef CONFIG_X86_NUMAQ | |
1821 | static void __init setup_ioapic_ids_from_mpc(void) | |
1822 | { | |
1823 | union IO_APIC_reg_00 reg_00; | |
1824 | physid_mask_t phys_id_present_map; | |
1825 | int apic; | |
1826 | int i; | |
1827 | unsigned char old_id; | |
1828 | unsigned long flags; | |
1829 | ||
ca05fea6 NP |
1830 | /* |
1831 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1832 | * no meaning without the serial APIC bus. | |
1833 | */ | |
7c5c1e42 SL |
1834 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1835 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1836 | return; |
1da177e4 LT |
1837 | /* |
1838 | * This is broken; anything with a real cpu count has to | |
1839 | * circumvent this idiocy regardless. | |
1840 | */ | |
1841 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1842 | ||
1843 | /* | |
1844 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1845 | */ | |
1846 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1847 | ||
1848 | /* Read the register 0 value */ | |
1849 | spin_lock_irqsave(&ioapic_lock, flags); | |
1850 | reg_00.raw = io_apic_read(apic, 0); | |
1851 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1852 | ||
1853 | old_id = mp_ioapics[apic].mpc_apicid; | |
1854 | ||
1855 | if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { | |
1856 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", | |
1857 | apic, mp_ioapics[apic].mpc_apicid); | |
1858 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1859 | reg_00.bits.ID); | |
1860 | mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; | |
1861 | } | |
1862 | ||
1da177e4 LT |
1863 | /* |
1864 | * Sanity check, is the ID really free? Every APIC in a | |
1865 | * system must have a unique ID or we get lots of nice | |
1866 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1867 | */ | |
1868 | if (check_apicid_used(phys_id_present_map, | |
1869 | mp_ioapics[apic].mpc_apicid)) { | |
1870 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", | |
1871 | apic, mp_ioapics[apic].mpc_apicid); | |
1872 | for (i = 0; i < get_physical_broadcast(); i++) | |
1873 | if (!physid_isset(i, phys_id_present_map)) | |
1874 | break; | |
1875 | if (i >= get_physical_broadcast()) | |
1876 | panic("Max APIC ID exceeded!\n"); | |
1877 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1878 | i); | |
1879 | physid_set(i, phys_id_present_map); | |
1880 | mp_ioapics[apic].mpc_apicid = i; | |
1881 | } else { | |
1882 | physid_mask_t tmp; | |
1883 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); | |
1884 | apic_printk(APIC_VERBOSE, "Setting %d in the " | |
1885 | "phys_id_present_map\n", | |
1886 | mp_ioapics[apic].mpc_apicid); | |
1887 | physids_or(phys_id_present_map, phys_id_present_map, tmp); | |
1888 | } | |
1889 | ||
1890 | ||
1891 | /* | |
1892 | * We need to adjust the IRQ routing table | |
1893 | * if the ID changed. | |
1894 | */ | |
1895 | if (old_id != mp_ioapics[apic].mpc_apicid) | |
1896 | for (i = 0; i < mp_irq_entries; i++) | |
1897 | if (mp_irqs[i].mpc_dstapic == old_id) | |
1898 | mp_irqs[i].mpc_dstapic | |
1899 | = mp_ioapics[apic].mpc_apicid; | |
1900 | ||
1901 | /* | |
1902 | * Read the right value from the MPC table and | |
1903 | * write it into the ID register. | |
1904 | */ | |
1905 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1906 | "...changing IO-APIC physical APIC ID to %d ...", | |
1907 | mp_ioapics[apic].mpc_apicid); | |
1908 | ||
1909 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; | |
1910 | spin_lock_irqsave(&ioapic_lock, flags); | |
1911 | io_apic_write(apic, 0, reg_00.raw); | |
1912 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1913 | ||
1914 | /* | |
1915 | * Sanity check | |
1916 | */ | |
1917 | spin_lock_irqsave(&ioapic_lock, flags); | |
1918 | reg_00.raw = io_apic_read(apic, 0); | |
1919 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1920 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) | |
1921 | printk("could not set ID!\n"); | |
1922 | else | |
1923 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1924 | } | |
1925 | } | |
1926 | #else | |
1927 | static void __init setup_ioapic_ids_from_mpc(void) { } | |
1928 | #endif | |
1929 | ||
1930 | /* | |
1931 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1932 | * about the timer IRQ. We do the following to work around the situation: | |
1933 | * | |
1934 | * - timer IRQ defaults to IO-APIC IRQ | |
1935 | * - if this function detects that timer IRQs are defunct, then we fall | |
1936 | * back to ISA timer IRQs | |
1937 | */ | |
1938 | static int __init timer_irq_works(void) | |
1939 | { | |
1940 | unsigned long t1 = jiffies; | |
1941 | ||
1942 | local_irq_enable(); | |
1943 | /* Let ten ticks pass... */ | |
1944 | mdelay((10 * 1000) / HZ); | |
1945 | ||
1946 | /* | |
1947 | * Expect a few ticks at least, to be sure some possible | |
1948 | * glue logic does not lock up after one or two first | |
1949 | * ticks in a non-ExtINT mode. Also the local APIC | |
1950 | * might have cached one ExtINT interrupt. Finally, at | |
1951 | * least one tick may be lost due to delays. | |
1952 | */ | |
1953 | if (jiffies - t1 > 4) | |
1954 | return 1; | |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | /* | |
1960 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1961 | * number of pending IRQ events unhandled. These cases are very rare, | |
1962 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1963 | * better to do it this way as thus we do not have to be aware of | |
1964 | * 'pending' interrupts in the IRQ path, except at this point. | |
1965 | */ | |
1966 | /* | |
1967 | * Edge triggered needs to resend any interrupt | |
1968 | * that was delayed but this is now handled in the device | |
1969 | * independent code. | |
1970 | */ | |
1971 | ||
1972 | /* | |
f5b9ed7a IM |
1973 | * Startup quirk: |
1974 | * | |
1da177e4 LT |
1975 | * Starting up a edge-triggered IO-APIC interrupt is |
1976 | * nasty - we need to make sure that we get the edge. | |
1977 | * If it is already asserted for some reason, we need | |
1978 | * return 1 to indicate that is was pending. | |
1979 | * | |
1980 | * This is not complete - we should be able to fake | |
1981 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1982 | * |
1983 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1984 | */ |
f5b9ed7a | 1985 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1986 | { |
1987 | int was_pending = 0; | |
1988 | unsigned long flags; | |
1989 | ||
1990 | spin_lock_irqsave(&ioapic_lock, flags); | |
1991 | if (irq < 16) { | |
1992 | disable_8259A_irq(irq); | |
1993 | if (i8259A_irq_pending(irq)) | |
1994 | was_pending = 1; | |
1995 | } | |
1996 | __unmask_IO_APIC_irq(irq); | |
1997 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1998 | ||
1999 | return was_pending; | |
2000 | } | |
2001 | ||
f5b9ed7a | 2002 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 2003 | { |
ace80ab7 | 2004 | move_native_irq(irq); |
1da177e4 LT |
2005 | ack_APIC_irq(); |
2006 | } | |
2007 | ||
f5b9ed7a | 2008 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
2009 | { |
2010 | unsigned long v; | |
2011 | int i; | |
2012 | ||
ace80ab7 | 2013 | move_native_irq(irq); |
1da177e4 LT |
2014 | /* |
2015 | * It appears there is an erratum which affects at least version 0x11 | |
2016 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2017 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2018 | * erroneously delivered as edge-triggered one but the respective IRR | |
2019 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2020 | * message but it will never arrive and further interrupts are blocked | |
2021 | * from the source. The exact reason is so far unknown, but the | |
2022 | * phenomenon was observed when two consecutive interrupt requests | |
2023 | * from a given source get delivered to the same CPU and the source is | |
2024 | * temporarily disabled in between. | |
2025 | * | |
2026 | * A workaround is to simulate an EOI message manually. We achieve it | |
2027 | * by setting the trigger mode to edge and then to level when the edge | |
2028 | * trigger mode gets detected in the TMR of a local APIC for a | |
2029 | * level-triggered interrupt. We mask the source for the time of the | |
2030 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2031 | * The idea is from Manfred Spraul. --macro | |
2032 | */ | |
b940d22d | 2033 | i = irq_vector[irq]; |
1da177e4 LT |
2034 | |
2035 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2036 | ||
2037 | ack_APIC_irq(); | |
2038 | ||
2039 | if (!(v & (1 << (i & 0x1f)))) { | |
2040 | atomic_inc(&irq_mis_count); | |
2041 | spin_lock(&ioapic_lock); | |
2042 | __mask_and_edge_IO_APIC_irq(irq); | |
2043 | __unmask_and_level_IO_APIC_irq(irq); | |
2044 | spin_unlock(&ioapic_lock); | |
2045 | } | |
2046 | } | |
2047 | ||
ace80ab7 | 2048 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2049 | { |
b940d22d | 2050 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
2051 | |
2052 | return 1; | |
2053 | } | |
2054 | ||
f5b9ed7a IM |
2055 | static struct irq_chip ioapic_chip __read_mostly = { |
2056 | .name = "IO-APIC", | |
ace80ab7 EB |
2057 | .startup = startup_ioapic_irq, |
2058 | .mask = mask_IO_APIC_irq, | |
2059 | .unmask = unmask_IO_APIC_irq, | |
2060 | .ack = ack_ioapic_irq, | |
2061 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 2062 | #ifdef CONFIG_SMP |
ace80ab7 | 2063 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2064 | #endif |
ace80ab7 | 2065 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2066 | }; |
2067 | ||
1da177e4 LT |
2068 | |
2069 | static inline void init_IO_APIC_traps(void) | |
2070 | { | |
2071 | int irq; | |
2072 | ||
2073 | /* | |
2074 | * NOTE! The local APIC isn't very good at handling | |
2075 | * multiple interrupts at the same interrupt level. | |
2076 | * As the interrupt level is determined by taking the | |
2077 | * vector number and shifting that right by 4, we | |
2078 | * want to spread these out a bit so that they don't | |
2079 | * all fall in the same interrupt level. | |
2080 | * | |
2081 | * Also, we've got to be careful not to trash gate | |
2082 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2083 | */ | |
2084 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
2085 | int tmp = irq; | |
b940d22d | 2086 | if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) { |
1da177e4 LT |
2087 | /* |
2088 | * Hmm.. We don't have an entry for this, | |
2089 | * so default to an old-fashioned 8259 | |
2090 | * interrupt if we can.. | |
2091 | */ | |
2092 | if (irq < 16) | |
2093 | make_8259A_irq(irq); | |
2094 | else | |
2095 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2096 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2097 | } |
2098 | } | |
2099 | } | |
2100 | ||
f5b9ed7a IM |
2101 | /* |
2102 | * The local APIC irq-chip implementation: | |
2103 | */ | |
1da177e4 | 2104 | |
f5b9ed7a IM |
2105 | static void ack_apic(unsigned int irq) |
2106 | { | |
2107 | ack_APIC_irq(); | |
1da177e4 LT |
2108 | } |
2109 | ||
f5b9ed7a | 2110 | static void mask_lapic_irq (unsigned int irq) |
1da177e4 LT |
2111 | { |
2112 | unsigned long v; | |
2113 | ||
2114 | v = apic_read(APIC_LVT0); | |
2115 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
2116 | } | |
2117 | ||
f5b9ed7a | 2118 | static void unmask_lapic_irq (unsigned int irq) |
1da177e4 | 2119 | { |
f5b9ed7a | 2120 | unsigned long v; |
1da177e4 | 2121 | |
f5b9ed7a IM |
2122 | v = apic_read(APIC_LVT0); |
2123 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
2124 | } | |
1da177e4 | 2125 | |
f5b9ed7a IM |
2126 | static struct irq_chip lapic_chip __read_mostly = { |
2127 | .name = "local-APIC-edge", | |
2128 | .mask = mask_lapic_irq, | |
2129 | .unmask = unmask_lapic_irq, | |
2130 | .eoi = ack_apic, | |
1da177e4 LT |
2131 | }; |
2132 | ||
2133 | static void setup_nmi (void) | |
2134 | { | |
2135 | /* | |
2136 | * Dirty trick to enable the NMI watchdog ... | |
2137 | * We put the 8259A master into AEOI mode and | |
2138 | * unmask on all local APICs LVT0 as NMI. | |
2139 | * | |
2140 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2141 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2142 | * the NMI handler or the timer interrupt. | |
2143 | */ | |
2144 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); | |
2145 | ||
2146 | on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1); | |
2147 | ||
2148 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2149 | } | |
2150 | ||
2151 | /* | |
2152 | * This looks a bit hackish but it's about the only one way of sending | |
2153 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2154 | * not support the ExtINT mode, unfortunately. We need to send these | |
2155 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2156 | * 8259A interrupt line asserted until INTA. --macro | |
2157 | */ | |
2158 | static inline void unlock_ExtINT_logic(void) | |
2159 | { | |
fcfd636a | 2160 | int apic, pin, i; |
1da177e4 LT |
2161 | struct IO_APIC_route_entry entry0, entry1; |
2162 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2163 | |
fcfd636a EB |
2164 | pin = find_isa_irq_pin(8, mp_INT); |
2165 | apic = find_isa_irq_apic(8, mp_INT); | |
1da177e4 LT |
2166 | if (pin == -1) |
2167 | return; | |
2168 | ||
cf4c6a2f | 2169 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2170 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2171 | |
2172 | memset(&entry1, 0, sizeof(entry1)); | |
2173 | ||
2174 | entry1.dest_mode = 0; /* physical delivery */ | |
2175 | entry1.mask = 0; /* unmask IRQ now */ | |
2176 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2177 | entry1.delivery_mode = dest_ExtINT; | |
2178 | entry1.polarity = entry0.polarity; | |
2179 | entry1.trigger = 0; | |
2180 | entry1.vector = 0; | |
2181 | ||
cf4c6a2f | 2182 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2183 | |
2184 | save_control = CMOS_READ(RTC_CONTROL); | |
2185 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2186 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2187 | RTC_FREQ_SELECT); | |
2188 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2189 | ||
2190 | i = 100; | |
2191 | while (i-- > 0) { | |
2192 | mdelay(10); | |
2193 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2194 | i -= 10; | |
2195 | } | |
2196 | ||
2197 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2198 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2199 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2200 | |
cf4c6a2f | 2201 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2202 | } |
2203 | ||
e0c1e9bf KM |
2204 | int timer_uses_ioapic_pin_0; |
2205 | ||
1da177e4 LT |
2206 | /* |
2207 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2208 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2209 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2210 | * fanatically on his truly buggy board. | |
2211 | */ | |
2212 | static inline void check_timer(void) | |
2213 | { | |
fcfd636a | 2214 | int apic1, pin1, apic2, pin2; |
1da177e4 LT |
2215 | int vector; |
2216 | ||
2217 | /* | |
2218 | * get/set the timer IRQ vector: | |
2219 | */ | |
2220 | disable_8259A_irq(0); | |
2221 | vector = assign_irq_vector(0); | |
2222 | set_intr_gate(vector, interrupt[0]); | |
2223 | ||
2224 | /* | |
2225 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
2226 | * mode for the 8259A whenever interrupts are routed | |
2227 | * through I/O APICs. Also IRQ0 has to be enabled in | |
2228 | * the 8259A which implies the virtual wire has to be | |
2229 | * disabled in the local APIC. | |
2230 | */ | |
2231 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
2232 | init_8259A(1); | |
2233 | timer_ack = 1; | |
f9262c12 AK |
2234 | if (timer_over_8254 > 0) |
2235 | enable_8259A_irq(0); | |
1da177e4 | 2236 | |
fcfd636a EB |
2237 | pin1 = find_isa_irq_pin(0, mp_INT); |
2238 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2239 | pin2 = ioapic_i8259.pin; | |
2240 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2241 | |
e0c1e9bf KM |
2242 | if (pin1 == 0) |
2243 | timer_uses_ioapic_pin_0 = 1; | |
2244 | ||
fcfd636a EB |
2245 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2246 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 LT |
2247 | |
2248 | if (pin1 != -1) { | |
2249 | /* | |
2250 | * Ok, does IRQ0 through the IOAPIC work? | |
2251 | */ | |
2252 | unmask_IO_APIC_irq(0); | |
2253 | if (timer_irq_works()) { | |
2254 | if (nmi_watchdog == NMI_IO_APIC) { | |
2255 | disable_8259A_irq(0); | |
2256 | setup_nmi(); | |
2257 | enable_8259A_irq(0); | |
1da177e4 | 2258 | } |
66759a01 CE |
2259 | if (disable_timer_pin_1 > 0) |
2260 | clear_IO_APIC_pin(0, pin1); | |
1da177e4 LT |
2261 | return; |
2262 | } | |
fcfd636a EB |
2263 | clear_IO_APIC_pin(apic1, pin1); |
2264 | printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " | |
2265 | "IO-APIC\n"); | |
1da177e4 LT |
2266 | } |
2267 | ||
2268 | printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); | |
2269 | if (pin2 != -1) { | |
2270 | printk("\n..... (found pin %d) ...", pin2); | |
2271 | /* | |
2272 | * legacy devices should be connected to IO APIC #0 | |
2273 | */ | |
fcfd636a | 2274 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
1da177e4 LT |
2275 | if (timer_irq_works()) { |
2276 | printk("works.\n"); | |
2277 | if (pin1 != -1) | |
fcfd636a | 2278 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
1da177e4 | 2279 | else |
fcfd636a | 2280 | add_pin_to_irq(0, apic2, pin2); |
1da177e4 LT |
2281 | if (nmi_watchdog == NMI_IO_APIC) { |
2282 | setup_nmi(); | |
1da177e4 LT |
2283 | } |
2284 | return; | |
2285 | } | |
2286 | /* | |
2287 | * Cleanup, just in case ... | |
2288 | */ | |
fcfd636a | 2289 | clear_IO_APIC_pin(apic2, pin2); |
1da177e4 LT |
2290 | } |
2291 | printk(" failed.\n"); | |
2292 | ||
2293 | if (nmi_watchdog == NMI_IO_APIC) { | |
2294 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
2295 | nmi_watchdog = 0; | |
2296 | } | |
2297 | ||
2298 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2299 | ||
2300 | disable_8259A_irq(0); | |
a460e745 IM |
2301 | set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, |
2302 | "fasteio"); | |
1da177e4 LT |
2303 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2304 | enable_8259A_irq(0); | |
2305 | ||
2306 | if (timer_irq_works()) { | |
2307 | printk(" works.\n"); | |
2308 | return; | |
2309 | } | |
2310 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); | |
2311 | printk(" failed.\n"); | |
2312 | ||
2313 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2314 | ||
2315 | timer_ack = 0; | |
2316 | init_8259A(0); | |
2317 | make_8259A_irq(0); | |
2318 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
2319 | ||
2320 | unlock_ExtINT_logic(); | |
2321 | ||
2322 | if (timer_irq_works()) { | |
2323 | printk(" works.\n"); | |
2324 | return; | |
2325 | } | |
2326 | printk(" failed :(.\n"); | |
2327 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2328 | "report. Then try booting with the 'noapic' option"); | |
2329 | } | |
2330 | ||
2331 | /* | |
2332 | * | |
2333 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
2334 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
2335 | * Linux doesn't really care, as it's not actually used | |
2336 | * for any interrupt handling anyway. | |
2337 | */ | |
2338 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2339 | ||
2340 | void __init setup_IO_APIC(void) | |
2341 | { | |
2342 | enable_IO_APIC(); | |
2343 | ||
2344 | if (acpi_ioapic) | |
2345 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
2346 | else | |
2347 | io_apic_irqs = ~PIC_IRQS; | |
2348 | ||
2349 | printk("ENABLING IO-APIC IRQs\n"); | |
2350 | ||
2351 | /* | |
2352 | * Set up IO-APIC IRQ routing. | |
2353 | */ | |
2354 | if (!acpi_ioapic) | |
2355 | setup_ioapic_ids_from_mpc(); | |
2356 | sync_Arb_IDs(); | |
2357 | setup_IO_APIC_irqs(); | |
2358 | init_IO_APIC_traps(); | |
1e4c85f9 | 2359 | check_timer(); |
1da177e4 LT |
2360 | if (!acpi_ioapic) |
2361 | print_IO_APIC(); | |
2362 | } | |
2363 | ||
f9262c12 AK |
2364 | static int __init setup_disable_8254_timer(char *s) |
2365 | { | |
2366 | timer_over_8254 = -1; | |
2367 | return 1; | |
2368 | } | |
2369 | static int __init setup_enable_8254_timer(char *s) | |
2370 | { | |
2371 | timer_over_8254 = 2; | |
2372 | return 1; | |
2373 | } | |
2374 | ||
2375 | __setup("disable_8254_timer", setup_disable_8254_timer); | |
2376 | __setup("enable_8254_timer", setup_enable_8254_timer); | |
2377 | ||
1da177e4 LT |
2378 | /* |
2379 | * Called after all the initialization is done. If we didnt find any | |
2380 | * APIC bugs then we can allow the modify fast path | |
2381 | */ | |
2382 | ||
2383 | static int __init io_apic_bug_finalize(void) | |
2384 | { | |
2385 | if(sis_apic_bug == -1) | |
2386 | sis_apic_bug = 0; | |
2387 | return 0; | |
2388 | } | |
2389 | ||
2390 | late_initcall(io_apic_bug_finalize); | |
2391 | ||
2392 | struct sysfs_ioapic_data { | |
2393 | struct sys_device dev; | |
2394 | struct IO_APIC_route_entry entry[0]; | |
2395 | }; | |
2396 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
2397 | ||
438510f6 | 2398 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2399 | { |
2400 | struct IO_APIC_route_entry *entry; | |
2401 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
2402 | int i; |
2403 | ||
2404 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2405 | entry = data->entry; | |
cf4c6a2f AK |
2406 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2407 | entry[i] = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2408 | |
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | static int ioapic_resume(struct sys_device *dev) | |
2413 | { | |
2414 | struct IO_APIC_route_entry *entry; | |
2415 | struct sysfs_ioapic_data *data; | |
2416 | unsigned long flags; | |
2417 | union IO_APIC_reg_00 reg_00; | |
2418 | int i; | |
2419 | ||
2420 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2421 | entry = data->entry; | |
2422 | ||
2423 | spin_lock_irqsave(&ioapic_lock, flags); | |
2424 | reg_00.raw = io_apic_read(dev->id, 0); | |
2425 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
2426 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
2427 | io_apic_write(dev->id, 0, reg_00.raw); | |
2428 | } | |
1da177e4 | 2429 | spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
2430 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2431 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
2432 | |
2433 | return 0; | |
2434 | } | |
2435 | ||
2436 | static struct sysdev_class ioapic_sysdev_class = { | |
2437 | set_kset_name("ioapic"), | |
2438 | .suspend = ioapic_suspend, | |
2439 | .resume = ioapic_resume, | |
2440 | }; | |
2441 | ||
2442 | static int __init ioapic_init_sysfs(void) | |
2443 | { | |
2444 | struct sys_device * dev; | |
2445 | int i, size, error = 0; | |
2446 | ||
2447 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2448 | if (error) | |
2449 | return error; | |
2450 | ||
2451 | for (i = 0; i < nr_ioapics; i++ ) { | |
2452 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
2453 | * sizeof(struct IO_APIC_route_entry); | |
2454 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
2455 | if (!mp_ioapic_data[i]) { | |
2456 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2457 | continue; | |
2458 | } | |
2459 | memset(mp_ioapic_data[i], 0, size); | |
2460 | dev = &mp_ioapic_data[i]->dev; | |
2461 | dev->id = i; | |
2462 | dev->cls = &ioapic_sysdev_class; | |
2463 | error = sysdev_register(dev); | |
2464 | if (error) { | |
2465 | kfree(mp_ioapic_data[i]); | |
2466 | mp_ioapic_data[i] = NULL; | |
2467 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2468 | continue; | |
2469 | } | |
2470 | } | |
2471 | ||
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | device_initcall(ioapic_init_sysfs); | |
2476 | ||
3fc471ed | 2477 | /* |
95d77884 | 2478 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2479 | */ |
2480 | int create_irq(void) | |
2481 | { | |
ace80ab7 EB |
2482 | /* Allocate an unused irq */ |
2483 | int irq, new, vector; | |
3fc471ed | 2484 | unsigned long flags; |
3fc471ed | 2485 | |
ace80ab7 EB |
2486 | irq = -ENOSPC; |
2487 | spin_lock_irqsave(&vector_lock, flags); | |
2488 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2489 | if (platform_legacy_irq(new)) | |
2490 | continue; | |
2491 | if (irq_vector[new] != 0) | |
2492 | continue; | |
2493 | vector = __assign_irq_vector(new); | |
2494 | if (likely(vector > 0)) | |
2495 | irq = new; | |
2496 | break; | |
2497 | } | |
2498 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2499 | |
ace80ab7 | 2500 | if (irq >= 0) { |
3fc471ed | 2501 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2502 | dynamic_irq_init(irq); |
2503 | } | |
2504 | return irq; | |
2505 | } | |
2506 | ||
2507 | void destroy_irq(unsigned int irq) | |
2508 | { | |
2509 | unsigned long flags; | |
3fc471ed EB |
2510 | |
2511 | dynamic_irq_cleanup(irq); | |
2512 | ||
2513 | spin_lock_irqsave(&vector_lock, flags); | |
3fc471ed EB |
2514 | irq_vector[irq] = 0; |
2515 | spin_unlock_irqrestore(&vector_lock, flags); | |
2516 | } | |
3fc471ed | 2517 | |
2d3fcc1c EB |
2518 | /* |
2519 | * MSI mesage composition | |
2520 | */ | |
2521 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2522 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2523 | { |
2d3fcc1c EB |
2524 | int vector; |
2525 | unsigned dest; | |
2526 | ||
2527 | vector = assign_irq_vector(irq); | |
2528 | if (vector >= 0) { | |
2529 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2530 | ||
2531 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2532 | msg->address_lo = | |
2533 | MSI_ADDR_BASE_LO | | |
2534 | ((INT_DEST_MODE == 0) ? | |
2535 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2536 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2537 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2538 | MSI_ADDR_REDIRECTION_CPU: | |
2539 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2540 | MSI_ADDR_DEST_ID(dest); | |
2541 | ||
2542 | msg->data = | |
2543 | MSI_DATA_TRIGGER_EDGE | | |
2544 | MSI_DATA_LEVEL_ASSERT | | |
2545 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2546 | MSI_DATA_DELIVERY_FIXED: | |
2547 | MSI_DATA_DELIVERY_LOWPRI) | | |
2548 | MSI_DATA_VECTOR(vector); | |
2549 | } | |
2550 | return vector; | |
2551 | } | |
2552 | ||
3b7d1921 EB |
2553 | #ifdef CONFIG_SMP |
2554 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2555 | { |
3b7d1921 EB |
2556 | struct msi_msg msg; |
2557 | unsigned int dest; | |
2558 | cpumask_t tmp; | |
2d3fcc1c | 2559 | int vector; |
3b7d1921 EB |
2560 | |
2561 | cpus_and(tmp, mask, cpu_online_map); | |
2562 | if (cpus_empty(tmp)) | |
2563 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2564 | |
2565 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2566 | if (vector < 0) |
2567 | return; | |
2d3fcc1c | 2568 | |
3b7d1921 EB |
2569 | dest = cpu_mask_to_apicid(mask); |
2570 | ||
2571 | read_msi_msg(irq, &msg); | |
2572 | ||
2573 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2574 | msg.data |= MSI_DATA_VECTOR(vector); | |
2575 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2576 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2577 | ||
2578 | write_msi_msg(irq, &msg); | |
2579 | set_native_irq_info(irq, mask); | |
2d3fcc1c | 2580 | } |
3b7d1921 | 2581 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2582 | |
3b7d1921 EB |
2583 | /* |
2584 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2585 | * which implement the MSI or MSI-X Capability Structure. | |
2586 | */ | |
2587 | static struct irq_chip msi_chip = { | |
2588 | .name = "PCI-MSI", | |
2589 | .unmask = unmask_msi_irq, | |
2590 | .mask = mask_msi_irq, | |
2591 | .ack = ack_ioapic_irq, | |
2592 | #ifdef CONFIG_SMP | |
2593 | .set_affinity = set_msi_irq_affinity, | |
2594 | #endif | |
2595 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2596 | }; |
2597 | ||
3b7d1921 EB |
2598 | int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev) |
2599 | { | |
2600 | struct msi_msg msg; | |
2601 | int ret; | |
2602 | ret = msi_compose_msg(dev, irq, &msg); | |
2603 | if (ret < 0) | |
2604 | return ret; | |
2605 | ||
2606 | write_msi_msg(irq, &msg); | |
2607 | ||
a460e745 IM |
2608 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2609 | "edge"); | |
3b7d1921 EB |
2610 | |
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | void arch_teardown_msi_irq(unsigned int irq) | |
2615 | { | |
2616 | return; | |
2617 | } | |
2618 | ||
2d3fcc1c EB |
2619 | #endif /* CONFIG_PCI_MSI */ |
2620 | ||
8b955b0d EB |
2621 | /* |
2622 | * Hypertransport interrupt support | |
2623 | */ | |
2624 | #ifdef CONFIG_HT_IRQ | |
2625 | ||
2626 | #ifdef CONFIG_SMP | |
2627 | ||
2628 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2629 | { | |
ec68307c EB |
2630 | struct ht_irq_msg msg; |
2631 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2632 | |
ec68307c EB |
2633 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2634 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2635 | |
ec68307c EB |
2636 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2637 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2638 | |
ec68307c | 2639 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2640 | } |
2641 | ||
2642 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2643 | { | |
2644 | unsigned int dest; | |
2645 | cpumask_t tmp; | |
2646 | ||
2647 | cpus_and(tmp, mask, cpu_online_map); | |
2648 | if (cpus_empty(tmp)) | |
2649 | tmp = TARGET_CPUS; | |
2650 | ||
2651 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2652 | ||
2653 | dest = cpu_mask_to_apicid(mask); | |
2654 | ||
2655 | target_ht_irq(irq, dest); | |
2656 | set_native_irq_info(irq, mask); | |
2657 | } | |
2658 | #endif | |
2659 | ||
c37e108d | 2660 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2661 | .name = "PCI-HT", |
2662 | .mask = mask_ht_irq, | |
2663 | .unmask = unmask_ht_irq, | |
2664 | .ack = ack_ioapic_irq, | |
2665 | #ifdef CONFIG_SMP | |
2666 | .set_affinity = set_ht_irq_affinity, | |
2667 | #endif | |
2668 | .retrigger = ioapic_retrigger_irq, | |
2669 | }; | |
2670 | ||
2671 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2672 | { | |
2673 | int vector; | |
2674 | ||
2675 | vector = assign_irq_vector(irq); | |
2676 | if (vector >= 0) { | |
ec68307c | 2677 | struct ht_irq_msg msg; |
8b955b0d EB |
2678 | unsigned dest; |
2679 | cpumask_t tmp; | |
2680 | ||
2681 | cpus_clear(tmp); | |
2682 | cpu_set(vector >> 8, tmp); | |
2683 | dest = cpu_mask_to_apicid(tmp); | |
2684 | ||
ec68307c | 2685 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2686 | |
ec68307c EB |
2687 | msg.address_lo = |
2688 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2689 | HT_IRQ_LOW_DEST_ID(dest) | |
2690 | HT_IRQ_LOW_VECTOR(vector) | | |
2691 | ((INT_DEST_MODE == 0) ? | |
2692 | HT_IRQ_LOW_DM_PHYSICAL : | |
2693 | HT_IRQ_LOW_DM_LOGICAL) | | |
2694 | HT_IRQ_LOW_RQEOI_EDGE | | |
2695 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2696 | HT_IRQ_LOW_MT_FIXED : | |
2697 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2698 | HT_IRQ_LOW_IRQ_MASKED; | |
2699 | ||
ec68307c | 2700 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2701 | |
a460e745 IM |
2702 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2703 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2704 | } |
2705 | return vector; | |
2706 | } | |
2707 | #endif /* CONFIG_HT_IRQ */ | |
2708 | ||
1da177e4 LT |
2709 | /* -------------------------------------------------------------------------- |
2710 | ACPI-based IOAPIC Configuration | |
2711 | -------------------------------------------------------------------------- */ | |
2712 | ||
888ba6c6 | 2713 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2714 | |
2715 | int __init io_apic_get_unique_id (int ioapic, int apic_id) | |
2716 | { | |
2717 | union IO_APIC_reg_00 reg_00; | |
2718 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2719 | physid_mask_t tmp; | |
2720 | unsigned long flags; | |
2721 | int i = 0; | |
2722 | ||
2723 | /* | |
2724 | * The P4 platform supports up to 256 APIC IDs on two separate APIC | |
2725 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
2726 | * supports up to 16 on one shared APIC bus. | |
2727 | * | |
2728 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full | |
2729 | * advantage of new APIC bus architecture. | |
2730 | */ | |
2731 | ||
2732 | if (physids_empty(apic_id_map)) | |
2733 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2734 | ||
2735 | spin_lock_irqsave(&ioapic_lock, flags); | |
2736 | reg_00.raw = io_apic_read(ioapic, 0); | |
2737 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2738 | ||
2739 | if (apic_id >= get_physical_broadcast()) { | |
2740 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2741 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2742 | apic_id = reg_00.bits.ID; | |
2743 | } | |
2744 | ||
2745 | /* | |
2746 | * Every APIC in a system must have a unique ID or we get lots of nice | |
2747 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2748 | */ | |
2749 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2750 | ||
2751 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2752 | if (!check_apicid_used(apic_id_map, i)) | |
2753 | break; | |
2754 | } | |
2755 | ||
2756 | if (i == get_physical_broadcast()) | |
2757 | panic("Max apic_id exceeded!\n"); | |
2758 | ||
2759 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2760 | "trying %d\n", ioapic, apic_id, i); | |
2761 | ||
2762 | apic_id = i; | |
2763 | } | |
2764 | ||
2765 | tmp = apicid_to_cpu_present(apic_id); | |
2766 | physids_or(apic_id_map, apic_id_map, tmp); | |
2767 | ||
2768 | if (reg_00.bits.ID != apic_id) { | |
2769 | reg_00.bits.ID = apic_id; | |
2770 | ||
2771 | spin_lock_irqsave(&ioapic_lock, flags); | |
2772 | io_apic_write(ioapic, 0, reg_00.raw); | |
2773 | reg_00.raw = io_apic_read(ioapic, 0); | |
2774 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2775 | ||
2776 | /* Sanity check */ | |
6070f9ec AD |
2777 | if (reg_00.bits.ID != apic_id) { |
2778 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2779 | return -1; | |
2780 | } | |
1da177e4 LT |
2781 | } |
2782 | ||
2783 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2784 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2785 | ||
2786 | return apic_id; | |
2787 | } | |
2788 | ||
2789 | ||
2790 | int __init io_apic_get_version (int ioapic) | |
2791 | { | |
2792 | union IO_APIC_reg_01 reg_01; | |
2793 | unsigned long flags; | |
2794 | ||
2795 | spin_lock_irqsave(&ioapic_lock, flags); | |
2796 | reg_01.raw = io_apic_read(ioapic, 1); | |
2797 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2798 | ||
2799 | return reg_01.bits.version; | |
2800 | } | |
2801 | ||
2802 | ||
2803 | int __init io_apic_get_redir_entries (int ioapic) | |
2804 | { | |
2805 | union IO_APIC_reg_01 reg_01; | |
2806 | unsigned long flags; | |
2807 | ||
2808 | spin_lock_irqsave(&ioapic_lock, flags); | |
2809 | reg_01.raw = io_apic_read(ioapic, 1); | |
2810 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2811 | ||
2812 | return reg_01.bits.entries; | |
2813 | } | |
2814 | ||
2815 | ||
2816 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) | |
2817 | { | |
2818 | struct IO_APIC_route_entry entry; | |
2819 | unsigned long flags; | |
2820 | ||
2821 | if (!IO_APIC_IRQ(irq)) { | |
2822 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2823 | ioapic); | |
2824 | return -EINVAL; | |
2825 | } | |
2826 | ||
2827 | /* | |
2828 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2829 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2830 | * corresponding device driver registers for this IRQ. | |
2831 | */ | |
2832 | ||
2833 | memset(&entry,0,sizeof(entry)); | |
2834 | ||
2835 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2836 | entry.dest_mode = INT_DEST_MODE; | |
2837 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2838 | entry.trigger = edge_level; | |
2839 | entry.polarity = active_high_low; | |
2840 | entry.mask = 1; | |
2841 | ||
2842 | /* | |
2843 | * IRQs < 16 are already in the irq_2_pin[] map | |
2844 | */ | |
2845 | if (irq >= 16) | |
2846 | add_pin_to_irq(irq, ioapic, pin); | |
2847 | ||
2848 | entry.vector = assign_irq_vector(irq); | |
2849 | ||
2850 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2851 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
2852 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
2853 | edge_level, active_high_low); | |
2854 | ||
2855 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2856 | ||
2857 | if (!ioapic && (irq < 16)) | |
2858 | disable_8259A_irq(irq); | |
2859 | ||
cf4c6a2f | 2860 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 | 2861 | spin_lock_irqsave(&ioapic_lock, flags); |
ace80ab7 | 2862 | set_native_irq_info(irq, TARGET_CPUS); |
1da177e4 LT |
2863 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2864 | ||
2865 | return 0; | |
2866 | } | |
2867 | ||
888ba6c6 | 2868 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2869 | |
2870 | static int __init parse_disable_timer_pin_1(char *arg) | |
2871 | { | |
2872 | disable_timer_pin_1 = 1; | |
2873 | return 0; | |
2874 | } | |
2875 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2876 | ||
2877 | static int __init parse_enable_timer_pin_1(char *arg) | |
2878 | { | |
2879 | disable_timer_pin_1 = -1; | |
2880 | return 0; | |
2881 | } | |
2882 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2883 | ||
2884 | static int __init parse_noapic(char *arg) | |
2885 | { | |
2886 | /* disable IO-APIC */ | |
2887 | disable_ioapic_setup(); | |
2888 | return 0; | |
2889 | } | |
2890 | early_param("noapic", parse_noapic); |