Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/smp_lock.h> |
29 | #include <linux/mc146818rtc.h> | |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
54d5d424 | 37 | |
1da177e4 LT |
38 | #include <asm/io.h> |
39 | #include <asm/smp.h> | |
40 | #include <asm/desc.h> | |
41 | #include <asm/timer.h> | |
306e440d | 42 | #include <asm/i8259.h> |
3e4ff115 | 43 | #include <asm/nmi.h> |
2d3fcc1c | 44 | #include <asm/msidef.h> |
8b955b0d | 45 | #include <asm/hypertransport.h> |
1da177e4 LT |
46 | |
47 | #include <mach_apic.h> | |
874c4fe3 | 48 | #include <mach_apicdef.h> |
1da177e4 LT |
49 | |
50 | #include "io_ports.h" | |
51 | ||
52 | int (*ioapic_renumber_irq)(int ioapic, int irq); | |
53 | atomic_t irq_mis_count; | |
54 | ||
fcfd636a EB |
55 | /* Where if anywhere is the i8259 connect in external int mode */ |
56 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
57 | ||
1da177e4 | 58 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 59 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 60 | |
f9262c12 AK |
61 | int timer_over_8254 __initdata = 1; |
62 | ||
1da177e4 LT |
63 | /* |
64 | * Is the SiS APIC rmw bug present ? | |
65 | * -1 = don't know, 0 = no, 1 = yes | |
66 | */ | |
67 | int sis_apic_bug = -1; | |
68 | ||
69 | /* | |
70 | * # of IRQ routing registers | |
71 | */ | |
72 | int nr_ioapic_registers[MAX_IO_APICS]; | |
73 | ||
1a3f239d | 74 | static int disable_timer_pin_1 __initdata; |
66759a01 | 75 | |
1da177e4 LT |
76 | /* |
77 | * Rough estimation of how many shared IRQs there are, can | |
78 | * be changed anytime. | |
79 | */ | |
80 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
81 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
82 | ||
83 | /* | |
84 | * This is performance-critical, we want to do it O(1) | |
85 | * | |
86 | * the indexing order of this array favors 1:1 mappings | |
87 | * between pins and IRQs. | |
88 | */ | |
89 | ||
90 | static struct irq_pin_list { | |
91 | int apic, pin, next; | |
92 | } irq_2_pin[PIN_MAP_SIZE]; | |
93 | ||
130fe05d LT |
94 | struct io_apic { |
95 | unsigned int index; | |
96 | unsigned int unused[3]; | |
97 | unsigned int data; | |
98 | }; | |
99 | ||
100 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
101 | { | |
102 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
103 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); | |
104 | } | |
105 | ||
106 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
107 | { | |
108 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
109 | writel(reg, &io_apic->index); | |
110 | return readl(&io_apic->data); | |
111 | } | |
112 | ||
113 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
114 | { | |
115 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
116 | writel(reg, &io_apic->index); | |
117 | writel(value, &io_apic->data); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Re-write a value: to be used for read-modify-write | |
122 | * cycles where the read already set up the index register. | |
123 | * | |
124 | * Older SiS APIC requires we rewrite the index register | |
125 | */ | |
126 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
127 | { | |
128 | volatile struct io_apic *io_apic = io_apic_base(apic); | |
129 | if (sis_apic_bug) | |
130 | writel(reg, &io_apic->index); | |
131 | writel(value, &io_apic->data); | |
132 | } | |
133 | ||
cf4c6a2f AK |
134 | union entry_union { |
135 | struct { u32 w1, w2; }; | |
136 | struct IO_APIC_route_entry entry; | |
137 | }; | |
138 | ||
139 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
140 | { | |
141 | union entry_union eu; | |
142 | unsigned long flags; | |
143 | spin_lock_irqsave(&ioapic_lock, flags); | |
144 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
145 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
146 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
147 | return eu.entry; | |
148 | } | |
149 | ||
f9dadfa7 LT |
150 | /* |
151 | * When we write a new IO APIC routing entry, we need to write the high | |
152 | * word first! If the mask bit in the low word is clear, we will enable | |
153 | * the interrupt, and we need to make sure the entry is fully populated | |
154 | * before that happens. | |
155 | */ | |
cf4c6a2f AK |
156 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
157 | { | |
158 | unsigned long flags; | |
159 | union entry_union eu; | |
160 | eu.entry = e; | |
f9dadfa7 LT |
161 | spin_lock_irqsave(&ioapic_lock, flags); |
162 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
163 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
164 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
165 | } | |
166 | ||
167 | /* | |
168 | * When we mask an IO APIC routing entry, we need to write the low | |
169 | * word first, in order to set the mask bit before we change the | |
170 | * high bits! | |
171 | */ | |
172 | static void ioapic_mask_entry(int apic, int pin) | |
173 | { | |
174 | unsigned long flags; | |
175 | union entry_union eu = { .entry.mask = 1 }; | |
176 | ||
cf4c6a2f AK |
177 | spin_lock_irqsave(&ioapic_lock, flags); |
178 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
179 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
180 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
181 | } | |
182 | ||
1da177e4 LT |
183 | /* |
184 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
185 | * shared ISA-space IRQs, so we have to support them. We are super | |
186 | * fast in the common case, and fast for shared ISA-space IRQs. | |
187 | */ | |
188 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
189 | { | |
190 | static int first_free_entry = NR_IRQS; | |
191 | struct irq_pin_list *entry = irq_2_pin + irq; | |
192 | ||
193 | while (entry->next) | |
194 | entry = irq_2_pin + entry->next; | |
195 | ||
196 | if (entry->pin != -1) { | |
197 | entry->next = first_free_entry; | |
198 | entry = irq_2_pin + entry->next; | |
199 | if (++first_free_entry >= PIN_MAP_SIZE) | |
200 | panic("io_apic.c: whoops"); | |
201 | } | |
202 | entry->apic = apic; | |
203 | entry->pin = pin; | |
204 | } | |
205 | ||
206 | /* | |
207 | * Reroute an IRQ to a different pin. | |
208 | */ | |
209 | static void __init replace_pin_at_irq(unsigned int irq, | |
210 | int oldapic, int oldpin, | |
211 | int newapic, int newpin) | |
212 | { | |
213 | struct irq_pin_list *entry = irq_2_pin + irq; | |
214 | ||
215 | while (1) { | |
216 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
217 | entry->apic = newapic; | |
218 | entry->pin = newpin; | |
219 | } | |
220 | if (!entry->next) | |
221 | break; | |
222 | entry = irq_2_pin + entry->next; | |
223 | } | |
224 | } | |
225 | ||
226 | static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) | |
227 | { | |
228 | struct irq_pin_list *entry = irq_2_pin + irq; | |
229 | unsigned int pin, reg; | |
230 | ||
231 | for (;;) { | |
232 | pin = entry->pin; | |
233 | if (pin == -1) | |
234 | break; | |
235 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
236 | reg &= ~disable; | |
237 | reg |= enable; | |
238 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
239 | if (!entry->next) | |
240 | break; | |
241 | entry = irq_2_pin + entry->next; | |
242 | } | |
243 | } | |
244 | ||
245 | /* mask = 1 */ | |
246 | static void __mask_IO_APIC_irq (unsigned int irq) | |
247 | { | |
248 | __modify_IO_APIC_irq(irq, 0x00010000, 0); | |
249 | } | |
250 | ||
251 | /* mask = 0 */ | |
252 | static void __unmask_IO_APIC_irq (unsigned int irq) | |
253 | { | |
254 | __modify_IO_APIC_irq(irq, 0, 0x00010000); | |
255 | } | |
256 | ||
257 | /* mask = 1, trigger = 0 */ | |
258 | static void __mask_and_edge_IO_APIC_irq (unsigned int irq) | |
259 | { | |
260 | __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); | |
261 | } | |
262 | ||
263 | /* mask = 0, trigger = 1 */ | |
264 | static void __unmask_and_level_IO_APIC_irq (unsigned int irq) | |
265 | { | |
266 | __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); | |
267 | } | |
268 | ||
269 | static void mask_IO_APIC_irq (unsigned int irq) | |
270 | { | |
271 | unsigned long flags; | |
272 | ||
273 | spin_lock_irqsave(&ioapic_lock, flags); | |
274 | __mask_IO_APIC_irq(irq); | |
275 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
276 | } | |
277 | ||
278 | static void unmask_IO_APIC_irq (unsigned int irq) | |
279 | { | |
280 | unsigned long flags; | |
281 | ||
282 | spin_lock_irqsave(&ioapic_lock, flags); | |
283 | __unmask_IO_APIC_irq(irq); | |
284 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
285 | } | |
286 | ||
287 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
288 | { | |
289 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
290 | |
291 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
cf4c6a2f | 292 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
293 | if (entry.delivery_mode == dest_SMI) |
294 | return; | |
295 | ||
296 | /* | |
297 | * Disable it in the IO-APIC irq-routing table: | |
298 | */ | |
f9dadfa7 | 299 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
300 | } |
301 | ||
302 | static void clear_IO_APIC (void) | |
303 | { | |
304 | int apic, pin; | |
305 | ||
306 | for (apic = 0; apic < nr_ioapics; apic++) | |
307 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
308 | clear_IO_APIC_pin(apic, pin); | |
309 | } | |
310 | ||
54d5d424 | 311 | #ifdef CONFIG_SMP |
1da177e4 LT |
312 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
313 | { | |
314 | unsigned long flags; | |
315 | int pin; | |
316 | struct irq_pin_list *entry = irq_2_pin + irq; | |
317 | unsigned int apicid_value; | |
54d5d424 | 318 | cpumask_t tmp; |
1da177e4 | 319 | |
54d5d424 AR |
320 | cpus_and(tmp, cpumask, cpu_online_map); |
321 | if (cpus_empty(tmp)) | |
322 | tmp = TARGET_CPUS; | |
323 | ||
324 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
325 | ||
1da177e4 LT |
326 | apicid_value = cpu_mask_to_apicid(cpumask); |
327 | /* Prepare to do the io_apic_write */ | |
328 | apicid_value = apicid_value << 24; | |
329 | spin_lock_irqsave(&ioapic_lock, flags); | |
330 | for (;;) { | |
331 | pin = entry->pin; | |
332 | if (pin == -1) | |
333 | break; | |
334 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
335 | if (!entry->next) | |
336 | break; | |
337 | entry = irq_2_pin + entry->next; | |
338 | } | |
ace80ab7 | 339 | set_native_irq_info(irq, cpumask); |
1da177e4 LT |
340 | spin_unlock_irqrestore(&ioapic_lock, flags); |
341 | } | |
342 | ||
343 | #if defined(CONFIG_IRQBALANCE) | |
344 | # include <asm/processor.h> /* kernel_thread() */ | |
345 | # include <linux/kernel_stat.h> /* kstat */ | |
346 | # include <linux/slab.h> /* kmalloc() */ | |
347 | # include <linux/timer.h> /* time_after() */ | |
348 | ||
1b61b910 | 349 | #ifdef CONFIG_BALANCED_IRQ_DEBUG |
1da177e4 LT |
350 | # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0) |
351 | # define Dprintk(x...) do { TDprintk(x); } while (0) | |
352 | # else | |
353 | # define TDprintk(x...) | |
354 | # define Dprintk(x...) | |
355 | # endif | |
356 | ||
1da177e4 | 357 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
358 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
359 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
360 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
361 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
362 | ||
363 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
364 | static int physical_balance __read_mostly; | |
365 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
366 | |
367 | static struct irq_cpu_info { | |
368 | unsigned long * last_irq; | |
369 | unsigned long * irq_delta; | |
370 | unsigned long irq; | |
371 | } irq_cpu_data[NR_CPUS]; | |
372 | ||
373 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
374 | #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) | |
375 | #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
376 | ||
377 | #define IDLE_ENOUGH(cpu,now) \ | |
378 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
379 | ||
380 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
381 | ||
382 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i])) | |
383 | ||
1b61b910 ZY |
384 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
385 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
386 | }; | |
1da177e4 | 387 | |
1b61b910 ZY |
388 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
389 | { | |
390 | balance_irq_affinity[irq] = mask; | |
391 | } | |
1da177e4 LT |
392 | |
393 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
394 | unsigned long now, int direction) | |
395 | { | |
396 | int search_idle = 1; | |
397 | int cpu = curr_cpu; | |
398 | ||
399 | goto inside; | |
400 | ||
401 | do { | |
402 | if (unlikely(cpu == curr_cpu)) | |
403 | search_idle = 0; | |
404 | inside: | |
405 | if (direction == 1) { | |
406 | cpu++; | |
407 | if (cpu >= NR_CPUS) | |
408 | cpu = 0; | |
409 | } else { | |
410 | cpu--; | |
411 | if (cpu == -1) | |
412 | cpu = NR_CPUS-1; | |
413 | } | |
414 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || | |
415 | (search_idle && !IDLE_ENOUGH(cpu,now))); | |
416 | ||
417 | return cpu; | |
418 | } | |
419 | ||
420 | static inline void balance_irq(int cpu, int irq) | |
421 | { | |
422 | unsigned long now = jiffies; | |
423 | cpumask_t allowed_mask; | |
424 | unsigned int new_cpu; | |
425 | ||
426 | if (irqbalance_disabled) | |
427 | return; | |
428 | ||
1b61b910 | 429 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 LT |
430 | new_cpu = move(cpu, allowed_mask, now, 1); |
431 | if (cpu != new_cpu) { | |
54d5d424 | 432 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
433 | } |
434 | } | |
435 | ||
436 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
437 | { | |
438 | int i, j; | |
439 | Dprintk("Rotating IRQs among CPUs.\n"); | |
394e3902 AM |
440 | for_each_online_cpu(i) { |
441 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
442 | if (!irq_desc[j].action) |
443 | continue; | |
444 | /* Is it a significant load ? */ | |
445 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < | |
446 | useful_load_threshold) | |
447 | continue; | |
448 | balance_irq(i, j); | |
449 | } | |
450 | } | |
451 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
452 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
453 | return; | |
454 | } | |
455 | ||
456 | static void do_irq_balance(void) | |
457 | { | |
458 | int i, j; | |
459 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
460 | unsigned long move_this_load = 0; | |
461 | int max_loaded = 0, min_loaded = 0; | |
462 | int load; | |
463 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
464 | int selected_irq; | |
465 | int tmp_loaded, first_attempt = 1; | |
466 | unsigned long tmp_cpu_irq; | |
467 | unsigned long imbalance = 0; | |
468 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
469 | ||
c8912599 | 470 | for_each_possible_cpu(i) { |
1da177e4 LT |
471 | int package_index; |
472 | CPU_IRQ(i) = 0; | |
473 | if (!cpu_online(i)) | |
474 | continue; | |
475 | package_index = CPU_TO_PACKAGEINDEX(i); | |
476 | for (j = 0; j < NR_IRQS; j++) { | |
477 | unsigned long value_now, delta; | |
478 | /* Is this an active IRQ? */ | |
479 | if (!irq_desc[j].action) | |
480 | continue; | |
481 | if ( package_index == i ) | |
482 | IRQ_DELTA(package_index,j) = 0; | |
483 | /* Determine the total count per processor per IRQ */ | |
484 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
485 | ||
486 | /* Determine the activity per processor per IRQ */ | |
487 | delta = value_now - LAST_CPU_IRQ(i,j); | |
488 | ||
489 | /* Update last_cpu_irq[][] for the next time */ | |
490 | LAST_CPU_IRQ(i,j) = value_now; | |
491 | ||
492 | /* Ignore IRQs whose rate is less than the clock */ | |
493 | if (delta < useful_load_threshold) | |
494 | continue; | |
495 | /* update the load for the processor or package total */ | |
496 | IRQ_DELTA(package_index,j) += delta; | |
497 | ||
498 | /* Keep track of the higher numbered sibling as well */ | |
499 | if (i != package_index) | |
500 | CPU_IRQ(i) += delta; | |
501 | /* | |
502 | * We have sibling A and sibling B in the package | |
503 | * | |
504 | * cpu_irq[A] = load for cpu A + load for cpu B | |
505 | * cpu_irq[B] = load for cpu B | |
506 | */ | |
507 | CPU_IRQ(package_index) += delta; | |
508 | } | |
509 | } | |
510 | /* Find the least loaded processor package */ | |
394e3902 | 511 | for_each_online_cpu(i) { |
1da177e4 LT |
512 | if (i != CPU_TO_PACKAGEINDEX(i)) |
513 | continue; | |
514 | if (min_cpu_irq > CPU_IRQ(i)) { | |
515 | min_cpu_irq = CPU_IRQ(i); | |
516 | min_loaded = i; | |
517 | } | |
518 | } | |
519 | max_cpu_irq = ULONG_MAX; | |
520 | ||
521 | tryanothercpu: | |
522 | /* Look for heaviest loaded processor. | |
523 | * We may come back to get the next heaviest loaded processor. | |
524 | * Skip processors with trivial loads. | |
525 | */ | |
526 | tmp_cpu_irq = 0; | |
527 | tmp_loaded = -1; | |
394e3902 | 528 | for_each_online_cpu(i) { |
1da177e4 LT |
529 | if (i != CPU_TO_PACKAGEINDEX(i)) |
530 | continue; | |
531 | if (max_cpu_irq <= CPU_IRQ(i)) | |
532 | continue; | |
533 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
534 | tmp_cpu_irq = CPU_IRQ(i); | |
535 | tmp_loaded = i; | |
536 | } | |
537 | } | |
538 | ||
539 | if (tmp_loaded == -1) { | |
540 | /* In the case of small number of heavy interrupt sources, | |
541 | * loading some of the cpus too much. We use Ingo's original | |
542 | * approach to rotate them around. | |
543 | */ | |
544 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
545 | rotate_irqs_among_cpus(useful_load_threshold); | |
546 | return; | |
547 | } | |
548 | goto not_worth_the_effort; | |
549 | } | |
550 | ||
551 | first_attempt = 0; /* heaviest search */ | |
552 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
553 | max_loaded = tmp_loaded; /* processor */ | |
554 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
555 | ||
556 | Dprintk("max_loaded cpu = %d\n", max_loaded); | |
557 | Dprintk("min_loaded cpu = %d\n", min_loaded); | |
558 | Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq); | |
559 | Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq); | |
560 | Dprintk("load imbalance = %lu\n", imbalance); | |
561 | ||
562 | /* if imbalance is less than approx 10% of max load, then | |
563 | * observe diminishing returns action. - quit | |
564 | */ | |
565 | if (imbalance < (max_cpu_irq >> 3)) { | |
566 | Dprintk("Imbalance too trivial\n"); | |
567 | goto not_worth_the_effort; | |
568 | } | |
569 | ||
570 | tryanotherirq: | |
571 | /* if we select an IRQ to move that can't go where we want, then | |
572 | * see if there is another one to try. | |
573 | */ | |
574 | move_this_load = 0; | |
575 | selected_irq = -1; | |
576 | for (j = 0; j < NR_IRQS; j++) { | |
577 | /* Is this an active IRQ? */ | |
578 | if (!irq_desc[j].action) | |
579 | continue; | |
580 | if (imbalance <= IRQ_DELTA(max_loaded,j)) | |
581 | continue; | |
582 | /* Try to find the IRQ that is closest to the imbalance | |
583 | * without going over. | |
584 | */ | |
585 | if (move_this_load < IRQ_DELTA(max_loaded,j)) { | |
586 | move_this_load = IRQ_DELTA(max_loaded,j); | |
587 | selected_irq = j; | |
588 | } | |
589 | } | |
590 | if (selected_irq == -1) { | |
591 | goto tryanothercpu; | |
592 | } | |
593 | ||
594 | imbalance = move_this_load; | |
595 | ||
596 | /* For physical_balance case, we accumlated both load | |
597 | * values in the one of the siblings cpu_irq[], | |
598 | * to use the same code for physical and logical processors | |
599 | * as much as possible. | |
600 | * | |
601 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
602 | * sibling A and sibling B in the slot for the lowest numbered | |
603 | * sibling (A), _AND_ the load for sibling B in the slot for | |
604 | * the higher numbered sibling. | |
605 | * | |
606 | * We seek the least loaded sibling by making the comparison | |
607 | * (A+B)/2 vs B | |
608 | */ | |
609 | load = CPU_IRQ(min_loaded) >> 1; | |
610 | for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) { | |
611 | if (load > CPU_IRQ(j)) { | |
612 | /* This won't change cpu_sibling_map[min_loaded] */ | |
613 | load = CPU_IRQ(j); | |
614 | min_loaded = j; | |
615 | } | |
616 | } | |
617 | ||
1b61b910 ZY |
618 | cpus_and(allowed_mask, |
619 | cpu_online_map, | |
620 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
621 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
622 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
623 | ||
624 | if (!cpus_empty(tmp)) { | |
1da177e4 LT |
625 | |
626 | Dprintk("irq = %d moved to cpu = %d\n", | |
627 | selected_irq, min_loaded); | |
628 | /* mark for change destination */ | |
54d5d424 AR |
629 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
630 | ||
1da177e4 LT |
631 | /* Since we made a change, come back sooner to |
632 | * check for more variation. | |
633 | */ | |
634 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
635 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
636 | return; | |
637 | } | |
638 | goto tryanotherirq; | |
639 | ||
640 | not_worth_the_effort: | |
641 | /* | |
642 | * if we did not find an IRQ to move, then adjust the time interval | |
643 | * upward | |
644 | */ | |
645 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
646 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); | |
647 | Dprintk("IRQ worth rotating not found\n"); | |
648 | return; | |
649 | } | |
650 | ||
651 | static int balanced_irq(void *unused) | |
652 | { | |
653 | int i; | |
654 | unsigned long prev_balance_time = jiffies; | |
655 | long time_remaining = balanced_irq_interval; | |
656 | ||
657 | daemonize("kirqd"); | |
658 | ||
659 | /* push everything to CPU 0 to give us a starting point. */ | |
660 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 661 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 662 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
663 | } |
664 | ||
665 | for ( ; ; ) { | |
52e6e630 | 666 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 667 | try_to_freeze(); |
1da177e4 LT |
668 | if (time_after(jiffies, |
669 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 670 | preempt_disable(); |
1da177e4 LT |
671 | do_irq_balance(); |
672 | prev_balance_time = jiffies; | |
673 | time_remaining = balanced_irq_interval; | |
f3705136 | 674 | preempt_enable(); |
1da177e4 LT |
675 | } |
676 | } | |
677 | return 0; | |
678 | } | |
679 | ||
680 | static int __init balanced_irq_init(void) | |
681 | { | |
682 | int i; | |
683 | struct cpuinfo_x86 *c; | |
684 | cpumask_t tmp; | |
685 | ||
686 | cpus_shift_right(tmp, cpu_online_map, 2); | |
687 | c = &boot_cpu_data; | |
688 | /* When not overwritten by the command line ask subarchitecture. */ | |
689 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
690 | irqbalance_disabled = NO_BALANCE_IRQ; | |
691 | if (irqbalance_disabled) | |
692 | return 0; | |
693 | ||
694 | /* disable irqbalance completely if there is only one processor online */ | |
695 | if (num_online_cpus() < 2) { | |
696 | irqbalance_disabled = 1; | |
697 | return 0; | |
698 | } | |
699 | /* | |
700 | * Enable physical balance only if more than 1 physical processor | |
701 | * is present | |
702 | */ | |
703 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
704 | physical_balance = 1; | |
705 | ||
394e3902 | 706 | for_each_online_cpu(i) { |
1da177e4 LT |
707 | irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
708 | irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
709 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { | |
710 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
711 | goto failed; | |
712 | } | |
713 | memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS); | |
714 | memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS); | |
715 | } | |
716 | ||
717 | printk(KERN_INFO "Starting balanced_irq\n"); | |
718 | if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) | |
719 | return 0; | |
720 | else | |
721 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); | |
722 | failed: | |
c8912599 | 723 | for_each_possible_cpu(i) { |
4ae6673e | 724 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 725 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 726 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 727 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
728 | } |
729 | return 0; | |
730 | } | |
731 | ||
732 | int __init irqbalance_disable(char *str) | |
733 | { | |
734 | irqbalance_disabled = 1; | |
9b41046c | 735 | return 1; |
1da177e4 LT |
736 | } |
737 | ||
738 | __setup("noirqbalance", irqbalance_disable); | |
739 | ||
1da177e4 | 740 | late_initcall(balanced_irq_init); |
1da177e4 | 741 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 742 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
743 | |
744 | #ifndef CONFIG_SMP | |
745 | void fastcall send_IPI_self(int vector) | |
746 | { | |
747 | unsigned int cfg; | |
748 | ||
749 | /* | |
750 | * Wait for idle. | |
751 | */ | |
752 | apic_wait_icr_idle(); | |
753 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
754 | /* | |
755 | * Send the IPI. The write to APIC_ICR fires this off. | |
756 | */ | |
757 | apic_write_around(APIC_ICR, cfg); | |
758 | } | |
759 | #endif /* !CONFIG_SMP */ | |
760 | ||
761 | ||
762 | /* | |
763 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
764 | * specific CPU-side IRQs. | |
765 | */ | |
766 | ||
767 | #define MAX_PIRQS 8 | |
768 | static int pirq_entries [MAX_PIRQS]; | |
769 | static int pirqs_enabled; | |
770 | int skip_ioapic_setup; | |
771 | ||
772 | static int __init ioapic_setup(char *str) | |
773 | { | |
774 | skip_ioapic_setup = 1; | |
775 | return 1; | |
776 | } | |
777 | ||
778 | __setup("noapic", ioapic_setup); | |
779 | ||
780 | static int __init ioapic_pirq_setup(char *str) | |
781 | { | |
782 | int i, max; | |
783 | int ints[MAX_PIRQS+1]; | |
784 | ||
785 | get_options(str, ARRAY_SIZE(ints), ints); | |
786 | ||
787 | for (i = 0; i < MAX_PIRQS; i++) | |
788 | pirq_entries[i] = -1; | |
789 | ||
790 | pirqs_enabled = 1; | |
791 | apic_printk(APIC_VERBOSE, KERN_INFO | |
792 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
793 | max = MAX_PIRQS; | |
794 | if (ints[0] < MAX_PIRQS) | |
795 | max = ints[0]; | |
796 | ||
797 | for (i = 0; i < max; i++) { | |
798 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
799 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
800 | /* | |
801 | * PIRQs are mapped upside down, usually. | |
802 | */ | |
803 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
804 | } | |
805 | return 1; | |
806 | } | |
807 | ||
808 | __setup("pirq=", ioapic_pirq_setup); | |
809 | ||
810 | /* | |
811 | * Find the IRQ entry number of a certain pin. | |
812 | */ | |
813 | static int find_irq_entry(int apic, int pin, int type) | |
814 | { | |
815 | int i; | |
816 | ||
817 | for (i = 0; i < mp_irq_entries; i++) | |
818 | if (mp_irqs[i].mpc_irqtype == type && | |
819 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
820 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
821 | mp_irqs[i].mpc_dstirq == pin) | |
822 | return i; | |
823 | ||
824 | return -1; | |
825 | } | |
826 | ||
827 | /* | |
828 | * Find the pin to which IRQ[irq] (ISA) is connected | |
829 | */ | |
fcfd636a | 830 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
831 | { |
832 | int i; | |
833 | ||
834 | for (i = 0; i < mp_irq_entries; i++) { | |
835 | int lbus = mp_irqs[i].mpc_srcbus; | |
836 | ||
837 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
838 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
839 | mp_bus_id_to_type[lbus] == MP_BUS_MCA || | |
840 | mp_bus_id_to_type[lbus] == MP_BUS_NEC98 | |
841 | ) && | |
842 | (mp_irqs[i].mpc_irqtype == type) && | |
843 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
844 | ||
845 | return mp_irqs[i].mpc_dstirq; | |
846 | } | |
847 | return -1; | |
848 | } | |
849 | ||
fcfd636a EB |
850 | static int __init find_isa_irq_apic(int irq, int type) |
851 | { | |
852 | int i; | |
853 | ||
854 | for (i = 0; i < mp_irq_entries; i++) { | |
855 | int lbus = mp_irqs[i].mpc_srcbus; | |
856 | ||
857 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
858 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
859 | mp_bus_id_to_type[lbus] == MP_BUS_MCA || | |
860 | mp_bus_id_to_type[lbus] == MP_BUS_NEC98 | |
861 | ) && | |
862 | (mp_irqs[i].mpc_irqtype == type) && | |
863 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
864 | break; | |
865 | } | |
866 | if (i < mp_irq_entries) { | |
867 | int apic; | |
868 | for(apic = 0; apic < nr_ioapics; apic++) { | |
869 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
870 | return apic; | |
871 | } | |
872 | } | |
873 | ||
874 | return -1; | |
875 | } | |
876 | ||
1da177e4 LT |
877 | /* |
878 | * Find a specific PCI IRQ entry. | |
879 | * Not an __init, possibly needed by modules | |
880 | */ | |
881 | static int pin_2_irq(int idx, int apic, int pin); | |
882 | ||
883 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
884 | { | |
885 | int apic, i, best_guess = -1; | |
886 | ||
887 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
888 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
889 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
890 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
891 | return -1; | |
892 | } | |
893 | for (i = 0; i < mp_irq_entries; i++) { | |
894 | int lbus = mp_irqs[i].mpc_srcbus; | |
895 | ||
896 | for (apic = 0; apic < nr_ioapics; apic++) | |
897 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
898 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
899 | break; | |
900 | ||
901 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && | |
902 | !mp_irqs[i].mpc_irqtype && | |
903 | (bus == lbus) && | |
904 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
905 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
906 | ||
907 | if (!(apic || IO_APIC_IRQ(irq))) | |
908 | continue; | |
909 | ||
910 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
911 | return irq; | |
912 | /* | |
913 | * Use the first all-but-pin matching entry as a | |
914 | * best-guess fuzzy result for broken mptables. | |
915 | */ | |
916 | if (best_guess < 0) | |
917 | best_guess = irq; | |
918 | } | |
919 | } | |
920 | return best_guess; | |
921 | } | |
129f6946 | 922 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
923 | |
924 | /* | |
925 | * This function currently is only a helper for the i386 smp boot process where | |
926 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
927 | * so mask in all cases should simply be TARGET_CPUS | |
928 | */ | |
54d5d424 | 929 | #ifdef CONFIG_SMP |
1da177e4 LT |
930 | void __init setup_ioapic_dest(void) |
931 | { | |
932 | int pin, ioapic, irq, irq_entry; | |
933 | ||
934 | if (skip_ioapic_setup == 1) | |
935 | return; | |
936 | ||
937 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
938 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
939 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
940 | if (irq_entry == -1) | |
941 | continue; | |
942 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
943 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
944 | } | |
945 | ||
946 | } | |
947 | } | |
54d5d424 | 948 | #endif |
1da177e4 LT |
949 | |
950 | /* | |
951 | * EISA Edge/Level control register, ELCR | |
952 | */ | |
953 | static int EISA_ELCR(unsigned int irq) | |
954 | { | |
955 | if (irq < 16) { | |
956 | unsigned int port = 0x4d0 + (irq >> 3); | |
957 | return (inb(port) >> (irq & 7)) & 1; | |
958 | } | |
959 | apic_printk(APIC_VERBOSE, KERN_INFO | |
960 | "Broken MPtable reports ISA irq %d\n", irq); | |
961 | return 0; | |
962 | } | |
963 | ||
964 | /* EISA interrupts are always polarity zero and can be edge or level | |
965 | * trigger depending on the ELCR value. If an interrupt is listed as | |
966 | * EISA conforming in the MP table, that means its trigger type must | |
967 | * be read in from the ELCR */ | |
968 | ||
969 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) | |
970 | #define default_EISA_polarity(idx) (0) | |
971 | ||
972 | /* ISA interrupts are always polarity zero edge triggered, | |
973 | * when listed as conforming in the MP table. */ | |
974 | ||
975 | #define default_ISA_trigger(idx) (0) | |
976 | #define default_ISA_polarity(idx) (0) | |
977 | ||
978 | /* PCI interrupts are always polarity one level triggered, | |
979 | * when listed as conforming in the MP table. */ | |
980 | ||
981 | #define default_PCI_trigger(idx) (1) | |
982 | #define default_PCI_polarity(idx) (1) | |
983 | ||
984 | /* MCA interrupts are always polarity zero level triggered, | |
985 | * when listed as conforming in the MP table. */ | |
986 | ||
987 | #define default_MCA_trigger(idx) (1) | |
988 | #define default_MCA_polarity(idx) (0) | |
989 | ||
990 | /* NEC98 interrupts are always polarity zero edge triggered, | |
991 | * when listed as conforming in the MP table. */ | |
992 | ||
993 | #define default_NEC98_trigger(idx) (0) | |
994 | #define default_NEC98_polarity(idx) (0) | |
995 | ||
996 | static int __init MPBIOS_polarity(int idx) | |
997 | { | |
998 | int bus = mp_irqs[idx].mpc_srcbus; | |
999 | int polarity; | |
1000 | ||
1001 | /* | |
1002 | * Determine IRQ line polarity (high active or low active): | |
1003 | */ | |
1004 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
1005 | { | |
1006 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
1007 | { | |
1008 | switch (mp_bus_id_to_type[bus]) | |
1009 | { | |
1010 | case MP_BUS_ISA: /* ISA pin */ | |
1011 | { | |
1012 | polarity = default_ISA_polarity(idx); | |
1013 | break; | |
1014 | } | |
1015 | case MP_BUS_EISA: /* EISA pin */ | |
1016 | { | |
1017 | polarity = default_EISA_polarity(idx); | |
1018 | break; | |
1019 | } | |
1020 | case MP_BUS_PCI: /* PCI pin */ | |
1021 | { | |
1022 | polarity = default_PCI_polarity(idx); | |
1023 | break; | |
1024 | } | |
1025 | case MP_BUS_MCA: /* MCA pin */ | |
1026 | { | |
1027 | polarity = default_MCA_polarity(idx); | |
1028 | break; | |
1029 | } | |
1030 | case MP_BUS_NEC98: /* NEC 98 pin */ | |
1031 | { | |
1032 | polarity = default_NEC98_polarity(idx); | |
1033 | break; | |
1034 | } | |
1035 | default: | |
1036 | { | |
1037 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1038 | polarity = 1; | |
1039 | break; | |
1040 | } | |
1041 | } | |
1042 | break; | |
1043 | } | |
1044 | case 1: /* high active */ | |
1045 | { | |
1046 | polarity = 0; | |
1047 | break; | |
1048 | } | |
1049 | case 2: /* reserved */ | |
1050 | { | |
1051 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1052 | polarity = 1; | |
1053 | break; | |
1054 | } | |
1055 | case 3: /* low active */ | |
1056 | { | |
1057 | polarity = 1; | |
1058 | break; | |
1059 | } | |
1060 | default: /* invalid */ | |
1061 | { | |
1062 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1063 | polarity = 1; | |
1064 | break; | |
1065 | } | |
1066 | } | |
1067 | return polarity; | |
1068 | } | |
1069 | ||
1070 | static int MPBIOS_trigger(int idx) | |
1071 | { | |
1072 | int bus = mp_irqs[idx].mpc_srcbus; | |
1073 | int trigger; | |
1074 | ||
1075 | /* | |
1076 | * Determine IRQ trigger mode (edge or level sensitive): | |
1077 | */ | |
1078 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
1079 | { | |
1080 | case 0: /* conforms, ie. bus-type dependent */ | |
1081 | { | |
1082 | switch (mp_bus_id_to_type[bus]) | |
1083 | { | |
1084 | case MP_BUS_ISA: /* ISA pin */ | |
1085 | { | |
1086 | trigger = default_ISA_trigger(idx); | |
1087 | break; | |
1088 | } | |
1089 | case MP_BUS_EISA: /* EISA pin */ | |
1090 | { | |
1091 | trigger = default_EISA_trigger(idx); | |
1092 | break; | |
1093 | } | |
1094 | case MP_BUS_PCI: /* PCI pin */ | |
1095 | { | |
1096 | trigger = default_PCI_trigger(idx); | |
1097 | break; | |
1098 | } | |
1099 | case MP_BUS_MCA: /* MCA pin */ | |
1100 | { | |
1101 | trigger = default_MCA_trigger(idx); | |
1102 | break; | |
1103 | } | |
1104 | case MP_BUS_NEC98: /* NEC 98 pin */ | |
1105 | { | |
1106 | trigger = default_NEC98_trigger(idx); | |
1107 | break; | |
1108 | } | |
1109 | default: | |
1110 | { | |
1111 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1112 | trigger = 1; | |
1113 | break; | |
1114 | } | |
1115 | } | |
1116 | break; | |
1117 | } | |
1118 | case 1: /* edge */ | |
1119 | { | |
1120 | trigger = 0; | |
1121 | break; | |
1122 | } | |
1123 | case 2: /* reserved */ | |
1124 | { | |
1125 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1126 | trigger = 1; | |
1127 | break; | |
1128 | } | |
1129 | case 3: /* level */ | |
1130 | { | |
1131 | trigger = 1; | |
1132 | break; | |
1133 | } | |
1134 | default: /* invalid */ | |
1135 | { | |
1136 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1137 | trigger = 0; | |
1138 | break; | |
1139 | } | |
1140 | } | |
1141 | return trigger; | |
1142 | } | |
1143 | ||
1144 | static inline int irq_polarity(int idx) | |
1145 | { | |
1146 | return MPBIOS_polarity(idx); | |
1147 | } | |
1148 | ||
1149 | static inline int irq_trigger(int idx) | |
1150 | { | |
1151 | return MPBIOS_trigger(idx); | |
1152 | } | |
1153 | ||
1154 | static int pin_2_irq(int idx, int apic, int pin) | |
1155 | { | |
1156 | int irq, i; | |
1157 | int bus = mp_irqs[idx].mpc_srcbus; | |
1158 | ||
1159 | /* | |
1160 | * Debugging check, we are in big trouble if this message pops up! | |
1161 | */ | |
1162 | if (mp_irqs[idx].mpc_dstirq != pin) | |
1163 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
1164 | ||
1165 | switch (mp_bus_id_to_type[bus]) | |
1166 | { | |
1167 | case MP_BUS_ISA: /* ISA pin */ | |
1168 | case MP_BUS_EISA: | |
1169 | case MP_BUS_MCA: | |
1170 | case MP_BUS_NEC98: | |
1171 | { | |
1172 | irq = mp_irqs[idx].mpc_srcbusirq; | |
1173 | break; | |
1174 | } | |
1175 | case MP_BUS_PCI: /* PCI pin */ | |
1176 | { | |
1177 | /* | |
1178 | * PCI IRQs are mapped in order | |
1179 | */ | |
1180 | i = irq = 0; | |
1181 | while (i < apic) | |
1182 | irq += nr_ioapic_registers[i++]; | |
1183 | irq += pin; | |
1184 | ||
1185 | /* | |
1186 | * For MPS mode, so far only needed by ES7000 platform | |
1187 | */ | |
1188 | if (ioapic_renumber_irq) | |
1189 | irq = ioapic_renumber_irq(apic, irq); | |
1190 | ||
1191 | break; | |
1192 | } | |
1193 | default: | |
1194 | { | |
1195 | printk(KERN_ERR "unknown bus type %d.\n",bus); | |
1196 | irq = 0; | |
1197 | break; | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | /* | |
1202 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1203 | */ | |
1204 | if ((pin >= 16) && (pin <= 23)) { | |
1205 | if (pirq_entries[pin-16] != -1) { | |
1206 | if (!pirq_entries[pin-16]) { | |
1207 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1208 | "disabling PIRQ%d\n", pin-16); | |
1209 | } else { | |
1210 | irq = pirq_entries[pin-16]; | |
1211 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1212 | "using PIRQ%d -> IRQ %d\n", | |
1213 | pin-16, irq); | |
1214 | } | |
1215 | } | |
1216 | } | |
1217 | return irq; | |
1218 | } | |
1219 | ||
1220 | static inline int IO_APIC_irq_trigger(int irq) | |
1221 | { | |
1222 | int apic, idx, pin; | |
1223 | ||
1224 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1225 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1226 | idx = find_irq_entry(apic,pin,mp_INT); | |
1227 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
1228 | return irq_trigger(idx); | |
1229 | } | |
1230 | } | |
1231 | /* | |
1232 | * nonexistent IRQs are edge default | |
1233 | */ | |
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
6c231b7b | 1238 | u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1239 | |
ace80ab7 | 1240 | static int __assign_irq_vector(int irq) |
1da177e4 LT |
1241 | { |
1242 | static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; | |
0a1ad60d | 1243 | int vector; |
1da177e4 | 1244 | |
ace80ab7 | 1245 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1246 | |
b940d22d EB |
1247 | if (irq_vector[irq] > 0) |
1248 | return irq_vector[irq]; | |
ace80ab7 | 1249 | |
1da177e4 LT |
1250 | current_vector += 8; |
1251 | if (current_vector == SYSCALL_VECTOR) | |
ace80ab7 | 1252 | current_vector += 8; |
1da177e4 LT |
1253 | |
1254 | if (current_vector >= FIRST_SYSTEM_VECTOR) { | |
1255 | offset++; | |
ace80ab7 | 1256 | if (!(offset % 8)) |
1da177e4 LT |
1257 | return -ENOSPC; |
1258 | current_vector = FIRST_DEVICE_VECTOR + offset; | |
1259 | } | |
1260 | ||
0a1ad60d | 1261 | vector = current_vector; |
b940d22d | 1262 | irq_vector[irq] = vector; |
ace80ab7 EB |
1263 | |
1264 | return vector; | |
1265 | } | |
0a1ad60d | 1266 | |
ace80ab7 EB |
1267 | static int assign_irq_vector(int irq) |
1268 | { | |
1269 | unsigned long flags; | |
1270 | int vector; | |
1271 | ||
1272 | spin_lock_irqsave(&vector_lock, flags); | |
1273 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1274 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1275 | |
0a1ad60d | 1276 | return vector; |
1da177e4 | 1277 | } |
f5b9ed7a | 1278 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1279 | |
1280 | #define IOAPIC_AUTO -1 | |
1281 | #define IOAPIC_EDGE 0 | |
1282 | #define IOAPIC_LEVEL 1 | |
1283 | ||
d1bef4ed | 1284 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1285 | { |
6ebcc00e JB |
1286 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1287 | trigger == IOAPIC_LEVEL) | |
a460e745 IM |
1288 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1289 | handle_fasteoi_irq, "fasteoi"); | |
6ebcc00e | 1290 | else |
a460e745 IM |
1291 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1292 | handle_edge_irq, "edge"); | |
ace80ab7 | 1293 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1294 | } |
1295 | ||
1296 | static void __init setup_IO_APIC_irqs(void) | |
1297 | { | |
1298 | struct IO_APIC_route_entry entry; | |
1299 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1300 | unsigned long flags; | |
1301 | ||
1302 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1303 | ||
1304 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1305 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1306 | ||
1307 | /* | |
1308 | * add it to the IO-APIC irq-routing table: | |
1309 | */ | |
1310 | memset(&entry,0,sizeof(entry)); | |
1311 | ||
1312 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1313 | entry.dest_mode = INT_DEST_MODE; | |
1314 | entry.mask = 0; /* enable IRQ */ | |
1315 | entry.dest.logical.logical_dest = | |
1316 | cpu_mask_to_apicid(TARGET_CPUS); | |
1317 | ||
1318 | idx = find_irq_entry(apic,pin,mp_INT); | |
1319 | if (idx == -1) { | |
1320 | if (first_notcon) { | |
1321 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1322 | " IO-APIC (apicid-pin) %d-%d", | |
1323 | mp_ioapics[apic].mpc_apicid, | |
1324 | pin); | |
1325 | first_notcon = 0; | |
1326 | } else | |
1327 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
1328 | mp_ioapics[apic].mpc_apicid, pin); | |
1329 | continue; | |
1330 | } | |
1331 | ||
1332 | entry.trigger = irq_trigger(idx); | |
1333 | entry.polarity = irq_polarity(idx); | |
1334 | ||
1335 | if (irq_trigger(idx)) { | |
1336 | entry.trigger = 1; | |
1337 | entry.mask = 1; | |
1338 | } | |
1339 | ||
1340 | irq = pin_2_irq(idx, apic, pin); | |
1341 | /* | |
1342 | * skip adding the timer int on secondary nodes, which causes | |
1343 | * a small but painful rift in the time-space continuum | |
1344 | */ | |
1345 | if (multi_timer_check(apic, irq)) | |
1346 | continue; | |
1347 | else | |
1348 | add_pin_to_irq(irq, apic, pin); | |
1349 | ||
1350 | if (!apic && !IO_APIC_IRQ(irq)) | |
1351 | continue; | |
1352 | ||
1353 | if (IO_APIC_IRQ(irq)) { | |
1354 | vector = assign_irq_vector(irq); | |
1355 | entry.vector = vector; | |
1356 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
1357 | ||
1358 | if (!apic && (irq < 16)) | |
1359 | disable_8259A_irq(irq); | |
1360 | } | |
cf4c6a2f | 1361 | ioapic_write_entry(apic, pin, entry); |
1da177e4 | 1362 | spin_lock_irqsave(&ioapic_lock, flags); |
54d5d424 | 1363 | set_native_irq_info(irq, TARGET_CPUS); |
1da177e4 LT |
1364 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1365 | } | |
1366 | } | |
1367 | ||
1368 | if (!first_notcon) | |
1369 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1370 | } | |
1371 | ||
1372 | /* | |
1373 | * Set up the 8259A-master output pin: | |
1374 | */ | |
fcfd636a | 1375 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
1376 | { |
1377 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
1378 | |
1379 | memset(&entry,0,sizeof(entry)); | |
1380 | ||
1381 | disable_8259A_irq(0); | |
1382 | ||
1383 | /* mask LVT0 */ | |
1384 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
1385 | ||
1386 | /* | |
1387 | * We use logical delivery to get the timer IRQ | |
1388 | * to the first CPU. | |
1389 | */ | |
1390 | entry.dest_mode = INT_DEST_MODE; | |
1391 | entry.mask = 0; /* unmask IRQ now */ | |
1392 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
1393 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1394 | entry.polarity = 0; | |
1395 | entry.trigger = 0; | |
1396 | entry.vector = vector; | |
1397 | ||
1398 | /* | |
1399 | * The timer IRQ doesn't have to know that behind the | |
1400 | * scene we have a 8259A-master in AEOI mode ... | |
1401 | */ | |
f5b9ed7a IM |
1402 | irq_desc[0].chip = &ioapic_chip; |
1403 | set_irq_handler(0, handle_edge_irq); | |
1da177e4 LT |
1404 | |
1405 | /* | |
1406 | * Add it to the IO-APIC irq-routing table: | |
1407 | */ | |
cf4c6a2f | 1408 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1409 | |
1410 | enable_8259A_irq(0); | |
1411 | } | |
1412 | ||
1413 | static inline void UNEXPECTED_IO_APIC(void) | |
1414 | { | |
1415 | } | |
1416 | ||
1417 | void __init print_IO_APIC(void) | |
1418 | { | |
1419 | int apic, i; | |
1420 | union IO_APIC_reg_00 reg_00; | |
1421 | union IO_APIC_reg_01 reg_01; | |
1422 | union IO_APIC_reg_02 reg_02; | |
1423 | union IO_APIC_reg_03 reg_03; | |
1424 | unsigned long flags; | |
1425 | ||
1426 | if (apic_verbosity == APIC_QUIET) | |
1427 | return; | |
1428 | ||
1429 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
1430 | for (i = 0; i < nr_ioapics; i++) | |
1431 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
1432 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
1433 | ||
1434 | /* | |
1435 | * We are a bit conservative about what we expect. We have to | |
1436 | * know about every hardware change ASAP. | |
1437 | */ | |
1438 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1439 | ||
1440 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1441 | ||
1442 | spin_lock_irqsave(&ioapic_lock, flags); | |
1443 | reg_00.raw = io_apic_read(apic, 0); | |
1444 | reg_01.raw = io_apic_read(apic, 1); | |
1445 | if (reg_01.bits.version >= 0x10) | |
1446 | reg_02.raw = io_apic_read(apic, 2); | |
1447 | if (reg_01.bits.version >= 0x20) | |
1448 | reg_03.raw = io_apic_read(apic, 3); | |
1449 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1450 | ||
1451 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
1452 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
1453 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1454 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1455 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1456 | if (reg_00.bits.ID >= get_physical_broadcast()) | |
1457 | UNEXPECTED_IO_APIC(); | |
1458 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) | |
1459 | UNEXPECTED_IO_APIC(); | |
1460 | ||
1461 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1462 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1463 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ | |
1464 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ | |
1465 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ | |
1466 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ | |
1467 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ | |
1468 | (reg_01.bits.entries != 0x2E) && | |
1469 | (reg_01.bits.entries != 0x3F) | |
1470 | ) | |
1471 | UNEXPECTED_IO_APIC(); | |
1472 | ||
1473 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1474 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1475 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ | |
1476 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ | |
1477 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ | |
1478 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ | |
1479 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ | |
1480 | ) | |
1481 | UNEXPECTED_IO_APIC(); | |
1482 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) | |
1483 | UNEXPECTED_IO_APIC(); | |
1484 | ||
1485 | /* | |
1486 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1487 | * but the value of reg_02 is read as the previous read register | |
1488 | * value, so ignore it if reg_02 == reg_01. | |
1489 | */ | |
1490 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1491 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1492 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1493 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) | |
1494 | UNEXPECTED_IO_APIC(); | |
1495 | } | |
1496 | ||
1497 | /* | |
1498 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1499 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1500 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1501 | */ | |
1502 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1503 | reg_03.raw != reg_01.raw) { | |
1504 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1505 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1506 | if (reg_03.bits.__reserved_1) | |
1507 | UNEXPECTED_IO_APIC(); | |
1508 | } | |
1509 | ||
1510 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1511 | ||
1512 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1513 | " Stat Dest Deli Vect: \n"); | |
1514 | ||
1515 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1516 | struct IO_APIC_route_entry entry; | |
1517 | ||
cf4c6a2f | 1518 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1519 | |
1520 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1521 | i, | |
1522 | entry.dest.logical.logical_dest, | |
1523 | entry.dest.physical.physical_dest | |
1524 | ); | |
1525 | ||
1526 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1527 | entry.mask, | |
1528 | entry.trigger, | |
1529 | entry.irr, | |
1530 | entry.polarity, | |
1531 | entry.delivery_status, | |
1532 | entry.dest_mode, | |
1533 | entry.delivery_mode, | |
1534 | entry.vector | |
1535 | ); | |
1536 | } | |
1537 | } | |
1da177e4 LT |
1538 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1539 | for (i = 0; i < NR_IRQS; i++) { | |
1540 | struct irq_pin_list *entry = irq_2_pin + i; | |
1541 | if (entry->pin < 0) | |
1542 | continue; | |
ace80ab7 | 1543 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1544 | for (;;) { |
1545 | printk("-> %d:%d", entry->apic, entry->pin); | |
1546 | if (!entry->next) | |
1547 | break; | |
1548 | entry = irq_2_pin + entry->next; | |
1549 | } | |
1550 | printk("\n"); | |
1551 | } | |
1552 | ||
1553 | printk(KERN_INFO ".................................... done.\n"); | |
1554 | ||
1555 | return; | |
1556 | } | |
1557 | ||
1558 | #if 0 | |
1559 | ||
1560 | static void print_APIC_bitfield (int base) | |
1561 | { | |
1562 | unsigned int v; | |
1563 | int i, j; | |
1564 | ||
1565 | if (apic_verbosity == APIC_QUIET) | |
1566 | return; | |
1567 | ||
1568 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1569 | for (i = 0; i < 8; i++) { | |
1570 | v = apic_read(base + i*0x10); | |
1571 | for (j = 0; j < 32; j++) { | |
1572 | if (v & (1<<j)) | |
1573 | printk("1"); | |
1574 | else | |
1575 | printk("0"); | |
1576 | } | |
1577 | printk("\n"); | |
1578 | } | |
1579 | } | |
1580 | ||
1581 | void /*__init*/ print_local_APIC(void * dummy) | |
1582 | { | |
1583 | unsigned int v, ver, maxlvt; | |
1584 | ||
1585 | if (apic_verbosity == APIC_QUIET) | |
1586 | return; | |
1587 | ||
1588 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1589 | smp_processor_id(), hard_smp_processor_id()); | |
1590 | v = apic_read(APIC_ID); | |
1591 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); | |
1592 | v = apic_read(APIC_LVR); | |
1593 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1594 | ver = GET_APIC_VERSION(v); | |
1595 | maxlvt = get_maxlvt(); | |
1596 | ||
1597 | v = apic_read(APIC_TASKPRI); | |
1598 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1599 | ||
1600 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1601 | v = apic_read(APIC_ARBPRI); | |
1602 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1603 | v & APIC_ARBPRI_MASK); | |
1604 | v = apic_read(APIC_PROCPRI); | |
1605 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1606 | } | |
1607 | ||
1608 | v = apic_read(APIC_EOI); | |
1609 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1610 | v = apic_read(APIC_RRR); | |
1611 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1612 | v = apic_read(APIC_LDR); | |
1613 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1614 | v = apic_read(APIC_DFR); | |
1615 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1616 | v = apic_read(APIC_SPIV); | |
1617 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1618 | ||
1619 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1620 | print_APIC_bitfield(APIC_ISR); | |
1621 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1622 | print_APIC_bitfield(APIC_TMR); | |
1623 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1624 | print_APIC_bitfield(APIC_IRR); | |
1625 | ||
1626 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1627 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1628 | apic_write(APIC_ESR, 0); | |
1629 | v = apic_read(APIC_ESR); | |
1630 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1631 | } | |
1632 | ||
1633 | v = apic_read(APIC_ICR); | |
1634 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1635 | v = apic_read(APIC_ICR2); | |
1636 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1637 | ||
1638 | v = apic_read(APIC_LVTT); | |
1639 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1640 | ||
1641 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1642 | v = apic_read(APIC_LVTPC); | |
1643 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1644 | } | |
1645 | v = apic_read(APIC_LVT0); | |
1646 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1647 | v = apic_read(APIC_LVT1); | |
1648 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1649 | ||
1650 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1651 | v = apic_read(APIC_LVTERR); | |
1652 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1653 | } | |
1654 | ||
1655 | v = apic_read(APIC_TMICT); | |
1656 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1657 | v = apic_read(APIC_TMCCT); | |
1658 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1659 | v = apic_read(APIC_TDCR); | |
1660 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1661 | printk("\n"); | |
1662 | } | |
1663 | ||
1664 | void print_all_local_APICs (void) | |
1665 | { | |
1666 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1667 | } | |
1668 | ||
1669 | void /*__init*/ print_PIC(void) | |
1670 | { | |
1da177e4 LT |
1671 | unsigned int v; |
1672 | unsigned long flags; | |
1673 | ||
1674 | if (apic_verbosity == APIC_QUIET) | |
1675 | return; | |
1676 | ||
1677 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1678 | ||
1679 | spin_lock_irqsave(&i8259A_lock, flags); | |
1680 | ||
1681 | v = inb(0xa1) << 8 | inb(0x21); | |
1682 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1683 | ||
1684 | v = inb(0xa0) << 8 | inb(0x20); | |
1685 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1686 | ||
1687 | outb(0x0b,0xa0); | |
1688 | outb(0x0b,0x20); | |
1689 | v = inb(0xa0) << 8 | inb(0x20); | |
1690 | outb(0x0a,0xa0); | |
1691 | outb(0x0a,0x20); | |
1692 | ||
1693 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1694 | ||
1695 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1696 | ||
1697 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1698 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1699 | } | |
1700 | ||
1701 | #endif /* 0 */ | |
1702 | ||
1703 | static void __init enable_IO_APIC(void) | |
1704 | { | |
1705 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1706 | int i8259_apic, i8259_pin; |
1707 | int i, apic; | |
1da177e4 LT |
1708 | unsigned long flags; |
1709 | ||
1710 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1711 | irq_2_pin[i].pin = -1; | |
1712 | irq_2_pin[i].next = 0; | |
1713 | } | |
1714 | if (!pirqs_enabled) | |
1715 | for (i = 0; i < MAX_PIRQS; i++) | |
1716 | pirq_entries[i] = -1; | |
1717 | ||
1718 | /* | |
1719 | * The number of IO-APIC IRQ registers (== #pins): | |
1720 | */ | |
fcfd636a | 1721 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1722 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1723 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1724 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1725 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1726 | } | |
1727 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1728 | int pin; | |
1729 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1730 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1731 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1732 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1733 | |
1734 | ||
1735 | /* If the interrupt line is enabled and in ExtInt mode | |
1736 | * I have found the pin where the i8259 is connected. | |
1737 | */ | |
1738 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1739 | ioapic_i8259.apic = apic; | |
1740 | ioapic_i8259.pin = pin; | |
1741 | goto found_i8259; | |
1742 | } | |
1743 | } | |
1744 | } | |
1745 | found_i8259: | |
1746 | /* Look to see what if the MP table has reported the ExtINT */ | |
1747 | /* If we could not find the appropriate pin by looking at the ioapic | |
1748 | * the i8259 probably is not connected the ioapic but give the | |
1749 | * mptable a chance anyway. | |
1750 | */ | |
1751 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1752 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1753 | /* Trust the MP table if nothing is setup in the hardware */ | |
1754 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1755 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1756 | ioapic_i8259.pin = i8259_pin; | |
1757 | ioapic_i8259.apic = i8259_apic; | |
1758 | } | |
1759 | /* Complain if the MP table and the hardware disagree */ | |
1760 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1761 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1762 | { | |
1763 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1764 | } |
1765 | ||
1766 | /* | |
1767 | * Do not trust the IO-APIC being empty at bootup | |
1768 | */ | |
1769 | clear_IO_APIC(); | |
1770 | } | |
1771 | ||
1772 | /* | |
1773 | * Not an __init, needed by the reboot code | |
1774 | */ | |
1775 | void disable_IO_APIC(void) | |
1776 | { | |
1777 | /* | |
1778 | * Clear the IO-APIC before rebooting: | |
1779 | */ | |
1780 | clear_IO_APIC(); | |
1781 | ||
650927ef | 1782 | /* |
0b968d23 | 1783 | * If the i8259 is routed through an IOAPIC |
650927ef | 1784 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1785 | * so legacy interrupts can be delivered. |
650927ef | 1786 | */ |
fcfd636a | 1787 | if (ioapic_i8259.pin != -1) { |
650927ef | 1788 | struct IO_APIC_route_entry entry; |
650927ef EB |
1789 | |
1790 | memset(&entry, 0, sizeof(entry)); | |
1791 | entry.mask = 0; /* Enabled */ | |
1792 | entry.trigger = 0; /* Edge */ | |
1793 | entry.irr = 0; | |
1794 | entry.polarity = 0; /* High */ | |
1795 | entry.delivery_status = 0; | |
1796 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1797 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1798 | entry.vector = 0; |
76865c3f VG |
1799 | entry.dest.physical.physical_dest = |
1800 | GET_APIC_ID(apic_read(APIC_ID)); | |
650927ef EB |
1801 | |
1802 | /* | |
1803 | * Add it to the IO-APIC irq-routing table: | |
1804 | */ | |
cf4c6a2f | 1805 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1806 | } |
fcfd636a | 1807 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1808 | } |
1809 | ||
1810 | /* | |
1811 | * function to set the IO-APIC physical IDs based on the | |
1812 | * values stored in the MPC table. | |
1813 | * | |
1814 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1815 | */ | |
1816 | ||
1817 | #ifndef CONFIG_X86_NUMAQ | |
1818 | static void __init setup_ioapic_ids_from_mpc(void) | |
1819 | { | |
1820 | union IO_APIC_reg_00 reg_00; | |
1821 | physid_mask_t phys_id_present_map; | |
1822 | int apic; | |
1823 | int i; | |
1824 | unsigned char old_id; | |
1825 | unsigned long flags; | |
1826 | ||
ca05fea6 NP |
1827 | /* |
1828 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1829 | * no meaning without the serial APIC bus. | |
1830 | */ | |
7c5c1e42 SL |
1831 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1832 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1833 | return; |
1da177e4 LT |
1834 | /* |
1835 | * This is broken; anything with a real cpu count has to | |
1836 | * circumvent this idiocy regardless. | |
1837 | */ | |
1838 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1839 | ||
1840 | /* | |
1841 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1842 | */ | |
1843 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1844 | ||
1845 | /* Read the register 0 value */ | |
1846 | spin_lock_irqsave(&ioapic_lock, flags); | |
1847 | reg_00.raw = io_apic_read(apic, 0); | |
1848 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1849 | ||
1850 | old_id = mp_ioapics[apic].mpc_apicid; | |
1851 | ||
1852 | if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { | |
1853 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", | |
1854 | apic, mp_ioapics[apic].mpc_apicid); | |
1855 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1856 | reg_00.bits.ID); | |
1857 | mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; | |
1858 | } | |
1859 | ||
1da177e4 LT |
1860 | /* |
1861 | * Sanity check, is the ID really free? Every APIC in a | |
1862 | * system must have a unique ID or we get lots of nice | |
1863 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1864 | */ | |
1865 | if (check_apicid_used(phys_id_present_map, | |
1866 | mp_ioapics[apic].mpc_apicid)) { | |
1867 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", | |
1868 | apic, mp_ioapics[apic].mpc_apicid); | |
1869 | for (i = 0; i < get_physical_broadcast(); i++) | |
1870 | if (!physid_isset(i, phys_id_present_map)) | |
1871 | break; | |
1872 | if (i >= get_physical_broadcast()) | |
1873 | panic("Max APIC ID exceeded!\n"); | |
1874 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1875 | i); | |
1876 | physid_set(i, phys_id_present_map); | |
1877 | mp_ioapics[apic].mpc_apicid = i; | |
1878 | } else { | |
1879 | physid_mask_t tmp; | |
1880 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); | |
1881 | apic_printk(APIC_VERBOSE, "Setting %d in the " | |
1882 | "phys_id_present_map\n", | |
1883 | mp_ioapics[apic].mpc_apicid); | |
1884 | physids_or(phys_id_present_map, phys_id_present_map, tmp); | |
1885 | } | |
1886 | ||
1887 | ||
1888 | /* | |
1889 | * We need to adjust the IRQ routing table | |
1890 | * if the ID changed. | |
1891 | */ | |
1892 | if (old_id != mp_ioapics[apic].mpc_apicid) | |
1893 | for (i = 0; i < mp_irq_entries; i++) | |
1894 | if (mp_irqs[i].mpc_dstapic == old_id) | |
1895 | mp_irqs[i].mpc_dstapic | |
1896 | = mp_ioapics[apic].mpc_apicid; | |
1897 | ||
1898 | /* | |
1899 | * Read the right value from the MPC table and | |
1900 | * write it into the ID register. | |
1901 | */ | |
1902 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1903 | "...changing IO-APIC physical APIC ID to %d ...", | |
1904 | mp_ioapics[apic].mpc_apicid); | |
1905 | ||
1906 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; | |
1907 | spin_lock_irqsave(&ioapic_lock, flags); | |
1908 | io_apic_write(apic, 0, reg_00.raw); | |
1909 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1910 | ||
1911 | /* | |
1912 | * Sanity check | |
1913 | */ | |
1914 | spin_lock_irqsave(&ioapic_lock, flags); | |
1915 | reg_00.raw = io_apic_read(apic, 0); | |
1916 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1917 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) | |
1918 | printk("could not set ID!\n"); | |
1919 | else | |
1920 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1921 | } | |
1922 | } | |
1923 | #else | |
1924 | static void __init setup_ioapic_ids_from_mpc(void) { } | |
1925 | #endif | |
1926 | ||
1927 | /* | |
1928 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1929 | * about the timer IRQ. We do the following to work around the situation: | |
1930 | * | |
1931 | * - timer IRQ defaults to IO-APIC IRQ | |
1932 | * - if this function detects that timer IRQs are defunct, then we fall | |
1933 | * back to ISA timer IRQs | |
1934 | */ | |
1935 | static int __init timer_irq_works(void) | |
1936 | { | |
1937 | unsigned long t1 = jiffies; | |
1938 | ||
1939 | local_irq_enable(); | |
1940 | /* Let ten ticks pass... */ | |
1941 | mdelay((10 * 1000) / HZ); | |
1942 | ||
1943 | /* | |
1944 | * Expect a few ticks at least, to be sure some possible | |
1945 | * glue logic does not lock up after one or two first | |
1946 | * ticks in a non-ExtINT mode. Also the local APIC | |
1947 | * might have cached one ExtINT interrupt. Finally, at | |
1948 | * least one tick may be lost due to delays. | |
1949 | */ | |
1950 | if (jiffies - t1 > 4) | |
1951 | return 1; | |
1952 | ||
1953 | return 0; | |
1954 | } | |
1955 | ||
1956 | /* | |
1957 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1958 | * number of pending IRQ events unhandled. These cases are very rare, | |
1959 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1960 | * better to do it this way as thus we do not have to be aware of | |
1961 | * 'pending' interrupts in the IRQ path, except at this point. | |
1962 | */ | |
1963 | /* | |
1964 | * Edge triggered needs to resend any interrupt | |
1965 | * that was delayed but this is now handled in the device | |
1966 | * independent code. | |
1967 | */ | |
1968 | ||
1969 | /* | |
f5b9ed7a IM |
1970 | * Startup quirk: |
1971 | * | |
1da177e4 LT |
1972 | * Starting up a edge-triggered IO-APIC interrupt is |
1973 | * nasty - we need to make sure that we get the edge. | |
1974 | * If it is already asserted for some reason, we need | |
1975 | * return 1 to indicate that is was pending. | |
1976 | * | |
1977 | * This is not complete - we should be able to fake | |
1978 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1979 | * |
1980 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1981 | */ |
f5b9ed7a | 1982 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1983 | { |
1984 | int was_pending = 0; | |
1985 | unsigned long flags; | |
1986 | ||
1987 | spin_lock_irqsave(&ioapic_lock, flags); | |
1988 | if (irq < 16) { | |
1989 | disable_8259A_irq(irq); | |
1990 | if (i8259A_irq_pending(irq)) | |
1991 | was_pending = 1; | |
1992 | } | |
1993 | __unmask_IO_APIC_irq(irq); | |
1994 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1995 | ||
1996 | return was_pending; | |
1997 | } | |
1998 | ||
f5b9ed7a | 1999 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 2000 | { |
ace80ab7 | 2001 | move_native_irq(irq); |
1da177e4 LT |
2002 | ack_APIC_irq(); |
2003 | } | |
2004 | ||
f5b9ed7a | 2005 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
2006 | { |
2007 | unsigned long v; | |
2008 | int i; | |
2009 | ||
ace80ab7 | 2010 | move_native_irq(irq); |
1da177e4 LT |
2011 | /* |
2012 | * It appears there is an erratum which affects at least version 0x11 | |
2013 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2014 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2015 | * erroneously delivered as edge-triggered one but the respective IRR | |
2016 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2017 | * message but it will never arrive and further interrupts are blocked | |
2018 | * from the source. The exact reason is so far unknown, but the | |
2019 | * phenomenon was observed when two consecutive interrupt requests | |
2020 | * from a given source get delivered to the same CPU and the source is | |
2021 | * temporarily disabled in between. | |
2022 | * | |
2023 | * A workaround is to simulate an EOI message manually. We achieve it | |
2024 | * by setting the trigger mode to edge and then to level when the edge | |
2025 | * trigger mode gets detected in the TMR of a local APIC for a | |
2026 | * level-triggered interrupt. We mask the source for the time of the | |
2027 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2028 | * The idea is from Manfred Spraul. --macro | |
2029 | */ | |
b940d22d | 2030 | i = irq_vector[irq]; |
1da177e4 LT |
2031 | |
2032 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2033 | ||
2034 | ack_APIC_irq(); | |
2035 | ||
2036 | if (!(v & (1 << (i & 0x1f)))) { | |
2037 | atomic_inc(&irq_mis_count); | |
2038 | spin_lock(&ioapic_lock); | |
2039 | __mask_and_edge_IO_APIC_irq(irq); | |
2040 | __unmask_and_level_IO_APIC_irq(irq); | |
2041 | spin_unlock(&ioapic_lock); | |
2042 | } | |
2043 | } | |
2044 | ||
ace80ab7 | 2045 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2046 | { |
b940d22d | 2047 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
2048 | |
2049 | return 1; | |
2050 | } | |
2051 | ||
f5b9ed7a IM |
2052 | static struct irq_chip ioapic_chip __read_mostly = { |
2053 | .name = "IO-APIC", | |
ace80ab7 EB |
2054 | .startup = startup_ioapic_irq, |
2055 | .mask = mask_IO_APIC_irq, | |
2056 | .unmask = unmask_IO_APIC_irq, | |
2057 | .ack = ack_ioapic_irq, | |
2058 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 2059 | #ifdef CONFIG_SMP |
ace80ab7 | 2060 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2061 | #endif |
ace80ab7 | 2062 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2063 | }; |
2064 | ||
1da177e4 LT |
2065 | |
2066 | static inline void init_IO_APIC_traps(void) | |
2067 | { | |
2068 | int irq; | |
2069 | ||
2070 | /* | |
2071 | * NOTE! The local APIC isn't very good at handling | |
2072 | * multiple interrupts at the same interrupt level. | |
2073 | * As the interrupt level is determined by taking the | |
2074 | * vector number and shifting that right by 4, we | |
2075 | * want to spread these out a bit so that they don't | |
2076 | * all fall in the same interrupt level. | |
2077 | * | |
2078 | * Also, we've got to be careful not to trash gate | |
2079 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2080 | */ | |
2081 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
2082 | int tmp = irq; | |
b940d22d | 2083 | if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) { |
1da177e4 LT |
2084 | /* |
2085 | * Hmm.. We don't have an entry for this, | |
2086 | * so default to an old-fashioned 8259 | |
2087 | * interrupt if we can.. | |
2088 | */ | |
2089 | if (irq < 16) | |
2090 | make_8259A_irq(irq); | |
2091 | else | |
2092 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2093 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2094 | } |
2095 | } | |
2096 | } | |
2097 | ||
f5b9ed7a IM |
2098 | /* |
2099 | * The local APIC irq-chip implementation: | |
2100 | */ | |
1da177e4 | 2101 | |
f5b9ed7a IM |
2102 | static void ack_apic(unsigned int irq) |
2103 | { | |
2104 | ack_APIC_irq(); | |
1da177e4 LT |
2105 | } |
2106 | ||
f5b9ed7a | 2107 | static void mask_lapic_irq (unsigned int irq) |
1da177e4 LT |
2108 | { |
2109 | unsigned long v; | |
2110 | ||
2111 | v = apic_read(APIC_LVT0); | |
2112 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
2113 | } | |
2114 | ||
f5b9ed7a | 2115 | static void unmask_lapic_irq (unsigned int irq) |
1da177e4 | 2116 | { |
f5b9ed7a | 2117 | unsigned long v; |
1da177e4 | 2118 | |
f5b9ed7a IM |
2119 | v = apic_read(APIC_LVT0); |
2120 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
2121 | } | |
1da177e4 | 2122 | |
f5b9ed7a IM |
2123 | static struct irq_chip lapic_chip __read_mostly = { |
2124 | .name = "local-APIC-edge", | |
2125 | .mask = mask_lapic_irq, | |
2126 | .unmask = unmask_lapic_irq, | |
2127 | .eoi = ack_apic, | |
1da177e4 LT |
2128 | }; |
2129 | ||
2130 | static void setup_nmi (void) | |
2131 | { | |
2132 | /* | |
2133 | * Dirty trick to enable the NMI watchdog ... | |
2134 | * We put the 8259A master into AEOI mode and | |
2135 | * unmask on all local APICs LVT0 as NMI. | |
2136 | * | |
2137 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2138 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2139 | * the NMI handler or the timer interrupt. | |
2140 | */ | |
2141 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); | |
2142 | ||
2143 | on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1); | |
2144 | ||
2145 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2146 | } | |
2147 | ||
2148 | /* | |
2149 | * This looks a bit hackish but it's about the only one way of sending | |
2150 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2151 | * not support the ExtINT mode, unfortunately. We need to send these | |
2152 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2153 | * 8259A interrupt line asserted until INTA. --macro | |
2154 | */ | |
2155 | static inline void unlock_ExtINT_logic(void) | |
2156 | { | |
fcfd636a | 2157 | int apic, pin, i; |
1da177e4 LT |
2158 | struct IO_APIC_route_entry entry0, entry1; |
2159 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2160 | |
fcfd636a EB |
2161 | pin = find_isa_irq_pin(8, mp_INT); |
2162 | apic = find_isa_irq_apic(8, mp_INT); | |
1da177e4 LT |
2163 | if (pin == -1) |
2164 | return; | |
2165 | ||
cf4c6a2f | 2166 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2167 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2168 | |
2169 | memset(&entry1, 0, sizeof(entry1)); | |
2170 | ||
2171 | entry1.dest_mode = 0; /* physical delivery */ | |
2172 | entry1.mask = 0; /* unmask IRQ now */ | |
2173 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2174 | entry1.delivery_mode = dest_ExtINT; | |
2175 | entry1.polarity = entry0.polarity; | |
2176 | entry1.trigger = 0; | |
2177 | entry1.vector = 0; | |
2178 | ||
cf4c6a2f | 2179 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2180 | |
2181 | save_control = CMOS_READ(RTC_CONTROL); | |
2182 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2183 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2184 | RTC_FREQ_SELECT); | |
2185 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2186 | ||
2187 | i = 100; | |
2188 | while (i-- > 0) { | |
2189 | mdelay(10); | |
2190 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2191 | i -= 10; | |
2192 | } | |
2193 | ||
2194 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2195 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2196 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2197 | |
cf4c6a2f | 2198 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2199 | } |
2200 | ||
e0c1e9bf KM |
2201 | int timer_uses_ioapic_pin_0; |
2202 | ||
1da177e4 LT |
2203 | /* |
2204 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2205 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2206 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2207 | * fanatically on his truly buggy board. | |
2208 | */ | |
2209 | static inline void check_timer(void) | |
2210 | { | |
fcfd636a | 2211 | int apic1, pin1, apic2, pin2; |
1da177e4 LT |
2212 | int vector; |
2213 | ||
2214 | /* | |
2215 | * get/set the timer IRQ vector: | |
2216 | */ | |
2217 | disable_8259A_irq(0); | |
2218 | vector = assign_irq_vector(0); | |
2219 | set_intr_gate(vector, interrupt[0]); | |
2220 | ||
2221 | /* | |
2222 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
2223 | * mode for the 8259A whenever interrupts are routed | |
2224 | * through I/O APICs. Also IRQ0 has to be enabled in | |
2225 | * the 8259A which implies the virtual wire has to be | |
2226 | * disabled in the local APIC. | |
2227 | */ | |
2228 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
2229 | init_8259A(1); | |
2230 | timer_ack = 1; | |
f9262c12 AK |
2231 | if (timer_over_8254 > 0) |
2232 | enable_8259A_irq(0); | |
1da177e4 | 2233 | |
fcfd636a EB |
2234 | pin1 = find_isa_irq_pin(0, mp_INT); |
2235 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2236 | pin2 = ioapic_i8259.pin; | |
2237 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2238 | |
e0c1e9bf KM |
2239 | if (pin1 == 0) |
2240 | timer_uses_ioapic_pin_0 = 1; | |
2241 | ||
fcfd636a EB |
2242 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2243 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 LT |
2244 | |
2245 | if (pin1 != -1) { | |
2246 | /* | |
2247 | * Ok, does IRQ0 through the IOAPIC work? | |
2248 | */ | |
2249 | unmask_IO_APIC_irq(0); | |
2250 | if (timer_irq_works()) { | |
2251 | if (nmi_watchdog == NMI_IO_APIC) { | |
2252 | disable_8259A_irq(0); | |
2253 | setup_nmi(); | |
2254 | enable_8259A_irq(0); | |
1da177e4 | 2255 | } |
66759a01 CE |
2256 | if (disable_timer_pin_1 > 0) |
2257 | clear_IO_APIC_pin(0, pin1); | |
1da177e4 LT |
2258 | return; |
2259 | } | |
fcfd636a EB |
2260 | clear_IO_APIC_pin(apic1, pin1); |
2261 | printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " | |
2262 | "IO-APIC\n"); | |
1da177e4 LT |
2263 | } |
2264 | ||
2265 | printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); | |
2266 | if (pin2 != -1) { | |
2267 | printk("\n..... (found pin %d) ...", pin2); | |
2268 | /* | |
2269 | * legacy devices should be connected to IO APIC #0 | |
2270 | */ | |
fcfd636a | 2271 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
1da177e4 LT |
2272 | if (timer_irq_works()) { |
2273 | printk("works.\n"); | |
2274 | if (pin1 != -1) | |
fcfd636a | 2275 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
1da177e4 | 2276 | else |
fcfd636a | 2277 | add_pin_to_irq(0, apic2, pin2); |
1da177e4 LT |
2278 | if (nmi_watchdog == NMI_IO_APIC) { |
2279 | setup_nmi(); | |
1da177e4 LT |
2280 | } |
2281 | return; | |
2282 | } | |
2283 | /* | |
2284 | * Cleanup, just in case ... | |
2285 | */ | |
fcfd636a | 2286 | clear_IO_APIC_pin(apic2, pin2); |
1da177e4 LT |
2287 | } |
2288 | printk(" failed.\n"); | |
2289 | ||
2290 | if (nmi_watchdog == NMI_IO_APIC) { | |
2291 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
2292 | nmi_watchdog = 0; | |
2293 | } | |
2294 | ||
2295 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2296 | ||
2297 | disable_8259A_irq(0); | |
a460e745 IM |
2298 | set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, |
2299 | "fasteio"); | |
1da177e4 LT |
2300 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2301 | enable_8259A_irq(0); | |
2302 | ||
2303 | if (timer_irq_works()) { | |
2304 | printk(" works.\n"); | |
2305 | return; | |
2306 | } | |
2307 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); | |
2308 | printk(" failed.\n"); | |
2309 | ||
2310 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2311 | ||
2312 | timer_ack = 0; | |
2313 | init_8259A(0); | |
2314 | make_8259A_irq(0); | |
2315 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
2316 | ||
2317 | unlock_ExtINT_logic(); | |
2318 | ||
2319 | if (timer_irq_works()) { | |
2320 | printk(" works.\n"); | |
2321 | return; | |
2322 | } | |
2323 | printk(" failed :(.\n"); | |
2324 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2325 | "report. Then try booting with the 'noapic' option"); | |
2326 | } | |
2327 | ||
2328 | /* | |
2329 | * | |
2330 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
2331 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
2332 | * Linux doesn't really care, as it's not actually used | |
2333 | * for any interrupt handling anyway. | |
2334 | */ | |
2335 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2336 | ||
2337 | void __init setup_IO_APIC(void) | |
2338 | { | |
2339 | enable_IO_APIC(); | |
2340 | ||
2341 | if (acpi_ioapic) | |
2342 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
2343 | else | |
2344 | io_apic_irqs = ~PIC_IRQS; | |
2345 | ||
2346 | printk("ENABLING IO-APIC IRQs\n"); | |
2347 | ||
2348 | /* | |
2349 | * Set up IO-APIC IRQ routing. | |
2350 | */ | |
2351 | if (!acpi_ioapic) | |
2352 | setup_ioapic_ids_from_mpc(); | |
2353 | sync_Arb_IDs(); | |
2354 | setup_IO_APIC_irqs(); | |
2355 | init_IO_APIC_traps(); | |
1e4c85f9 | 2356 | check_timer(); |
1da177e4 LT |
2357 | if (!acpi_ioapic) |
2358 | print_IO_APIC(); | |
2359 | } | |
2360 | ||
f9262c12 AK |
2361 | static int __init setup_disable_8254_timer(char *s) |
2362 | { | |
2363 | timer_over_8254 = -1; | |
2364 | return 1; | |
2365 | } | |
2366 | static int __init setup_enable_8254_timer(char *s) | |
2367 | { | |
2368 | timer_over_8254 = 2; | |
2369 | return 1; | |
2370 | } | |
2371 | ||
2372 | __setup("disable_8254_timer", setup_disable_8254_timer); | |
2373 | __setup("enable_8254_timer", setup_enable_8254_timer); | |
2374 | ||
1da177e4 LT |
2375 | /* |
2376 | * Called after all the initialization is done. If we didnt find any | |
2377 | * APIC bugs then we can allow the modify fast path | |
2378 | */ | |
2379 | ||
2380 | static int __init io_apic_bug_finalize(void) | |
2381 | { | |
2382 | if(sis_apic_bug == -1) | |
2383 | sis_apic_bug = 0; | |
2384 | return 0; | |
2385 | } | |
2386 | ||
2387 | late_initcall(io_apic_bug_finalize); | |
2388 | ||
2389 | struct sysfs_ioapic_data { | |
2390 | struct sys_device dev; | |
2391 | struct IO_APIC_route_entry entry[0]; | |
2392 | }; | |
2393 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
2394 | ||
438510f6 | 2395 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2396 | { |
2397 | struct IO_APIC_route_entry *entry; | |
2398 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
2399 | int i; |
2400 | ||
2401 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2402 | entry = data->entry; | |
cf4c6a2f AK |
2403 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2404 | entry[i] = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2405 | |
2406 | return 0; | |
2407 | } | |
2408 | ||
2409 | static int ioapic_resume(struct sys_device *dev) | |
2410 | { | |
2411 | struct IO_APIC_route_entry *entry; | |
2412 | struct sysfs_ioapic_data *data; | |
2413 | unsigned long flags; | |
2414 | union IO_APIC_reg_00 reg_00; | |
2415 | int i; | |
2416 | ||
2417 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2418 | entry = data->entry; | |
2419 | ||
2420 | spin_lock_irqsave(&ioapic_lock, flags); | |
2421 | reg_00.raw = io_apic_read(dev->id, 0); | |
2422 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
2423 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
2424 | io_apic_write(dev->id, 0, reg_00.raw); | |
2425 | } | |
1da177e4 | 2426 | spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
2427 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2428 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
2429 | |
2430 | return 0; | |
2431 | } | |
2432 | ||
2433 | static struct sysdev_class ioapic_sysdev_class = { | |
2434 | set_kset_name("ioapic"), | |
2435 | .suspend = ioapic_suspend, | |
2436 | .resume = ioapic_resume, | |
2437 | }; | |
2438 | ||
2439 | static int __init ioapic_init_sysfs(void) | |
2440 | { | |
2441 | struct sys_device * dev; | |
2442 | int i, size, error = 0; | |
2443 | ||
2444 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2445 | if (error) | |
2446 | return error; | |
2447 | ||
2448 | for (i = 0; i < nr_ioapics; i++ ) { | |
2449 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
2450 | * sizeof(struct IO_APIC_route_entry); | |
2451 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
2452 | if (!mp_ioapic_data[i]) { | |
2453 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2454 | continue; | |
2455 | } | |
2456 | memset(mp_ioapic_data[i], 0, size); | |
2457 | dev = &mp_ioapic_data[i]->dev; | |
2458 | dev->id = i; | |
2459 | dev->cls = &ioapic_sysdev_class; | |
2460 | error = sysdev_register(dev); | |
2461 | if (error) { | |
2462 | kfree(mp_ioapic_data[i]); | |
2463 | mp_ioapic_data[i] = NULL; | |
2464 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2465 | continue; | |
2466 | } | |
2467 | } | |
2468 | ||
2469 | return 0; | |
2470 | } | |
2471 | ||
2472 | device_initcall(ioapic_init_sysfs); | |
2473 | ||
3fc471ed | 2474 | /* |
95d77884 | 2475 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2476 | */ |
2477 | int create_irq(void) | |
2478 | { | |
ace80ab7 EB |
2479 | /* Allocate an unused irq */ |
2480 | int irq, new, vector; | |
3fc471ed | 2481 | unsigned long flags; |
3fc471ed | 2482 | |
ace80ab7 EB |
2483 | irq = -ENOSPC; |
2484 | spin_lock_irqsave(&vector_lock, flags); | |
2485 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2486 | if (platform_legacy_irq(new)) | |
2487 | continue; | |
2488 | if (irq_vector[new] != 0) | |
2489 | continue; | |
2490 | vector = __assign_irq_vector(new); | |
2491 | if (likely(vector > 0)) | |
2492 | irq = new; | |
2493 | break; | |
2494 | } | |
2495 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2496 | |
ace80ab7 | 2497 | if (irq >= 0) { |
3fc471ed | 2498 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2499 | dynamic_irq_init(irq); |
2500 | } | |
2501 | return irq; | |
2502 | } | |
2503 | ||
2504 | void destroy_irq(unsigned int irq) | |
2505 | { | |
2506 | unsigned long flags; | |
3fc471ed EB |
2507 | |
2508 | dynamic_irq_cleanup(irq); | |
2509 | ||
2510 | spin_lock_irqsave(&vector_lock, flags); | |
3fc471ed EB |
2511 | irq_vector[irq] = 0; |
2512 | spin_unlock_irqrestore(&vector_lock, flags); | |
2513 | } | |
3fc471ed | 2514 | |
2d3fcc1c EB |
2515 | /* |
2516 | * MSI mesage composition | |
2517 | */ | |
2518 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2519 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2520 | { |
2d3fcc1c EB |
2521 | int vector; |
2522 | unsigned dest; | |
2523 | ||
2524 | vector = assign_irq_vector(irq); | |
2525 | if (vector >= 0) { | |
2526 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2527 | ||
2528 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2529 | msg->address_lo = | |
2530 | MSI_ADDR_BASE_LO | | |
2531 | ((INT_DEST_MODE == 0) ? | |
2532 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2533 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2534 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2535 | MSI_ADDR_REDIRECTION_CPU: | |
2536 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2537 | MSI_ADDR_DEST_ID(dest); | |
2538 | ||
2539 | msg->data = | |
2540 | MSI_DATA_TRIGGER_EDGE | | |
2541 | MSI_DATA_LEVEL_ASSERT | | |
2542 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2543 | MSI_DATA_DELIVERY_FIXED: | |
2544 | MSI_DATA_DELIVERY_LOWPRI) | | |
2545 | MSI_DATA_VECTOR(vector); | |
2546 | } | |
2547 | return vector; | |
2548 | } | |
2549 | ||
3b7d1921 EB |
2550 | #ifdef CONFIG_SMP |
2551 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2552 | { |
3b7d1921 EB |
2553 | struct msi_msg msg; |
2554 | unsigned int dest; | |
2555 | cpumask_t tmp; | |
2d3fcc1c | 2556 | int vector; |
3b7d1921 EB |
2557 | |
2558 | cpus_and(tmp, mask, cpu_online_map); | |
2559 | if (cpus_empty(tmp)) | |
2560 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2561 | |
2562 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2563 | if (vector < 0) |
2564 | return; | |
2d3fcc1c | 2565 | |
3b7d1921 EB |
2566 | dest = cpu_mask_to_apicid(mask); |
2567 | ||
2568 | read_msi_msg(irq, &msg); | |
2569 | ||
2570 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2571 | msg.data |= MSI_DATA_VECTOR(vector); | |
2572 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2573 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2574 | ||
2575 | write_msi_msg(irq, &msg); | |
2576 | set_native_irq_info(irq, mask); | |
2d3fcc1c | 2577 | } |
3b7d1921 | 2578 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2579 | |
3b7d1921 EB |
2580 | /* |
2581 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2582 | * which implement the MSI or MSI-X Capability Structure. | |
2583 | */ | |
2584 | static struct irq_chip msi_chip = { | |
2585 | .name = "PCI-MSI", | |
2586 | .unmask = unmask_msi_irq, | |
2587 | .mask = mask_msi_irq, | |
2588 | .ack = ack_ioapic_irq, | |
2589 | #ifdef CONFIG_SMP | |
2590 | .set_affinity = set_msi_irq_affinity, | |
2591 | #endif | |
2592 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2593 | }; |
2594 | ||
3b7d1921 EB |
2595 | int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev) |
2596 | { | |
2597 | struct msi_msg msg; | |
2598 | int ret; | |
2599 | ret = msi_compose_msg(dev, irq, &msg); | |
2600 | if (ret < 0) | |
2601 | return ret; | |
2602 | ||
2603 | write_msi_msg(irq, &msg); | |
2604 | ||
a460e745 IM |
2605 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2606 | "edge"); | |
3b7d1921 EB |
2607 | |
2608 | return 0; | |
2609 | } | |
2610 | ||
2611 | void arch_teardown_msi_irq(unsigned int irq) | |
2612 | { | |
2613 | return; | |
2614 | } | |
2615 | ||
2d3fcc1c EB |
2616 | #endif /* CONFIG_PCI_MSI */ |
2617 | ||
8b955b0d EB |
2618 | /* |
2619 | * Hypertransport interrupt support | |
2620 | */ | |
2621 | #ifdef CONFIG_HT_IRQ | |
2622 | ||
2623 | #ifdef CONFIG_SMP | |
2624 | ||
2625 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2626 | { | |
2627 | u32 low, high; | |
2628 | low = read_ht_irq_low(irq); | |
2629 | high = read_ht_irq_high(irq); | |
2630 | ||
2631 | low &= ~(HT_IRQ_LOW_DEST_ID_MASK); | |
2632 | high &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
2633 | ||
2634 | low |= HT_IRQ_LOW_DEST_ID(dest); | |
2635 | high |= HT_IRQ_HIGH_DEST_ID(dest); | |
2636 | ||
2637 | write_ht_irq_low(irq, low); | |
2638 | write_ht_irq_high(irq, high); | |
2639 | } | |
2640 | ||
2641 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2642 | { | |
2643 | unsigned int dest; | |
2644 | cpumask_t tmp; | |
2645 | ||
2646 | cpus_and(tmp, mask, cpu_online_map); | |
2647 | if (cpus_empty(tmp)) | |
2648 | tmp = TARGET_CPUS; | |
2649 | ||
2650 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2651 | ||
2652 | dest = cpu_mask_to_apicid(mask); | |
2653 | ||
2654 | target_ht_irq(irq, dest); | |
2655 | set_native_irq_info(irq, mask); | |
2656 | } | |
2657 | #endif | |
2658 | ||
c37e108d | 2659 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2660 | .name = "PCI-HT", |
2661 | .mask = mask_ht_irq, | |
2662 | .unmask = unmask_ht_irq, | |
2663 | .ack = ack_ioapic_irq, | |
2664 | #ifdef CONFIG_SMP | |
2665 | .set_affinity = set_ht_irq_affinity, | |
2666 | #endif | |
2667 | .retrigger = ioapic_retrigger_irq, | |
2668 | }; | |
2669 | ||
2670 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2671 | { | |
2672 | int vector; | |
2673 | ||
2674 | vector = assign_irq_vector(irq); | |
2675 | if (vector >= 0) { | |
2676 | u32 low, high; | |
2677 | unsigned dest; | |
2678 | cpumask_t tmp; | |
2679 | ||
2680 | cpus_clear(tmp); | |
2681 | cpu_set(vector >> 8, tmp); | |
2682 | dest = cpu_mask_to_apicid(tmp); | |
2683 | ||
2684 | high = HT_IRQ_HIGH_DEST_ID(dest); | |
2685 | ||
2686 | low = HT_IRQ_LOW_BASE | | |
2687 | HT_IRQ_LOW_DEST_ID(dest) | | |
2688 | HT_IRQ_LOW_VECTOR(vector) | | |
2689 | ((INT_DEST_MODE == 0) ? | |
2690 | HT_IRQ_LOW_DM_PHYSICAL : | |
2691 | HT_IRQ_LOW_DM_LOGICAL) | | |
2692 | HT_IRQ_LOW_RQEOI_EDGE | | |
2693 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2694 | HT_IRQ_LOW_MT_FIXED : | |
2695 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2696 | HT_IRQ_LOW_IRQ_MASKED; | |
2697 | ||
2698 | write_ht_irq_low(irq, low); | |
2699 | write_ht_irq_high(irq, high); | |
2700 | ||
a460e745 IM |
2701 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2702 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2703 | } |
2704 | return vector; | |
2705 | } | |
2706 | #endif /* CONFIG_HT_IRQ */ | |
2707 | ||
1da177e4 LT |
2708 | /* -------------------------------------------------------------------------- |
2709 | ACPI-based IOAPIC Configuration | |
2710 | -------------------------------------------------------------------------- */ | |
2711 | ||
888ba6c6 | 2712 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2713 | |
2714 | int __init io_apic_get_unique_id (int ioapic, int apic_id) | |
2715 | { | |
2716 | union IO_APIC_reg_00 reg_00; | |
2717 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2718 | physid_mask_t tmp; | |
2719 | unsigned long flags; | |
2720 | int i = 0; | |
2721 | ||
2722 | /* | |
2723 | * The P4 platform supports up to 256 APIC IDs on two separate APIC | |
2724 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
2725 | * supports up to 16 on one shared APIC bus. | |
2726 | * | |
2727 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full | |
2728 | * advantage of new APIC bus architecture. | |
2729 | */ | |
2730 | ||
2731 | if (physids_empty(apic_id_map)) | |
2732 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2733 | ||
2734 | spin_lock_irqsave(&ioapic_lock, flags); | |
2735 | reg_00.raw = io_apic_read(ioapic, 0); | |
2736 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2737 | ||
2738 | if (apic_id >= get_physical_broadcast()) { | |
2739 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2740 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2741 | apic_id = reg_00.bits.ID; | |
2742 | } | |
2743 | ||
2744 | /* | |
2745 | * Every APIC in a system must have a unique ID or we get lots of nice | |
2746 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2747 | */ | |
2748 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2749 | ||
2750 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2751 | if (!check_apicid_used(apic_id_map, i)) | |
2752 | break; | |
2753 | } | |
2754 | ||
2755 | if (i == get_physical_broadcast()) | |
2756 | panic("Max apic_id exceeded!\n"); | |
2757 | ||
2758 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2759 | "trying %d\n", ioapic, apic_id, i); | |
2760 | ||
2761 | apic_id = i; | |
2762 | } | |
2763 | ||
2764 | tmp = apicid_to_cpu_present(apic_id); | |
2765 | physids_or(apic_id_map, apic_id_map, tmp); | |
2766 | ||
2767 | if (reg_00.bits.ID != apic_id) { | |
2768 | reg_00.bits.ID = apic_id; | |
2769 | ||
2770 | spin_lock_irqsave(&ioapic_lock, flags); | |
2771 | io_apic_write(ioapic, 0, reg_00.raw); | |
2772 | reg_00.raw = io_apic_read(ioapic, 0); | |
2773 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2774 | ||
2775 | /* Sanity check */ | |
6070f9ec AD |
2776 | if (reg_00.bits.ID != apic_id) { |
2777 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2778 | return -1; | |
2779 | } | |
1da177e4 LT |
2780 | } |
2781 | ||
2782 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2783 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2784 | ||
2785 | return apic_id; | |
2786 | } | |
2787 | ||
2788 | ||
2789 | int __init io_apic_get_version (int ioapic) | |
2790 | { | |
2791 | union IO_APIC_reg_01 reg_01; | |
2792 | unsigned long flags; | |
2793 | ||
2794 | spin_lock_irqsave(&ioapic_lock, flags); | |
2795 | reg_01.raw = io_apic_read(ioapic, 1); | |
2796 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2797 | ||
2798 | return reg_01.bits.version; | |
2799 | } | |
2800 | ||
2801 | ||
2802 | int __init io_apic_get_redir_entries (int ioapic) | |
2803 | { | |
2804 | union IO_APIC_reg_01 reg_01; | |
2805 | unsigned long flags; | |
2806 | ||
2807 | spin_lock_irqsave(&ioapic_lock, flags); | |
2808 | reg_01.raw = io_apic_read(ioapic, 1); | |
2809 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2810 | ||
2811 | return reg_01.bits.entries; | |
2812 | } | |
2813 | ||
2814 | ||
2815 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) | |
2816 | { | |
2817 | struct IO_APIC_route_entry entry; | |
2818 | unsigned long flags; | |
2819 | ||
2820 | if (!IO_APIC_IRQ(irq)) { | |
2821 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2822 | ioapic); | |
2823 | return -EINVAL; | |
2824 | } | |
2825 | ||
2826 | /* | |
2827 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2828 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2829 | * corresponding device driver registers for this IRQ. | |
2830 | */ | |
2831 | ||
2832 | memset(&entry,0,sizeof(entry)); | |
2833 | ||
2834 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2835 | entry.dest_mode = INT_DEST_MODE; | |
2836 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2837 | entry.trigger = edge_level; | |
2838 | entry.polarity = active_high_low; | |
2839 | entry.mask = 1; | |
2840 | ||
2841 | /* | |
2842 | * IRQs < 16 are already in the irq_2_pin[] map | |
2843 | */ | |
2844 | if (irq >= 16) | |
2845 | add_pin_to_irq(irq, ioapic, pin); | |
2846 | ||
2847 | entry.vector = assign_irq_vector(irq); | |
2848 | ||
2849 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2850 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
2851 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
2852 | edge_level, active_high_low); | |
2853 | ||
2854 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2855 | ||
2856 | if (!ioapic && (irq < 16)) | |
2857 | disable_8259A_irq(irq); | |
2858 | ||
cf4c6a2f | 2859 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 | 2860 | spin_lock_irqsave(&ioapic_lock, flags); |
ace80ab7 | 2861 | set_native_irq_info(irq, TARGET_CPUS); |
1da177e4 LT |
2862 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2863 | ||
2864 | return 0; | |
2865 | } | |
2866 | ||
888ba6c6 | 2867 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2868 | |
2869 | static int __init parse_disable_timer_pin_1(char *arg) | |
2870 | { | |
2871 | disable_timer_pin_1 = 1; | |
2872 | return 0; | |
2873 | } | |
2874 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2875 | ||
2876 | static int __init parse_enable_timer_pin_1(char *arg) | |
2877 | { | |
2878 | disable_timer_pin_1 = -1; | |
2879 | return 0; | |
2880 | } | |
2881 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2882 | ||
2883 | static int __init parse_noapic(char *arg) | |
2884 | { | |
2885 | /* disable IO-APIC */ | |
2886 | disable_ioapic_setup(); | |
2887 | return 0; | |
2888 | } | |
2889 | early_param("noapic", parse_noapic); |