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[PATCH] kdump/i386: apic verification failure fix
[deliverable/linux.git] / arch / i386 / kernel / mpparse.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
1da177e4
LT		 17#include <linux/init.h>
18#include <linux/acpi.h>
19#include <linux/delay.h>
20#include <linux/config.h>
21#include <linux/bootmem.h>
22#include <linux/smp_lock.h>
23#include <linux/kernel_stat.h>
24#include <linux/mc146818rtc.h>
25#include <linux/bitops.h>
26
27#include <asm/smp.h>
28#include <asm/acpi.h>
29#include <asm/mtrr.h>
30#include <asm/mpspec.h>
31#include <asm/io_apic.h>
32
33#include <mach_apic.h>
34#include <mach_mpparse.h>
35#include <bios_ebda.h>
36
37/* Have we found an MP table */
38int smp_found_config;
39unsigned int __initdata maxcpus = NR_CPUS;
40
41/*
42 * Various Linux-internal data structures created from the
43 * MP-table.
44 */
45int apic_version [MAX_APICS];
46int mp_bus_id_to_type [MAX_MP_BUSSES];
47int mp_bus_id_to_node [MAX_MP_BUSSES];
48int mp_bus_id_to_local [MAX_MP_BUSSES];
49int quad_local_to_mp_bus_id [NR_CPUS/4][4];
50int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
51static int mp_current_pci_id;
52
53/* I/O APIC entries */
54struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55
56/* # of MP IRQ source entries */
57struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58
59/* MP IRQ source entries */
60int mp_irq_entries;
61
62int nr_ioapics;
63
64int pic_mode;
65unsigned long mp_lapic_addr;
66
911a62d4
VP		 67unsigned int def_to_bigsmp = 0;
68
1da177e4
LT		 69/* Processor that is doing the boot up */
70unsigned int boot_cpu_physical_apicid = -1U;
1da177e4 71/* Internal processor count */
9f40a72a 72static unsigned int __devinitdata num_processors;
1da177e4
LT		 73
74/* Bitmask of physically existing CPUs */
75physid_mask_t phys_cpu_present_map;
76
77u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
78
79/*
80 * Intel MP BIOS table parsing routines:
81 */
82
83
84/*
85 * Checksum an MP configuration block.
86 */
87
88static int __init mpf_checksum(unsigned char *mp, int len)
89{
90 int sum = 0;
91
92 while (len--)
93 sum += *mp++;
94
95 return sum & 0xFF;
96}
97
98/*
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
101 * doing this ....
102 */
103
104static int mpc_record;
105static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
106
107#ifdef CONFIG_X86_NUMAQ
108static int MP_valid_apicid(int apicid, int version)
109{
110 return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
111}
112#else
113static int MP_valid_apicid(int apicid, int version)
114{
115 if (version >= 0x14)
116 return apicid < 0xff;
117 else
118 return apicid < 0xf;
119}
120#endif
121
9f40a72a 122static void __devinit MP_processor_info (struct mpc_config_processor *m)
1da177e4 123{
1299232b
AM		 124 int ver, apicid;
125 physid_mask_t phys_cpu;
1da177e4
LT		 126
127 if (!(m->mpc_cpuflag & CPU_ENABLED))
128 return;
129
130 apicid = mpc_apic_id(m, translation_table[mpc_record]);
131
132 if (m->mpc_featureflag&(1<<0))
133 Dprintk(" Floating point unit present.\n");
134 if (m->mpc_featureflag&(1<<7))
135 Dprintk(" Machine Exception supported.\n");
136 if (m->mpc_featureflag&(1<<8))
137 Dprintk(" 64 bit compare & exchange supported.\n");
138 if (m->mpc_featureflag&(1<<9))
139 Dprintk(" Internal APIC present.\n");
140 if (m->mpc_featureflag&(1<<11))
141 Dprintk(" SEP present.\n");
142 if (m->mpc_featureflag&(1<<12))
143 Dprintk(" MTRR present.\n");
144 if (m->mpc_featureflag&(1<<13))
145 Dprintk(" PGE present.\n");
146 if (m->mpc_featureflag&(1<<14))
147 Dprintk(" MCA present.\n");
148 if (m->mpc_featureflag&(1<<15))
149 Dprintk(" CMOV present.\n");
150 if (m->mpc_featureflag&(1<<16))
151 Dprintk(" PAT present.\n");
152 if (m->mpc_featureflag&(1<<17))
153 Dprintk(" PSE present.\n");
154 if (m->mpc_featureflag&(1<<18))
155 Dprintk(" PSN present.\n");
156 if (m->mpc_featureflag&(1<<19))
157 Dprintk(" Cache Line Flush Instruction present.\n");
158 /* 20 Reserved */
159 if (m->mpc_featureflag&(1<<21))
160 Dprintk(" Debug Trace and EMON Store present.\n");
161 if (m->mpc_featureflag&(1<<22))
162 Dprintk(" ACPI Thermal Throttle Registers present.\n");
163 if (m->mpc_featureflag&(1<<23))
164 Dprintk(" MMX present.\n");
165 if (m->mpc_featureflag&(1<<24))
166 Dprintk(" FXSR present.\n");
167 if (m->mpc_featureflag&(1<<25))
168 Dprintk(" XMM present.\n");
169 if (m->mpc_featureflag&(1<<26))
170 Dprintk(" Willamette New Instructions present.\n");
171 if (m->mpc_featureflag&(1<<27))
172 Dprintk(" Self Snoop present.\n");
173 if (m->mpc_featureflag&(1<<28))
174 Dprintk(" HT present.\n");
175 if (m->mpc_featureflag&(1<<29))
176 Dprintk(" Thermal Monitor present.\n");
177 /* 30, 31 Reserved */
178
179
180 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
181 Dprintk(" Bootup CPU\n");
182 boot_cpu_physical_apicid = m->mpc_apicid;
1da177e4
LT		 183 }
184
185 if (num_processors >= NR_CPUS) {
186 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
187 " Processor ignored.\n", NR_CPUS);
188 return;
189 }
190
191 if (num_processors >= maxcpus) {
192 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
193 " Processor ignored.\n", maxcpus);
194 return;
195 }
1da177e4
LT		 196 ver = m->mpc_apicver;
197
198 if (!MP_valid_apicid(apicid, ver)) {
199 printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
200 m->mpc_apicid, MAX_APICS);
1da177e4
LT		 201 return;
202 }
203
1299232b
AM		 204 cpu_set(num_processors, cpu_possible_map);
205 num_processors++;
206 phys_cpu = apicid_to_cpu_present(apicid);
207 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
208
1da177e4
LT		 209 /*
210 * Validate version
211 */
212 if (ver == 0x0) {
1299232b
AM		 213 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
214 "fixing up to 0x10. (tell your hw vendor)\n",
215 m->mpc_apicid);
1da177e4
LT		 216 ver = 0x10;
217 }
218 apic_version[m->mpc_apicid] = ver;
911a62d4
VP		 219 if ((num_processors > 8) &&
220 APIC_XAPIC(ver) &&
221 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL))
222 def_to_bigsmp = 1;
223 else
224 def_to_bigsmp = 0;
225
1da177e4
LT		 226 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
227}
228
229static void __init MP_bus_info (struct mpc_config_bus *m)
230{
231 char str[7];
232
233 memcpy(str, m->mpc_bustype, 6);
234 str[6] = 0;
235
236 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
237
238 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
239 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
240 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
241 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
242 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
243 mpc_oem_pci_bus(m, translation_table[mpc_record]);
244 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
245 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
246 mp_current_pci_id++;
247 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
248 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
249 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
250 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
251 } else {
252 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
253 }
254}
255
256static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
257{
258 if (!(m->mpc_flags & MPC_APIC_USABLE))
259 return;
260
261 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
262 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
263 if (nr_ioapics >= MAX_IO_APICS) {
264 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
265 MAX_IO_APICS, nr_ioapics);
266 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
267 }
268 if (!m->mpc_apicaddr) {
269 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
270 " found in MP table, skipping!\n");
271 return;
272 }
273 mp_ioapics[nr_ioapics] = *m;
274 nr_ioapics++;
275}
276
277static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
278{
279 mp_irqs [mp_irq_entries] = *m;
280 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
281 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
282 m->mpc_irqtype, m->mpc_irqflag & 3,
283 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
284 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
285 if (++mp_irq_entries == MAX_IRQ_SOURCES)
286 panic("Max # of irq sources exceeded!!\n");
287}
288
289static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
290{
291 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
292 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
293 m->mpc_irqtype, m->mpc_irqflag & 3,
294 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
295 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
296 /*
297 * Well it seems all SMP boards in existence
298 * use ExtINT/LVT1 == LINT0 and
299 * NMI/LVT2 == LINT1 - the following check
300 * will show us if this assumptions is false.
301 * Until then we do not have to add baggage.
302 */
303 if ((m->mpc_irqtype == mp_ExtINT) &&
304 (m->mpc_destapiclint != 0))
305 BUG();
306 if ((m->mpc_irqtype == mp_NMI) &&
307 (m->mpc_destapiclint != 1))
308 BUG();
309}
310
311#ifdef CONFIG_X86_NUMAQ
312static void __init MP_translation_info (struct mpc_config_translation *m)
313{
314 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
315
316 if (mpc_record >= MAX_MPC_ENTRY)
317 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
318 else
319 translation_table[mpc_record] = m; /* stash this for later */
320 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
321 node_set_online(m->trans_quad);
322}
323
324/*
325 * Read/parse the MPC oem tables
326 */
327
328static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
329 unsigned short oemsize)
330{
331 int count = sizeof (*oemtable); /* the header size */
332 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
333
334 mpc_record = 0;
335 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
336 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
337 {
338 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
339 oemtable->oem_signature[0],
340 oemtable->oem_signature[1],
341 oemtable->oem_signature[2],
342 oemtable->oem_signature[3]);
343 return;
344 }
345 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
346 {
347 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
348 return;
349 }
350 while (count < oemtable->oem_length) {
351 switch (*oemptr) {
352 case MP_TRANSLATION:
353 {
354 struct mpc_config_translation *m=
355 (struct mpc_config_translation *)oemptr;
356 MP_translation_info(m);
357 oemptr += sizeof(*m);
358 count += sizeof(*m);
359 ++mpc_record;
360 break;
361 }
362 default:
363 {
364 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
365 return;
366 }
367 }
368 }
369}
370
371static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
372 char *productid)
373{
374 if (strncmp(oem, "IBM NUMA", 8))
375 printk("Warning! May not be a NUMA-Q system!\n");
376 if (mpc->mpc_oemptr)
377 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
378 mpc->mpc_oemsize);
379}
380#endif /* CONFIG_X86_NUMAQ */
381
382/*
383 * Read/parse the MPC
384 */
385
386static int __init smp_read_mpc(struct mp_config_table *mpc)
387{
388 char str[16];
389 char oem[10];
390 int count=sizeof(*mpc);
391 unsigned char *mpt=((unsigned char *)mpc)+count;
392
393 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
394 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
395 *(u32 *)mpc->mpc_signature);
396 return 0;
397 }
398 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
399 printk(KERN_ERR "SMP mptable: checksum error!\n");
400 return 0;
401 }
402 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
403 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
404 mpc->mpc_spec);
405 return 0;
406 }
407 if (!mpc->mpc_lapic) {
408 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
409 return 0;
410 }
411 memcpy(oem,mpc->mpc_oem,8);
412 oem[8]=0;
413 printk(KERN_INFO "OEM ID: %s ",oem);
414
415 memcpy(str,mpc->mpc_productid,12);
416 str[12]=0;
417 printk("Product ID: %s ",str);
418
419 mps_oem_check(mpc, oem, str);
420
421 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
422
423 /*
424 * Save the local APIC address (it might be non-default) -- but only
425 * if we're not using ACPI.
426 */
427 if (!acpi_lapic)
428 mp_lapic_addr = mpc->mpc_lapic;
429
430 /*
431 * Now process the configuration blocks.
432 */
433 mpc_record = 0;
434 while (count < mpc->mpc_length) {
435 switch(*mpt) {
436 case MP_PROCESSOR:
437 {
438 struct mpc_config_processor *m=
439 (struct mpc_config_processor *)mpt;
440 /* ACPI may have already provided this data */
441 if (!acpi_lapic)
442 MP_processor_info(m);
443 mpt += sizeof(*m);
444 count += sizeof(*m);
445 break;
446 }
447 case MP_BUS:
448 {
449 struct mpc_config_bus *m=
450 (struct mpc_config_bus *)mpt;
451 MP_bus_info(m);
452 mpt += sizeof(*m);
453 count += sizeof(*m);
454 break;
455 }
456 case MP_IOAPIC:
457 {
458 struct mpc_config_ioapic *m=
459 (struct mpc_config_ioapic *)mpt;
460 MP_ioapic_info(m);
461 mpt+=sizeof(*m);
462 count+=sizeof(*m);
463 break;
464 }
465 case MP_INTSRC:
466 {
467 struct mpc_config_intsrc *m=
468 (struct mpc_config_intsrc *)mpt;
469
470 MP_intsrc_info(m);
471 mpt+=sizeof(*m);
472 count+=sizeof(*m);
473 break;
474 }
475 case MP_LINTSRC:
476 {
477 struct mpc_config_lintsrc *m=
478 (struct mpc_config_lintsrc *)mpt;
479 MP_lintsrc_info(m);
480 mpt+=sizeof(*m);
481 count+=sizeof(*m);
482 break;
483 }
484 default:
485 {
486 count = mpc->mpc_length;
487 break;
488 }
489 }
490 ++mpc_record;
491 }
492 clustered_apic_check();
493 if (!num_processors)
494 printk(KERN_ERR "SMP mptable: no processors registered!\n");
495 return num_processors;
496}
497
498static int __init ELCR_trigger(unsigned int irq)
499{
500 unsigned int port;
501
502 port = 0x4d0 + (irq >> 3);
503 return (inb(port) >> (irq & 7)) & 1;
504}
505
506static void __init construct_default_ioirq_mptable(int mpc_default_type)
507{
508 struct mpc_config_intsrc intsrc;
509 int i;
510 int ELCR_fallback = 0;
511
512 intsrc.mpc_type = MP_INTSRC;
513 intsrc.mpc_irqflag = 0; /* conforming */
514 intsrc.mpc_srcbus = 0;
515 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
516
517 intsrc.mpc_irqtype = mp_INT;
518
519 /*
520 * If true, we have an ISA/PCI system with no IRQ entries
521 * in the MP table. To prevent the PCI interrupts from being set up
522 * incorrectly, we try to use the ELCR. The sanity check to see if
523 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
524 * never be level sensitive, so we simply see if the ELCR agrees.
525 * If it does, we assume it's valid.
526 */
527 if (mpc_default_type == 5) {
528 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
529
530 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
531 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
532 else {
533 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
534 ELCR_fallback = 1;
535 }
536 }
537
538 for (i = 0; i < 16; i++) {
539 switch (mpc_default_type) {
540 case 2:
541 if (i == 0 || i == 13)
542 continue; /* IRQ0 & IRQ13 not connected */
543 /* fall through */
544 default:
545 if (i == 2)
546 continue; /* IRQ2 is never connected */
547 }
548
549 if (ELCR_fallback) {
550 /*
551 * If the ELCR indicates a level-sensitive interrupt, we
552 * copy that information over to the MP table in the
553 * irqflag field (level sensitive, active high polarity).
554 */
555 if (ELCR_trigger(i))
556 intsrc.mpc_irqflag = 13;
557 else
558 intsrc.mpc_irqflag = 0;
559 }
560
561 intsrc.mpc_srcbusirq = i;
562 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
563 MP_intsrc_info(&intsrc);
564 }
565
566 intsrc.mpc_irqtype = mp_ExtINT;
567 intsrc.mpc_srcbusirq = 0;
568 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
569 MP_intsrc_info(&intsrc);
570}
571
572static inline void __init construct_default_ISA_mptable(int mpc_default_type)
573{
574 struct mpc_config_processor processor;
575 struct mpc_config_bus bus;
576 struct mpc_config_ioapic ioapic;
577 struct mpc_config_lintsrc lintsrc;
578 int linttypes[2] = { mp_ExtINT, mp_NMI };
579 int i;
580
581 /*
582 * local APIC has default address
583 */
584 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
585
586 /*
587 * 2 CPUs, numbered 0 & 1.
588 */
589 processor.mpc_type = MP_PROCESSOR;
590 /* Either an integrated APIC or a discrete 82489DX. */
591 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
592 processor.mpc_cpuflag = CPU_ENABLED;
593 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
594 (boot_cpu_data.x86_model << 4) |
595 boot_cpu_data.x86_mask;
596 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
597 processor.mpc_reserved[0] = 0;
598 processor.mpc_reserved[1] = 0;
599 for (i = 0; i < 2; i++) {
600 processor.mpc_apicid = i;
601 MP_processor_info(&processor);
602 }
603
604 bus.mpc_type = MP_BUS;
605 bus.mpc_busid = 0;
606 switch (mpc_default_type) {
607 default:
608 printk("???\n");
609 printk(KERN_ERR "Unknown standard configuration %d\n",
610 mpc_default_type);
611 /* fall through */
612 case 1:
613 case 5:
614 memcpy(bus.mpc_bustype, "ISA ", 6);
615 break;
616 case 2:
617 case 6:
618 case 3:
619 memcpy(bus.mpc_bustype, "EISA ", 6);
620 break;
621 case 4:
622 case 7:
623 memcpy(bus.mpc_bustype, "MCA ", 6);
624 }
625 MP_bus_info(&bus);
626 if (mpc_default_type > 4) {
627 bus.mpc_busid = 1;
628 memcpy(bus.mpc_bustype, "PCI ", 6);
629 MP_bus_info(&bus);
630 }
631
632 ioapic.mpc_type = MP_IOAPIC;
633 ioapic.mpc_apicid = 2;
634 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
635 ioapic.mpc_flags = MPC_APIC_USABLE;
636 ioapic.mpc_apicaddr = 0xFEC00000;
637 MP_ioapic_info(&ioapic);
638
639 /*
640 * We set up most of the low 16 IO-APIC pins according to MPS rules.
641 */
642 construct_default_ioirq_mptable(mpc_default_type);
643
644 lintsrc.mpc_type = MP_LINTSRC;
645 lintsrc.mpc_irqflag = 0; /* conforming */
646 lintsrc.mpc_srcbusid = 0;
647 lintsrc.mpc_srcbusirq = 0;
648 lintsrc.mpc_destapic = MP_APIC_ALL;
649 for (i = 0; i < 2; i++) {
650 lintsrc.mpc_irqtype = linttypes[i];
651 lintsrc.mpc_destapiclint = i;
652 MP_lintsrc_info(&lintsrc);
653 }
654}
655
656static struct intel_mp_floating *mpf_found;
657
658/*
659 * Scan the memory blocks for an SMP configuration block.
660 */
661void __init get_smp_config (void)
662{
663 struct intel_mp_floating *mpf = mpf_found;
664
665 /*
1da177e4
LT		 666 * ACPI supports both logical (e.g. Hyper-Threading) and physical
667 * processors, where MPS only supports physical.
668 */
669 if (acpi_lapic && acpi_ioapic) {
670 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
671 return;
672 }
673 else if (acpi_lapic)
674 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
675
676 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
677 if (mpf->mpf_feature2 & (1<<7)) {
678 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
679 pic_mode = 1;
680 } else {
681 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
682 pic_mode = 0;
683 }
684
685 /*
686 * Now see if we need to read further.
687 */
688 if (mpf->mpf_feature1 != 0) {
689
690 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
691 construct_default_ISA_mptable(mpf->mpf_feature1);
692
693 } else if (mpf->mpf_physptr) {
694
695 /*
696 * Read the physical hardware table. Anything here will
697 * override the defaults.
698 */
699 if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
700 smp_found_config = 0;
701 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
702 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
703 return;
704 }
705 /*
706 * If there are no explicit MP IRQ entries, then we are
707 * broken. We set up most of the low 16 IO-APIC pins to
708 * ISA defaults and hope it will work.
709 */
710 if (!mp_irq_entries) {
711 struct mpc_config_bus bus;
712
713 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
714
715 bus.mpc_type = MP_BUS;
716 bus.mpc_busid = 0;
717 memcpy(bus.mpc_bustype, "ISA ", 6);
718 MP_bus_info(&bus);
719
720 construct_default_ioirq_mptable(0);
721 }
722
723 } else
724 BUG();
725
726 printk(KERN_INFO "Processors: %d\n", num_processors);
727 /*
728 * Only use the first configuration found.
729 */
730}
731
732static int __init smp_scan_config (unsigned long base, unsigned long length)
733{
734 unsigned long *bp = phys_to_virt(base);
735 struct intel_mp_floating *mpf;
736
737 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
738 if (sizeof(*mpf) != 16)
739 printk("Error: MPF size\n");
740
741 while (length > 0) {
742 mpf = (struct intel_mp_floating *)bp;
743 if ((*bp == SMP_MAGIC_IDENT) &&
744 (mpf->mpf_length == 1) &&
745 !mpf_checksum((unsigned char *)bp, 16) &&
746 ((mpf->mpf_specification == 1)
747 || (mpf->mpf_specification == 4)) ) {
748
749 smp_found_config = 1;
750 printk(KERN_INFO "found SMP MP-table at %08lx\n",
751 virt_to_phys(mpf));
752 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
753 if (mpf->mpf_physptr) {
754 /*
755 * We cannot access to MPC table to compute
756 * table size yet, as only few megabytes from
757 * the bottom is mapped now.
758 * PC-9800's MPC table places on the very last
759 * of physical memory; so that simply reserving
760 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
761 * in reserve_bootmem.
762 */
763 unsigned long size = PAGE_SIZE;
764 unsigned long end = max_low_pfn * PAGE_SIZE;
765 if (mpf->mpf_physptr + size > end)
766 size = end - mpf->mpf_physptr;
767 reserve_bootmem(mpf->mpf_physptr, size);
768 }
769
770 mpf_found = mpf;
771 return 1;
772 }
773 bp += 4;
774 length -= 16;
775 }
776 return 0;
777}
778
779void __init find_smp_config (void)
780{
781 unsigned int address;
782
783 /*
784 * FIXME: Linux assumes you have 640K of base ram..
785 * this continues the error...
786 *
787 * 1) Scan the bottom 1K for a signature
788 * 2) Scan the top 1K of base RAM
789 * 3) Scan the 64K of bios
790 */
791 if (smp_scan_config(0x0,0x400) ||
792 smp_scan_config(639*0x400,0x400) ||
793 smp_scan_config(0xF0000,0x10000))
794 return;
795 /*
796 * If it is an SMP machine we should know now, unless the
797 * configuration is in an EISA/MCA bus machine with an
798 * extended bios data area.
799 *
800 * there is a real-mode segmented pointer pointing to the
801 * 4K EBDA area at 0x40E, calculate and scan it here.
802 *
803 * NOTE! There are Linux loaders that will corrupt the EBDA
804 * area, and as such this kind of SMP config may be less
805 * trustworthy, simply because the SMP table may have been
806 * stomped on during early boot. These loaders are buggy and
807 * should be fixed.
808 *
809 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
810 */
811
812 address = get_bios_ebda();
813 if (address)
814 smp_scan_config(address, 0x400);
815}
816
817/* --------------------------------------------------------------------------
818 ACPI-based MP Configuration
819 -------------------------------------------------------------------------- */
820
888ba6c6 821#ifdef CONFIG_ACPI
1da177e4
LT		 822
823void __init mp_register_lapic_address (
824 u64 address)
825{
826 mp_lapic_addr = (unsigned long) address;
827
828 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
829
830 if (boot_cpu_physical_apicid == -1U)
831 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
832
833 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
834}
835
836
9f40a72a 837void __devinit mp_register_lapic (
1da177e4
LT		 838 u8 id,
839 u8 enabled)
840{
841 struct mpc_config_processor processor;
842 int boot_cpu = 0;
843
844 if (MAX_APICS - id <= 0) {
845 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
846 id, MAX_APICS);
847 return;
848 }
849
850 if (id == boot_cpu_physical_apicid)
851 boot_cpu = 1;
852
853 processor.mpc_type = MP_PROCESSOR;
854 processor.mpc_apicid = id;
855 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
856 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
857 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
858 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
859 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
860 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
861 processor.mpc_reserved[0] = 0;
862 processor.mpc_reserved[1] = 0;
863
864 MP_processor_info(&processor);
865}
866
8466361a 867#ifdef CONFIG_X86_IO_APIC
1da177e4
LT		 868
869#define MP_ISA_BUS 0
870#define MP_MAX_IOAPIC_PIN 127
871
872static struct mp_ioapic_routing {
873 int apic_id;
874 int gsi_base;
875 int gsi_end;
876 u32 pin_programmed[4];
877} mp_ioapic_routing[MAX_IO_APICS];
878
879
880static int mp_find_ioapic (
881 int gsi)
882{
883 int i = 0;
884
885 /* Find the IOAPIC that manages this GSI. */
886 for (i = 0; i < nr_ioapics; i++) {
887 if ((gsi >= mp_ioapic_routing[i].gsi_base)
888 && (gsi <= mp_ioapic_routing[i].gsi_end))
889 return i;
890 }
891
892 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
893
894 return -1;
895}
896
897
898void __init mp_register_ioapic (
899 u8 id,
900 u32 address,
901 u32 gsi_base)
902{
903 int idx = 0;
904
905 if (nr_ioapics >= MAX_IO_APICS) {
906 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
907 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
908 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
909 }
910 if (!address) {
911 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
912 " found in MADT table, skipping!\n");
913 return;
914 }
915
916 idx = nr_ioapics++;
917
918 mp_ioapics[idx].mpc_type = MP_IOAPIC;
919 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
920 mp_ioapics[idx].mpc_apicaddr = address;
921
922 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
ca05fea6
NP		 923 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))
924 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
925 else
926 mp_ioapics[idx].mpc_apicid = id;
1da177e4
LT		 927 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
928
929 /*
930 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
931 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
932 */
933 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
934 mp_ioapic_routing[idx].gsi_base = gsi_base;
935 mp_ioapic_routing[idx].gsi_end = gsi_base +
936 io_apic_get_redir_entries(idx);
937
938 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
939 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
940 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
941 mp_ioapic_routing[idx].gsi_base,
942 mp_ioapic_routing[idx].gsi_end);
943
944 return;
945}
946
947
948void __init mp_override_legacy_irq (
949 u8 bus_irq,
950 u8 polarity,
951 u8 trigger,
952 u32 gsi)
953{
954 struct mpc_config_intsrc intsrc;
955 int ioapic = -1;
956 int pin = -1;
957
958 /*
959 * Convert 'gsi' to 'ioapic.pin'.
960 */
961 ioapic = mp_find_ioapic(gsi);
962 if (ioapic < 0)
963 return;
964 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
965
966 /*
967 * TBD: This check is for faulty timer entries, where the override
968 * erroneously sets the trigger to level, resulting in a HUGE
969 * increase of timer interrupts!
970 */
971 if ((bus_irq == 0) && (trigger == 3))
972 trigger = 1;
973
974 intsrc.mpc_type = MP_INTSRC;
975 intsrc.mpc_irqtype = mp_INT;
976 intsrc.mpc_irqflag = (trigger << 2) | polarity;
977 intsrc.mpc_srcbus = MP_ISA_BUS;
978 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
979 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
980 intsrc.mpc_dstirq = pin; /* INTIN# */
981
982 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
983 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
984 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
985 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
986
987 mp_irqs[mp_irq_entries] = intsrc;
988 if (++mp_irq_entries == MAX_IRQ_SOURCES)
989 panic("Max # of irq sources exceeded!\n");
990
991 return;
992}
993
994int es7000_plat;
995
996void __init mp_config_acpi_legacy_irqs (void)
997{
998 struct mpc_config_intsrc intsrc;
999 int i = 0;
1000 int ioapic = -1;
1001
1002 /*
1003 * Fabricate the legacy ISA bus (bus #31).
1004 */
1005 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1006 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1007
1008 /*
1009 * Older generations of ES7000 have no legacy identity mappings
1010 */
1011 if (es7000_plat == 1)
1012 return;
1013
1014 /*
1015 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1016 */
1017 ioapic = mp_find_ioapic(0);
1018 if (ioapic < 0)
1019 return;
1020
1021 intsrc.mpc_type = MP_INTSRC;
1022 intsrc.mpc_irqflag = 0; /* Conforming */
1023 intsrc.mpc_srcbus = MP_ISA_BUS;
1024 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1025
1026 /*
1027 * Use the default configuration for the IRQs 0-15. Unless
1028 * overriden by (MADT) interrupt source override entries.
1029 */
1030 for (i = 0; i < 16; i++) {
1031 int idx;
1032
1033 for (idx = 0; idx < mp_irq_entries; idx++) {
1034 struct mpc_config_intsrc *irq = mp_irqs + idx;
1035
1036 /* Do we already have a mapping for this ISA IRQ? */
1037 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1038 break;
1039
1040 /* Do we already have a mapping for this IOAPIC pin */
1041 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1042 (irq->mpc_dstirq == i))
1043 break;
1044 }
1045
1046 if (idx != mp_irq_entries) {
1047 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1048 continue; /* IRQ already used */
1049 }
1050
1051 intsrc.mpc_irqtype = mp_INT;
1052 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1053 intsrc.mpc_dstirq = i;
1054
1055 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1056 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1057 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1058 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1059 intsrc.mpc_dstirq);
1060
1061 mp_irqs[mp_irq_entries] = intsrc;
1062 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1063 panic("Max # of irq sources exceeded!\n");
1064 }
1065}
1066
c434b7a6
NP		 1067#define MAX_GSI_NUM 4096
1068
1da177e4
LT		 1069int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
1070{
1071 int ioapic = -1;
1072 int ioapic_pin = 0;
1073 int idx, bit = 0;
c434b7a6
NP		 1074 static int pci_irq = 16;
1075 /*
1076 * Mapping between Global System Interrups, which
1077 * represent all possible interrupts, and IRQs
1078 * assigned to actual devices.
1079 */
1080 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4 1081
1da177e4
LT		 1082 /* Don't set up the ACPI SCI because it's already set up */
1083 if (acpi_fadt.sci_int == gsi)
1084 return gsi;
1da177e4
LT		 1085
1086 ioapic = mp_find_ioapic(gsi);
1087 if (ioapic < 0) {
1088 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1089 return gsi;
1090 }
1091
1092 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1093
1094 if (ioapic_renumber_irq)
1095 gsi = ioapic_renumber_irq(ioapic, gsi);
1096
1097 /*
1098 * Avoid pin reprogramming. PRTs typically include entries
1099 * with redundant pin->gsi mappings (but unique PCI devices);
1100 * we only program the IOAPIC on the first.
1101 */
1102 bit = ioapic_pin % 32;
1103 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1104 if (idx > 3) {
1105 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1106 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1107 ioapic_pin);
1108 return gsi;
1109 }
1110 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1111 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1112 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
c434b7a6 1113 return gsi_to_irq[gsi];
1da177e4
LT		 1114 }
1115
1116 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1117
c434b7a6
NP		 1118 if (edge_level) {
1119 /*
1120 * For PCI devices assign IRQs in order, avoiding gaps
1121 * due to unused I/O APIC pins.
1122 */
1123 int irq = gsi;
1124 if (gsi < MAX_GSI_NUM) {
e1afc3f5
NP		 1125 if (gsi > 15)
1126 gsi = pci_irq++;
e1afc3f5
NP		 1127 /*
1128 * Don't assign IRQ used by ACPI SCI
1129 */
1130 if (gsi == acpi_fadt.sci_int)
1131 gsi = pci_irq++;
c434b7a6
NP		 1132 gsi_to_irq[irq] = gsi;
1133 } else {
1134 printk(KERN_ERR "GSI %u is too high\n", gsi);
1135 return gsi;
1136 }
1137 }
1138
1da177e4
LT		 1139 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1140 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
1141 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
1142 return gsi;
1143}
1144
8466361a 1145#endif /* CONFIG_X86_IO_APIC */
888ba6c6 1146#endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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