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[ACPI] delete CONFIG_ACPI_BOOT
[deliverable/linux.git] / arch / i386 / kernel / mpparse.c
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1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
17#include <linux/irq.h>
18#include <linux/init.h>
19#include <linux/acpi.h>
20#include <linux/delay.h>
21#include <linux/config.h>
22#include <linux/bootmem.h>
23#include <linux/smp_lock.h>
24#include <linux/kernel_stat.h>
25#include <linux/mc146818rtc.h>
26#include <linux/bitops.h>
27
28#include <asm/smp.h>
29#include <asm/acpi.h>
30#include <asm/mtrr.h>
31#include <asm/mpspec.h>
32#include <asm/io_apic.h>
33
34#include <mach_apic.h>
35#include <mach_mpparse.h>
36#include <bios_ebda.h>
37
38/* Have we found an MP table */
39int smp_found_config;
40unsigned int __initdata maxcpus = NR_CPUS;
41
42/*
43 * Various Linux-internal data structures created from the
44 * MP-table.
45 */
46int apic_version [MAX_APICS];
47int mp_bus_id_to_type [MAX_MP_BUSSES];
48int mp_bus_id_to_node [MAX_MP_BUSSES];
49int mp_bus_id_to_local [MAX_MP_BUSSES];
50int quad_local_to_mp_bus_id [NR_CPUS/4][4];
51int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
52static int mp_current_pci_id;
53
54/* I/O APIC entries */
55struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
56
57/* # of MP IRQ source entries */
58struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
59
60/* MP IRQ source entries */
61int mp_irq_entries;
62
63int nr_ioapics;
64
65int pic_mode;
66unsigned long mp_lapic_addr;
67
68/* Processor that is doing the boot up */
69unsigned int boot_cpu_physical_apicid = -1U;
1da177e4
LT		 70/* Internal processor count */
71static unsigned int __initdata num_processors;
72
73/* Bitmask of physically existing CPUs */
74physid_mask_t phys_cpu_present_map;
75
76u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
77
78/*
79 * Intel MP BIOS table parsing routines:
80 */
81
82
83/*
84 * Checksum an MP configuration block.
85 */
86
87static int __init mpf_checksum(unsigned char *mp, int len)
88{
89 int sum = 0;
90
91 while (len--)
92 sum += *mp++;
93
94 return sum & 0xFF;
95}
96
97/*
98 * Have to match translation table entries to main table entries by counter
99 * hence the mpc_record variable .... can't see a less disgusting way of
100 * doing this ....
101 */
102
103static int mpc_record;
104static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
105
106#ifdef CONFIG_X86_NUMAQ
107static int MP_valid_apicid(int apicid, int version)
108{
109 return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
110}
111#else
112static int MP_valid_apicid(int apicid, int version)
113{
114 if (version >= 0x14)
115 return apicid < 0xff;
116 else
117 return apicid < 0xf;
118}
119#endif
120
121static void __init MP_processor_info (struct mpc_config_processor *m)
122{
123 int ver, apicid;
124 physid_mask_t tmp;
125
126 if (!(m->mpc_cpuflag & CPU_ENABLED))
127 return;
128
129 apicid = mpc_apic_id(m, translation_table[mpc_record]);
130
131 if (m->mpc_featureflag&(1<<0))
132 Dprintk(" Floating point unit present.\n");
133 if (m->mpc_featureflag&(1<<7))
134 Dprintk(" Machine Exception supported.\n");
135 if (m->mpc_featureflag&(1<<8))
136 Dprintk(" 64 bit compare & exchange supported.\n");
137 if (m->mpc_featureflag&(1<<9))
138 Dprintk(" Internal APIC present.\n");
139 if (m->mpc_featureflag&(1<<11))
140 Dprintk(" SEP present.\n");
141 if (m->mpc_featureflag&(1<<12))
142 Dprintk(" MTRR present.\n");
143 if (m->mpc_featureflag&(1<<13))
144 Dprintk(" PGE present.\n");
145 if (m->mpc_featureflag&(1<<14))
146 Dprintk(" MCA present.\n");
147 if (m->mpc_featureflag&(1<<15))
148 Dprintk(" CMOV present.\n");
149 if (m->mpc_featureflag&(1<<16))
150 Dprintk(" PAT present.\n");
151 if (m->mpc_featureflag&(1<<17))
152 Dprintk(" PSE present.\n");
153 if (m->mpc_featureflag&(1<<18))
154 Dprintk(" PSN present.\n");
155 if (m->mpc_featureflag&(1<<19))
156 Dprintk(" Cache Line Flush Instruction present.\n");
157 /* 20 Reserved */
158 if (m->mpc_featureflag&(1<<21))
159 Dprintk(" Debug Trace and EMON Store present.\n");
160 if (m->mpc_featureflag&(1<<22))
161 Dprintk(" ACPI Thermal Throttle Registers present.\n");
162 if (m->mpc_featureflag&(1<<23))
163 Dprintk(" MMX present.\n");
164 if (m->mpc_featureflag&(1<<24))
165 Dprintk(" FXSR present.\n");
166 if (m->mpc_featureflag&(1<<25))
167 Dprintk(" XMM present.\n");
168 if (m->mpc_featureflag&(1<<26))
169 Dprintk(" Willamette New Instructions present.\n");
170 if (m->mpc_featureflag&(1<<27))
171 Dprintk(" Self Snoop present.\n");
172 if (m->mpc_featureflag&(1<<28))
173 Dprintk(" HT present.\n");
174 if (m->mpc_featureflag&(1<<29))
175 Dprintk(" Thermal Monitor present.\n");
176 /* 30, 31 Reserved */
177
178
179 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
180 Dprintk(" Bootup CPU\n");
181 boot_cpu_physical_apicid = m->mpc_apicid;
1da177e4
LT		 182 }
183
184 if (num_processors >= NR_CPUS) {
185 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
186 " Processor ignored.\n", NR_CPUS);
187 return;
188 }
189
190 if (num_processors >= maxcpus) {
191 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
192 " Processor ignored.\n", maxcpus);
193 return;
194 }
195 num_processors++;
196 ver = m->mpc_apicver;
197
198 if (!MP_valid_apicid(apicid, ver)) {
199 printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
200 m->mpc_apicid, MAX_APICS);
201 --num_processors;
202 return;
203 }
204
205 tmp = apicid_to_cpu_present(apicid);
206 physids_or(phys_cpu_present_map, phys_cpu_present_map, tmp);
207
208 /*
209 * Validate version
210 */
211 if (ver == 0x0) {
212 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
213 ver = 0x10;
214 }
215 apic_version[m->mpc_apicid] = ver;
216 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
217}
218
219static void __init MP_bus_info (struct mpc_config_bus *m)
220{
221 char str[7];
222
223 memcpy(str, m->mpc_bustype, 6);
224 str[6] = 0;
225
226 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
227
228 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
229 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
230 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
231 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
232 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
233 mpc_oem_pci_bus(m, translation_table[mpc_record]);
234 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
235 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
236 mp_current_pci_id++;
237 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
238 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
239 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
240 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
241 } else {
242 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
243 }
244}
245
246static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
247{
248 if (!(m->mpc_flags & MPC_APIC_USABLE))
249 return;
250
251 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
252 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
253 if (nr_ioapics >= MAX_IO_APICS) {
254 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
255 MAX_IO_APICS, nr_ioapics);
256 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
257 }
258 if (!m->mpc_apicaddr) {
259 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
260 " found in MP table, skipping!\n");
261 return;
262 }
263 mp_ioapics[nr_ioapics] = *m;
264 nr_ioapics++;
265}
266
267static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
268{
269 mp_irqs [mp_irq_entries] = *m;
270 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
271 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
272 m->mpc_irqtype, m->mpc_irqflag & 3,
273 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
274 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
275 if (++mp_irq_entries == MAX_IRQ_SOURCES)
276 panic("Max # of irq sources exceeded!!\n");
277}
278
279static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
280{
281 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
282 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
283 m->mpc_irqtype, m->mpc_irqflag & 3,
284 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
285 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
286 /*
287 * Well it seems all SMP boards in existence
288 * use ExtINT/LVT1 == LINT0 and
289 * NMI/LVT2 == LINT1 - the following check
290 * will show us if this assumptions is false.
291 * Until then we do not have to add baggage.
292 */
293 if ((m->mpc_irqtype == mp_ExtINT) &&
294 (m->mpc_destapiclint != 0))
295 BUG();
296 if ((m->mpc_irqtype == mp_NMI) &&
297 (m->mpc_destapiclint != 1))
298 BUG();
299}
300
301#ifdef CONFIG_X86_NUMAQ
302static void __init MP_translation_info (struct mpc_config_translation *m)
303{
304 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
305
306 if (mpc_record >= MAX_MPC_ENTRY)
307 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
308 else
309 translation_table[mpc_record] = m; /* stash this for later */
310 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
311 node_set_online(m->trans_quad);
312}
313
314/*
315 * Read/parse the MPC oem tables
316 */
317
318static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
319 unsigned short oemsize)
320{
321 int count = sizeof (*oemtable); /* the header size */
322 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
323
324 mpc_record = 0;
325 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
326 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
327 {
328 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
329 oemtable->oem_signature[0],
330 oemtable->oem_signature[1],
331 oemtable->oem_signature[2],
332 oemtable->oem_signature[3]);
333 return;
334 }
335 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
336 {
337 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
338 return;
339 }
340 while (count < oemtable->oem_length) {
341 switch (*oemptr) {
342 case MP_TRANSLATION:
343 {
344 struct mpc_config_translation *m=
345 (struct mpc_config_translation *)oemptr;
346 MP_translation_info(m);
347 oemptr += sizeof(*m);
348 count += sizeof(*m);
349 ++mpc_record;
350 break;
351 }
352 default:
353 {
354 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
355 return;
356 }
357 }
358 }
359}
360
361static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
362 char *productid)
363{
364 if (strncmp(oem, "IBM NUMA", 8))
365 printk("Warning! May not be a NUMA-Q system!\n");
366 if (mpc->mpc_oemptr)
367 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
368 mpc->mpc_oemsize);
369}
370#endif /* CONFIG_X86_NUMAQ */
371
372/*
373 * Read/parse the MPC
374 */
375
376static int __init smp_read_mpc(struct mp_config_table *mpc)
377{
378 char str[16];
379 char oem[10];
380 int count=sizeof(*mpc);
381 unsigned char *mpt=((unsigned char *)mpc)+count;
382
383 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
384 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
385 *(u32 *)mpc->mpc_signature);
386 return 0;
387 }
388 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
389 printk(KERN_ERR "SMP mptable: checksum error!\n");
390 return 0;
391 }
392 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
393 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
394 mpc->mpc_spec);
395 return 0;
396 }
397 if (!mpc->mpc_lapic) {
398 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
399 return 0;
400 }
401 memcpy(oem,mpc->mpc_oem,8);
402 oem[8]=0;
403 printk(KERN_INFO "OEM ID: %s ",oem);
404
405 memcpy(str,mpc->mpc_productid,12);
406 str[12]=0;
407 printk("Product ID: %s ",str);
408
409 mps_oem_check(mpc, oem, str);
410
411 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
412
413 /*
414 * Save the local APIC address (it might be non-default) -- but only
415 * if we're not using ACPI.
416 */
417 if (!acpi_lapic)
418 mp_lapic_addr = mpc->mpc_lapic;
419
420 /*
421 * Now process the configuration blocks.
422 */
423 mpc_record = 0;
424 while (count < mpc->mpc_length) {
425 switch(*mpt) {
426 case MP_PROCESSOR:
427 {
428 struct mpc_config_processor *m=
429 (struct mpc_config_processor *)mpt;
430 /* ACPI may have already provided this data */
431 if (!acpi_lapic)
432 MP_processor_info(m);
433 mpt += sizeof(*m);
434 count += sizeof(*m);
435 break;
436 }
437 case MP_BUS:
438 {
439 struct mpc_config_bus *m=
440 (struct mpc_config_bus *)mpt;
441 MP_bus_info(m);
442 mpt += sizeof(*m);
443 count += sizeof(*m);
444 break;
445 }
446 case MP_IOAPIC:
447 {
448 struct mpc_config_ioapic *m=
449 (struct mpc_config_ioapic *)mpt;
450 MP_ioapic_info(m);
451 mpt+=sizeof(*m);
452 count+=sizeof(*m);
453 break;
454 }
455 case MP_INTSRC:
456 {
457 struct mpc_config_intsrc *m=
458 (struct mpc_config_intsrc *)mpt;
459
460 MP_intsrc_info(m);
461 mpt+=sizeof(*m);
462 count+=sizeof(*m);
463 break;
464 }
465 case MP_LINTSRC:
466 {
467 struct mpc_config_lintsrc *m=
468 (struct mpc_config_lintsrc *)mpt;
469 MP_lintsrc_info(m);
470 mpt+=sizeof(*m);
471 count+=sizeof(*m);
472 break;
473 }
474 default:
475 {
476 count = mpc->mpc_length;
477 break;
478 }
479 }
480 ++mpc_record;
481 }
482 clustered_apic_check();
483 if (!num_processors)
484 printk(KERN_ERR "SMP mptable: no processors registered!\n");
485 return num_processors;
486}
487
488static int __init ELCR_trigger(unsigned int irq)
489{
490 unsigned int port;
491
492 port = 0x4d0 + (irq >> 3);
493 return (inb(port) >> (irq & 7)) & 1;
494}
495
496static void __init construct_default_ioirq_mptable(int mpc_default_type)
497{
498 struct mpc_config_intsrc intsrc;
499 int i;
500 int ELCR_fallback = 0;
501
502 intsrc.mpc_type = MP_INTSRC;
503 intsrc.mpc_irqflag = 0; /* conforming */
504 intsrc.mpc_srcbus = 0;
505 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
506
507 intsrc.mpc_irqtype = mp_INT;
508
509 /*
510 * If true, we have an ISA/PCI system with no IRQ entries
511 * in the MP table. To prevent the PCI interrupts from being set up
512 * incorrectly, we try to use the ELCR. The sanity check to see if
513 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
514 * never be level sensitive, so we simply see if the ELCR agrees.
515 * If it does, we assume it's valid.
516 */
517 if (mpc_default_type == 5) {
518 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
519
520 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
521 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
522 else {
523 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
524 ELCR_fallback = 1;
525 }
526 }
527
528 for (i = 0; i < 16; i++) {
529 switch (mpc_default_type) {
530 case 2:
531 if (i == 0 || i == 13)
532 continue; /* IRQ0 & IRQ13 not connected */
533 /* fall through */
534 default:
535 if (i == 2)
536 continue; /* IRQ2 is never connected */
537 }
538
539 if (ELCR_fallback) {
540 /*
541 * If the ELCR indicates a level-sensitive interrupt, we
542 * copy that information over to the MP table in the
543 * irqflag field (level sensitive, active high polarity).
544 */
545 if (ELCR_trigger(i))
546 intsrc.mpc_irqflag = 13;
547 else
548 intsrc.mpc_irqflag = 0;
549 }
550
551 intsrc.mpc_srcbusirq = i;
552 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
553 MP_intsrc_info(&intsrc);
554 }
555
556 intsrc.mpc_irqtype = mp_ExtINT;
557 intsrc.mpc_srcbusirq = 0;
558 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
559 MP_intsrc_info(&intsrc);
560}
561
562static inline void __init construct_default_ISA_mptable(int mpc_default_type)
563{
564 struct mpc_config_processor processor;
565 struct mpc_config_bus bus;
566 struct mpc_config_ioapic ioapic;
567 struct mpc_config_lintsrc lintsrc;
568 int linttypes[2] = { mp_ExtINT, mp_NMI };
569 int i;
570
571 /*
572 * local APIC has default address
573 */
574 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
575
576 /*
577 * 2 CPUs, numbered 0 & 1.
578 */
579 processor.mpc_type = MP_PROCESSOR;
580 /* Either an integrated APIC or a discrete 82489DX. */
581 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
582 processor.mpc_cpuflag = CPU_ENABLED;
583 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
584 (boot_cpu_data.x86_model << 4) |
585 boot_cpu_data.x86_mask;
586 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
587 processor.mpc_reserved[0] = 0;
588 processor.mpc_reserved[1] = 0;
589 for (i = 0; i < 2; i++) {
590 processor.mpc_apicid = i;
591 MP_processor_info(&processor);
592 }
593
594 bus.mpc_type = MP_BUS;
595 bus.mpc_busid = 0;
596 switch (mpc_default_type) {
597 default:
598 printk("???\n");
599 printk(KERN_ERR "Unknown standard configuration %d\n",
600 mpc_default_type);
601 /* fall through */
602 case 1:
603 case 5:
604 memcpy(bus.mpc_bustype, "ISA ", 6);
605 break;
606 case 2:
607 case 6:
608 case 3:
609 memcpy(bus.mpc_bustype, "EISA ", 6);
610 break;
611 case 4:
612 case 7:
613 memcpy(bus.mpc_bustype, "MCA ", 6);
614 }
615 MP_bus_info(&bus);
616 if (mpc_default_type > 4) {
617 bus.mpc_busid = 1;
618 memcpy(bus.mpc_bustype, "PCI ", 6);
619 MP_bus_info(&bus);
620 }
621
622 ioapic.mpc_type = MP_IOAPIC;
623 ioapic.mpc_apicid = 2;
624 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
625 ioapic.mpc_flags = MPC_APIC_USABLE;
626 ioapic.mpc_apicaddr = 0xFEC00000;
627 MP_ioapic_info(&ioapic);
628
629 /*
630 * We set up most of the low 16 IO-APIC pins according to MPS rules.
631 */
632 construct_default_ioirq_mptable(mpc_default_type);
633
634 lintsrc.mpc_type = MP_LINTSRC;
635 lintsrc.mpc_irqflag = 0; /* conforming */
636 lintsrc.mpc_srcbusid = 0;
637 lintsrc.mpc_srcbusirq = 0;
638 lintsrc.mpc_destapic = MP_APIC_ALL;
639 for (i = 0; i < 2; i++) {
640 lintsrc.mpc_irqtype = linttypes[i];
641 lintsrc.mpc_destapiclint = i;
642 MP_lintsrc_info(&lintsrc);
643 }
644}
645
646static struct intel_mp_floating *mpf_found;
647
648/*
649 * Scan the memory blocks for an SMP configuration block.
650 */
651void __init get_smp_config (void)
652{
653 struct intel_mp_floating *mpf = mpf_found;
654
655 /*
1da177e4
LT		 656 * ACPI supports both logical (e.g. Hyper-Threading) and physical
657 * processors, where MPS only supports physical.
658 */
659 if (acpi_lapic && acpi_ioapic) {
660 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
661 return;
662 }
663 else if (acpi_lapic)
664 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
665
666 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
667 if (mpf->mpf_feature2 & (1<<7)) {
668 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
669 pic_mode = 1;
670 } else {
671 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
672 pic_mode = 0;
673 }
674
675 /*
676 * Now see if we need to read further.
677 */
678 if (mpf->mpf_feature1 != 0) {
679
680 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
681 construct_default_ISA_mptable(mpf->mpf_feature1);
682
683 } else if (mpf->mpf_physptr) {
684
685 /*
686 * Read the physical hardware table. Anything here will
687 * override the defaults.
688 */
689 if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
690 smp_found_config = 0;
691 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
692 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
693 return;
694 }
695 /*
696 * If there are no explicit MP IRQ entries, then we are
697 * broken. We set up most of the low 16 IO-APIC pins to
698 * ISA defaults and hope it will work.
699 */
700 if (!mp_irq_entries) {
701 struct mpc_config_bus bus;
702
703 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
704
705 bus.mpc_type = MP_BUS;
706 bus.mpc_busid = 0;
707 memcpy(bus.mpc_bustype, "ISA ", 6);
708 MP_bus_info(&bus);
709
710 construct_default_ioirq_mptable(0);
711 }
712
713 } else
714 BUG();
715
716 printk(KERN_INFO "Processors: %d\n", num_processors);
717 /*
718 * Only use the first configuration found.
719 */
720}
721
722static int __init smp_scan_config (unsigned long base, unsigned long length)
723{
724 unsigned long *bp = phys_to_virt(base);
725 struct intel_mp_floating *mpf;
726
727 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
728 if (sizeof(*mpf) != 16)
729 printk("Error: MPF size\n");
730
731 while (length > 0) {
732 mpf = (struct intel_mp_floating *)bp;
733 if ((*bp == SMP_MAGIC_IDENT) &&
734 (mpf->mpf_length == 1) &&
735 !mpf_checksum((unsigned char *)bp, 16) &&
736 ((mpf->mpf_specification == 1)
737 || (mpf->mpf_specification == 4)) ) {
738
739 smp_found_config = 1;
740 printk(KERN_INFO "found SMP MP-table at %08lx\n",
741 virt_to_phys(mpf));
742 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
743 if (mpf->mpf_physptr) {
744 /*
745 * We cannot access to MPC table to compute
746 * table size yet, as only few megabytes from
747 * the bottom is mapped now.
748 * PC-9800's MPC table places on the very last
749 * of physical memory; so that simply reserving
750 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
751 * in reserve_bootmem.
752 */
753 unsigned long size = PAGE_SIZE;
754 unsigned long end = max_low_pfn * PAGE_SIZE;
755 if (mpf->mpf_physptr + size > end)
756 size = end - mpf->mpf_physptr;
757 reserve_bootmem(mpf->mpf_physptr, size);
758 }
759
760 mpf_found = mpf;
761 return 1;
762 }
763 bp += 4;
764 length -= 16;
765 }
766 return 0;
767}
768
769void __init find_smp_config (void)
770{
771 unsigned int address;
772
773 /*
774 * FIXME: Linux assumes you have 640K of base ram..
775 * this continues the error...
776 *
777 * 1) Scan the bottom 1K for a signature
778 * 2) Scan the top 1K of base RAM
779 * 3) Scan the 64K of bios
780 */
781 if (smp_scan_config(0x0,0x400) ||
782 smp_scan_config(639*0x400,0x400) ||
783 smp_scan_config(0xF0000,0x10000))
784 return;
785 /*
786 * If it is an SMP machine we should know now, unless the
787 * configuration is in an EISA/MCA bus machine with an
788 * extended bios data area.
789 *
790 * there is a real-mode segmented pointer pointing to the
791 * 4K EBDA area at 0x40E, calculate and scan it here.
792 *
793 * NOTE! There are Linux loaders that will corrupt the EBDA
794 * area, and as such this kind of SMP config may be less
795 * trustworthy, simply because the SMP table may have been
796 * stomped on during early boot. These loaders are buggy and
797 * should be fixed.
798 *
799 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
800 */
801
802 address = get_bios_ebda();
803 if (address)
804 smp_scan_config(address, 0x400);
805}
806
807/* --------------------------------------------------------------------------
808 ACPI-based MP Configuration
809 -------------------------------------------------------------------------- */
810
888ba6c6 811#ifdef CONFIG_ACPI
1da177e4
LT		 812
813void __init mp_register_lapic_address (
814 u64 address)
815{
816 mp_lapic_addr = (unsigned long) address;
817
818 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
819
820 if (boot_cpu_physical_apicid == -1U)
821 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
822
823 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
824}
825
826
827void __init mp_register_lapic (
828 u8 id,
829 u8 enabled)
830{
831 struct mpc_config_processor processor;
832 int boot_cpu = 0;
833
834 if (MAX_APICS - id <= 0) {
835 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
836 id, MAX_APICS);
837 return;
838 }
839
840 if (id == boot_cpu_physical_apicid)
841 boot_cpu = 1;
842
843 processor.mpc_type = MP_PROCESSOR;
844 processor.mpc_apicid = id;
845 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
846 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
847 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
848 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
849 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
850 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
851 processor.mpc_reserved[0] = 0;
852 processor.mpc_reserved[1] = 0;
853
854 MP_processor_info(&processor);
855}
856
888ba6c6 857#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
1da177e4
LT		 858
859#define MP_ISA_BUS 0
860#define MP_MAX_IOAPIC_PIN 127
861
862static struct mp_ioapic_routing {
863 int apic_id;
864 int gsi_base;
865 int gsi_end;
866 u32 pin_programmed[4];
867} mp_ioapic_routing[MAX_IO_APICS];
868
869
870static int mp_find_ioapic (
871 int gsi)
872{
873 int i = 0;
874
875 /* Find the IOAPIC that manages this GSI. */
876 for (i = 0; i < nr_ioapics; i++) {
877 if ((gsi >= mp_ioapic_routing[i].gsi_base)
878 && (gsi <= mp_ioapic_routing[i].gsi_end))
879 return i;
880 }
881
882 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
883
884 return -1;
885}
886
887
888void __init mp_register_ioapic (
889 u8 id,
890 u32 address,
891 u32 gsi_base)
892{
893 int idx = 0;
894
895 if (nr_ioapics >= MAX_IO_APICS) {
896 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
897 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
898 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
899 }
900 if (!address) {
901 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
902 " found in MADT table, skipping!\n");
903 return;
904 }
905
906 idx = nr_ioapics++;
907
908 mp_ioapics[idx].mpc_type = MP_IOAPIC;
909 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
910 mp_ioapics[idx].mpc_apicaddr = address;
911
912 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
ca05fea6
NP		 913 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))
914 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
915 else
916 mp_ioapics[idx].mpc_apicid = id;
1da177e4
LT		 917 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
918
919 /*
920 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
921 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
922 */
923 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
924 mp_ioapic_routing[idx].gsi_base = gsi_base;
925 mp_ioapic_routing[idx].gsi_end = gsi_base +
926 io_apic_get_redir_entries(idx);
927
928 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
929 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
930 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
931 mp_ioapic_routing[idx].gsi_base,
932 mp_ioapic_routing[idx].gsi_end);
933
934 return;
935}
936
937
938void __init mp_override_legacy_irq (
939 u8 bus_irq,
940 u8 polarity,
941 u8 trigger,
942 u32 gsi)
943{
944 struct mpc_config_intsrc intsrc;
945 int ioapic = -1;
946 int pin = -1;
947
948 /*
949 * Convert 'gsi' to 'ioapic.pin'.
950 */
951 ioapic = mp_find_ioapic(gsi);
952 if (ioapic < 0)
953 return;
954 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
955
956 /*
957 * TBD: This check is for faulty timer entries, where the override
958 * erroneously sets the trigger to level, resulting in a HUGE
959 * increase of timer interrupts!
960 */
961 if ((bus_irq == 0) && (trigger == 3))
962 trigger = 1;
963
964 intsrc.mpc_type = MP_INTSRC;
965 intsrc.mpc_irqtype = mp_INT;
966 intsrc.mpc_irqflag = (trigger << 2) | polarity;
967 intsrc.mpc_srcbus = MP_ISA_BUS;
968 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
969 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
970 intsrc.mpc_dstirq = pin; /* INTIN# */
971
972 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
973 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
974 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
975 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
976
977 mp_irqs[mp_irq_entries] = intsrc;
978 if (++mp_irq_entries == MAX_IRQ_SOURCES)
979 panic("Max # of irq sources exceeded!\n");
980
981 return;
982}
983
984int es7000_plat;
985
986void __init mp_config_acpi_legacy_irqs (void)
987{
988 struct mpc_config_intsrc intsrc;
989 int i = 0;
990 int ioapic = -1;
991
992 /*
993 * Fabricate the legacy ISA bus (bus #31).
994 */
995 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
996 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
997
998 /*
999 * Older generations of ES7000 have no legacy identity mappings
1000 */
1001 if (es7000_plat == 1)
1002 return;
1003
1004 /*
1005 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1006 */
1007 ioapic = mp_find_ioapic(0);
1008 if (ioapic < 0)
1009 return;
1010
1011 intsrc.mpc_type = MP_INTSRC;
1012 intsrc.mpc_irqflag = 0; /* Conforming */
1013 intsrc.mpc_srcbus = MP_ISA_BUS;
1014 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1015
1016 /*
1017 * Use the default configuration for the IRQs 0-15. Unless
1018 * overriden by (MADT) interrupt source override entries.
1019 */
1020 for (i = 0; i < 16; i++) {
1021 int idx;
1022
1023 for (idx = 0; idx < mp_irq_entries; idx++) {
1024 struct mpc_config_intsrc *irq = mp_irqs + idx;
1025
1026 /* Do we already have a mapping for this ISA IRQ? */
1027 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1028 break;
1029
1030 /* Do we already have a mapping for this IOAPIC pin */
1031 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1032 (irq->mpc_dstirq == i))
1033 break;
1034 }
1035
1036 if (idx != mp_irq_entries) {
1037 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1038 continue; /* IRQ already used */
1039 }
1040
1041 intsrc.mpc_irqtype = mp_INT;
1042 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1043 intsrc.mpc_dstirq = i;
1044
1045 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1046 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1047 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1048 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1049 intsrc.mpc_dstirq);
1050
1051 mp_irqs[mp_irq_entries] = intsrc;
1052 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1053 panic("Max # of irq sources exceeded!\n");
1054 }
1055}
1056
c434b7a6
NP		 1057#define MAX_GSI_NUM 4096
1058
1da177e4
LT		 1059int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
1060{
1061 int ioapic = -1;
1062 int ioapic_pin = 0;
1063 int idx, bit = 0;
c434b7a6
NP		 1064 static int pci_irq = 16;
1065 /*
1066 * Mapping between Global System Interrups, which
1067 * represent all possible interrupts, and IRQs
1068 * assigned to actual devices.
1069 */
1070 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4
LT		 1071
1072#ifdef CONFIG_ACPI_BUS
1073 /* Don't set up the ACPI SCI because it's already set up */
1074 if (acpi_fadt.sci_int == gsi)
1075 return gsi;
1076#endif
1077
1078 ioapic = mp_find_ioapic(gsi);
1079 if (ioapic < 0) {
1080 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1081 return gsi;
1082 }
1083
1084 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1085
1086 if (ioapic_renumber_irq)
1087 gsi = ioapic_renumber_irq(ioapic, gsi);
1088
1089 /*
1090 * Avoid pin reprogramming. PRTs typically include entries
1091 * with redundant pin->gsi mappings (but unique PCI devices);
1092 * we only program the IOAPIC on the first.
1093 */
1094 bit = ioapic_pin % 32;
1095 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1096 if (idx > 3) {
1097 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1098 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1099 ioapic_pin);
1100 return gsi;
1101 }
1102 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1103 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1104 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
c434b7a6 1105 return gsi_to_irq[gsi];
1da177e4
LT		 1106 }
1107
1108 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1109
c434b7a6
NP		 1110 if (edge_level) {
1111 /*
1112 * For PCI devices assign IRQs in order, avoiding gaps
1113 * due to unused I/O APIC pins.
1114 */
1115 int irq = gsi;
1116 if (gsi < MAX_GSI_NUM) {
e1afc3f5
NP		 1117 if (gsi > 15)
1118 gsi = pci_irq++;
1119#ifdef CONFIG_ACPI_BUS
1120 /*
1121 * Don't assign IRQ used by ACPI SCI
1122 */
1123 if (gsi == acpi_fadt.sci_int)
1124 gsi = pci_irq++;
1125#endif
c434b7a6
NP		 1126 gsi_to_irq[irq] = gsi;
1127 } else {
1128 printk(KERN_ERR "GSI %u is too high\n", gsi);
1129 return gsi;
1130 }
1131 }
1132
1da177e4
LT		 1133 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1134 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
1135 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
1136 return gsi;
1137}
1138
888ba6c6
LB		 1139#endif /* CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER */
1140#endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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