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[PATCH] i386: Consolidate modern APIC handling
[deliverable/linux.git] / arch / i386 / kernel / mpparse.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
1da177e4
LT		 17#include <linux/init.h>
18#include <linux/acpi.h>
19#include <linux/delay.h>
20#include <linux/config.h>
21#include <linux/bootmem.h>
22#include <linux/smp_lock.h>
23#include <linux/kernel_stat.h>
24#include <linux/mc146818rtc.h>
25#include <linux/bitops.h>
26
27#include <asm/smp.h>
28#include <asm/acpi.h>
29#include <asm/mtrr.h>
30#include <asm/mpspec.h>
31#include <asm/io_apic.h>
32
33#include <mach_apic.h>
34#include <mach_mpparse.h>
35#include <bios_ebda.h>
36
37/* Have we found an MP table */
38int smp_found_config;
39unsigned int __initdata maxcpus = NR_CPUS;
40
e72c8585
AR		 41#ifdef CONFIG_HOTPLUG_CPU
42#define CPU_HOTPLUG_ENABLED (1)
43#else
44#define CPU_HOTPLUG_ENABLED (0)
45#endif
46
1da177e4
LT		 47/*
48 * Various Linux-internal data structures created from the
49 * MP-table.
50 */
51int apic_version [MAX_APICS];
52int mp_bus_id_to_type [MAX_MP_BUSSES];
53int mp_bus_id_to_node [MAX_MP_BUSSES];
54int mp_bus_id_to_local [MAX_MP_BUSSES];
55int quad_local_to_mp_bus_id [NR_CPUS/4][4];
56int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
57static int mp_current_pci_id;
58
59/* I/O APIC entries */
60struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
61
62/* # of MP IRQ source entries */
63struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
64
65/* MP IRQ source entries */
66int mp_irq_entries;
67
68int nr_ioapics;
69
70int pic_mode;
71unsigned long mp_lapic_addr;
72
911a62d4
VP		 73unsigned int def_to_bigsmp = 0;
74
1da177e4
LT		 75/* Processor that is doing the boot up */
76unsigned int boot_cpu_physical_apicid = -1U;
1da177e4 77/* Internal processor count */
9f40a72a 78static unsigned int __devinitdata num_processors;
1da177e4
LT		 79
80/* Bitmask of physically existing CPUs */
81physid_mask_t phys_cpu_present_map;
82
83u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
84
85/*
86 * Intel MP BIOS table parsing routines:
87 */
88
89
90/*
91 * Checksum an MP configuration block.
92 */
93
94static int __init mpf_checksum(unsigned char *mp, int len)
95{
96 int sum = 0;
97
98 while (len--)
99 sum += *mp++;
100
101 return sum & 0xFF;
102}
103
104/*
105 * Have to match translation table entries to main table entries by counter
106 * hence the mpc_record variable .... can't see a less disgusting way of
107 * doing this ....
108 */
109
110static int mpc_record;
111static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
112
9f40a72a 113static void __devinit MP_processor_info (struct mpc_config_processor *m)
1da177e4 114{
1299232b
AM		 115 int ver, apicid;
116 physid_mask_t phys_cpu;
1da177e4
LT		 117
118 if (!(m->mpc_cpuflag & CPU_ENABLED))
119 return;
120
121 apicid = mpc_apic_id(m, translation_table[mpc_record]);
122
123 if (m->mpc_featureflag&(1<<0))
124 Dprintk(" Floating point unit present.\n");
125 if (m->mpc_featureflag&(1<<7))
126 Dprintk(" Machine Exception supported.\n");
127 if (m->mpc_featureflag&(1<<8))
128 Dprintk(" 64 bit compare & exchange supported.\n");
129 if (m->mpc_featureflag&(1<<9))
130 Dprintk(" Internal APIC present.\n");
131 if (m->mpc_featureflag&(1<<11))
132 Dprintk(" SEP present.\n");
133 if (m->mpc_featureflag&(1<<12))
134 Dprintk(" MTRR present.\n");
135 if (m->mpc_featureflag&(1<<13))
136 Dprintk(" PGE present.\n");
137 if (m->mpc_featureflag&(1<<14))
138 Dprintk(" MCA present.\n");
139 if (m->mpc_featureflag&(1<<15))
140 Dprintk(" CMOV present.\n");
141 if (m->mpc_featureflag&(1<<16))
142 Dprintk(" PAT present.\n");
143 if (m->mpc_featureflag&(1<<17))
144 Dprintk(" PSE present.\n");
145 if (m->mpc_featureflag&(1<<18))
146 Dprintk(" PSN present.\n");
147 if (m->mpc_featureflag&(1<<19))
148 Dprintk(" Cache Line Flush Instruction present.\n");
149 /* 20 Reserved */
150 if (m->mpc_featureflag&(1<<21))
151 Dprintk(" Debug Trace and EMON Store present.\n");
152 if (m->mpc_featureflag&(1<<22))
153 Dprintk(" ACPI Thermal Throttle Registers present.\n");
154 if (m->mpc_featureflag&(1<<23))
155 Dprintk(" MMX present.\n");
156 if (m->mpc_featureflag&(1<<24))
157 Dprintk(" FXSR present.\n");
158 if (m->mpc_featureflag&(1<<25))
159 Dprintk(" XMM present.\n");
160 if (m->mpc_featureflag&(1<<26))
161 Dprintk(" Willamette New Instructions present.\n");
162 if (m->mpc_featureflag&(1<<27))
163 Dprintk(" Self Snoop present.\n");
164 if (m->mpc_featureflag&(1<<28))
165 Dprintk(" HT present.\n");
166 if (m->mpc_featureflag&(1<<29))
167 Dprintk(" Thermal Monitor present.\n");
168 /* 30, 31 Reserved */
169
170
171 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
172 Dprintk(" Bootup CPU\n");
173 boot_cpu_physical_apicid = m->mpc_apicid;
1da177e4
LT		 174 }
175
1da177e4
LT		 176 ver = m->mpc_apicver;
177
1da177e4
LT		 178 /*
179 * Validate version
180 */
181 if (ver == 0x0) {
1299232b
AM		 182 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
183 "fixing up to 0x10. (tell your hw vendor)\n",
184 m->mpc_apicid);
1da177e4
LT		 185 ver = 0x10;
186 }
187 apic_version[m->mpc_apicid] = ver;
6c180d94
EB		 188
189 phys_cpu = apicid_to_cpu_present(apicid);
190 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
191
192 if (num_processors >= NR_CPUS) {
193 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
194 " Processor ignored.\n", NR_CPUS);
195 return;
196 }
197
198 if (num_processors >= maxcpus) {
199 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
200 " Processor ignored.\n", maxcpus);
201 return;
202 }
203
204 cpu_set(num_processors, cpu_possible_map);
205 num_processors++;
206
e72c8585
AR		 207 if (CPU_HOTPLUG_ENABLED || (num_processors > 8)) {
208 switch (boot_cpu_data.x86_vendor) {
209 case X86_VENDOR_INTEL:
210 if (!APIC_XAPIC(ver)) {
211 def_to_bigsmp = 0;
212 break;
213 }
214 /* If P4 and above fall through */
215 case X86_VENDOR_AMD:
216 def_to_bigsmp = 1;
217 }
218 }
1da177e4
LT		 219 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
220}
221
222static void __init MP_bus_info (struct mpc_config_bus *m)
223{
224 char str[7];
225
226 memcpy(str, m->mpc_bustype, 6);
227 str[6] = 0;
228
229 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
230
231 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
232 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
233 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
234 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
235 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
236 mpc_oem_pci_bus(m, translation_table[mpc_record]);
237 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
238 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
239 mp_current_pci_id++;
240 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
241 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
242 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
243 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
244 } else {
245 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
246 }
247}
248
249static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
250{
251 if (!(m->mpc_flags & MPC_APIC_USABLE))
252 return;
253
254 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
255 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
256 if (nr_ioapics >= MAX_IO_APICS) {
257 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
258 MAX_IO_APICS, nr_ioapics);
259 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
260 }
261 if (!m->mpc_apicaddr) {
262 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
263 " found in MP table, skipping!\n");
264 return;
265 }
266 mp_ioapics[nr_ioapics] = *m;
267 nr_ioapics++;
268}
269
270static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
271{
272 mp_irqs [mp_irq_entries] = *m;
273 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
274 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
275 m->mpc_irqtype, m->mpc_irqflag & 3,
276 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
277 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
278 if (++mp_irq_entries == MAX_IRQ_SOURCES)
279 panic("Max # of irq sources exceeded!!\n");
280}
281
282static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
283{
284 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
285 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
286 m->mpc_irqtype, m->mpc_irqflag & 3,
287 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
288 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
289 /*
290 * Well it seems all SMP boards in existence
291 * use ExtINT/LVT1 == LINT0 and
292 * NMI/LVT2 == LINT1 - the following check
293 * will show us if this assumptions is false.
294 * Until then we do not have to add baggage.
295 */
296 if ((m->mpc_irqtype == mp_ExtINT) &&
297 (m->mpc_destapiclint != 0))
298 BUG();
299 if ((m->mpc_irqtype == mp_NMI) &&
300 (m->mpc_destapiclint != 1))
301 BUG();
302}
303
304#ifdef CONFIG_X86_NUMAQ
305static void __init MP_translation_info (struct mpc_config_translation *m)
306{
307 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
308
309 if (mpc_record >= MAX_MPC_ENTRY)
310 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
311 else
312 translation_table[mpc_record] = m; /* stash this for later */
313 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
314 node_set_online(m->trans_quad);
315}
316
317/*
318 * Read/parse the MPC oem tables
319 */
320
321static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
322 unsigned short oemsize)
323{
324 int count = sizeof (*oemtable); /* the header size */
325 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
326
327 mpc_record = 0;
328 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
329 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
330 {
331 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
332 oemtable->oem_signature[0],
333 oemtable->oem_signature[1],
334 oemtable->oem_signature[2],
335 oemtable->oem_signature[3]);
336 return;
337 }
338 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
339 {
340 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
341 return;
342 }
343 while (count < oemtable->oem_length) {
344 switch (*oemptr) {
345 case MP_TRANSLATION:
346 {
347 struct mpc_config_translation *m=
348 (struct mpc_config_translation *)oemptr;
349 MP_translation_info(m);
350 oemptr += sizeof(*m);
351 count += sizeof(*m);
352 ++mpc_record;
353 break;
354 }
355 default:
356 {
357 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
358 return;
359 }
360 }
361 }
362}
363
364static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
365 char *productid)
366{
367 if (strncmp(oem, "IBM NUMA", 8))
368 printk("Warning! May not be a NUMA-Q system!\n");
369 if (mpc->mpc_oemptr)
370 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
371 mpc->mpc_oemsize);
372}
373#endif /* CONFIG_X86_NUMAQ */
374
375/*
376 * Read/parse the MPC
377 */
378
379static int __init smp_read_mpc(struct mp_config_table *mpc)
380{
381 char str[16];
382 char oem[10];
383 int count=sizeof(*mpc);
384 unsigned char *mpt=((unsigned char *)mpc)+count;
385
386 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
387 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
388 *(u32 *)mpc->mpc_signature);
389 return 0;
390 }
391 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
392 printk(KERN_ERR "SMP mptable: checksum error!\n");
393 return 0;
394 }
395 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
396 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
397 mpc->mpc_spec);
398 return 0;
399 }
400 if (!mpc->mpc_lapic) {
401 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
402 return 0;
403 }
404 memcpy(oem,mpc->mpc_oem,8);
405 oem[8]=0;
406 printk(KERN_INFO "OEM ID: %s ",oem);
407
408 memcpy(str,mpc->mpc_productid,12);
409 str[12]=0;
410 printk("Product ID: %s ",str);
411
412 mps_oem_check(mpc, oem, str);
413
414 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
415
416 /*
417 * Save the local APIC address (it might be non-default) -- but only
418 * if we're not using ACPI.
419 */
420 if (!acpi_lapic)
421 mp_lapic_addr = mpc->mpc_lapic;
422
423 /*
424 * Now process the configuration blocks.
425 */
426 mpc_record = 0;
427 while (count < mpc->mpc_length) {
428 switch(*mpt) {
429 case MP_PROCESSOR:
430 {
431 struct mpc_config_processor *m=
432 (struct mpc_config_processor *)mpt;
433 /* ACPI may have already provided this data */
434 if (!acpi_lapic)
435 MP_processor_info(m);
436 mpt += sizeof(*m);
437 count += sizeof(*m);
438 break;
439 }
440 case MP_BUS:
441 {
442 struct mpc_config_bus *m=
443 (struct mpc_config_bus *)mpt;
444 MP_bus_info(m);
445 mpt += sizeof(*m);
446 count += sizeof(*m);
447 break;
448 }
449 case MP_IOAPIC:
450 {
451 struct mpc_config_ioapic *m=
452 (struct mpc_config_ioapic *)mpt;
453 MP_ioapic_info(m);
454 mpt+=sizeof(*m);
455 count+=sizeof(*m);
456 break;
457 }
458 case MP_INTSRC:
459 {
460 struct mpc_config_intsrc *m=
461 (struct mpc_config_intsrc *)mpt;
462
463 MP_intsrc_info(m);
464 mpt+=sizeof(*m);
465 count+=sizeof(*m);
466 break;
467 }
468 case MP_LINTSRC:
469 {
470 struct mpc_config_lintsrc *m=
471 (struct mpc_config_lintsrc *)mpt;
472 MP_lintsrc_info(m);
473 mpt+=sizeof(*m);
474 count+=sizeof(*m);
475 break;
476 }
477 default:
478 {
479 count = mpc->mpc_length;
480 break;
481 }
482 }
483 ++mpc_record;
484 }
485 clustered_apic_check();
486 if (!num_processors)
487 printk(KERN_ERR "SMP mptable: no processors registered!\n");
488 return num_processors;
489}
490
491static int __init ELCR_trigger(unsigned int irq)
492{
493 unsigned int port;
494
495 port = 0x4d0 + (irq >> 3);
496 return (inb(port) >> (irq & 7)) & 1;
497}
498
499static void __init construct_default_ioirq_mptable(int mpc_default_type)
500{
501 struct mpc_config_intsrc intsrc;
502 int i;
503 int ELCR_fallback = 0;
504
505 intsrc.mpc_type = MP_INTSRC;
506 intsrc.mpc_irqflag = 0; /* conforming */
507 intsrc.mpc_srcbus = 0;
508 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
509
510 intsrc.mpc_irqtype = mp_INT;
511
512 /*
513 * If true, we have an ISA/PCI system with no IRQ entries
514 * in the MP table. To prevent the PCI interrupts from being set up
515 * incorrectly, we try to use the ELCR. The sanity check to see if
516 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
517 * never be level sensitive, so we simply see if the ELCR agrees.
518 * If it does, we assume it's valid.
519 */
520 if (mpc_default_type == 5) {
521 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
522
523 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
524 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
525 else {
526 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
527 ELCR_fallback = 1;
528 }
529 }
530
531 for (i = 0; i < 16; i++) {
532 switch (mpc_default_type) {
533 case 2:
534 if (i == 0 || i == 13)
535 continue; /* IRQ0 & IRQ13 not connected */
536 /* fall through */
537 default:
538 if (i == 2)
539 continue; /* IRQ2 is never connected */
540 }
541
542 if (ELCR_fallback) {
543 /*
544 * If the ELCR indicates a level-sensitive interrupt, we
545 * copy that information over to the MP table in the
546 * irqflag field (level sensitive, active high polarity).
547 */
548 if (ELCR_trigger(i))
549 intsrc.mpc_irqflag = 13;
550 else
551 intsrc.mpc_irqflag = 0;
552 }
553
554 intsrc.mpc_srcbusirq = i;
555 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
556 MP_intsrc_info(&intsrc);
557 }
558
559 intsrc.mpc_irqtype = mp_ExtINT;
560 intsrc.mpc_srcbusirq = 0;
561 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
562 MP_intsrc_info(&intsrc);
563}
564
565static inline void __init construct_default_ISA_mptable(int mpc_default_type)
566{
567 struct mpc_config_processor processor;
568 struct mpc_config_bus bus;
569 struct mpc_config_ioapic ioapic;
570 struct mpc_config_lintsrc lintsrc;
571 int linttypes[2] = { mp_ExtINT, mp_NMI };
572 int i;
573
574 /*
575 * local APIC has default address
576 */
577 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
578
579 /*
580 * 2 CPUs, numbered 0 & 1.
581 */
582 processor.mpc_type = MP_PROCESSOR;
583 /* Either an integrated APIC or a discrete 82489DX. */
584 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
585 processor.mpc_cpuflag = CPU_ENABLED;
586 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
587 (boot_cpu_data.x86_model << 4) |
588 boot_cpu_data.x86_mask;
589 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
590 processor.mpc_reserved[0] = 0;
591 processor.mpc_reserved[1] = 0;
592 for (i = 0; i < 2; i++) {
593 processor.mpc_apicid = i;
594 MP_processor_info(&processor);
595 }
596
597 bus.mpc_type = MP_BUS;
598 bus.mpc_busid = 0;
599 switch (mpc_default_type) {
600 default:
601 printk("???\n");
602 printk(KERN_ERR "Unknown standard configuration %d\n",
603 mpc_default_type);
604 /* fall through */
605 case 1:
606 case 5:
607 memcpy(bus.mpc_bustype, "ISA ", 6);
608 break;
609 case 2:
610 case 6:
611 case 3:
612 memcpy(bus.mpc_bustype, "EISA ", 6);
613 break;
614 case 4:
615 case 7:
616 memcpy(bus.mpc_bustype, "MCA ", 6);
617 }
618 MP_bus_info(&bus);
619 if (mpc_default_type > 4) {
620 bus.mpc_busid = 1;
621 memcpy(bus.mpc_bustype, "PCI ", 6);
622 MP_bus_info(&bus);
623 }
624
625 ioapic.mpc_type = MP_IOAPIC;
626 ioapic.mpc_apicid = 2;
627 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
628 ioapic.mpc_flags = MPC_APIC_USABLE;
629 ioapic.mpc_apicaddr = 0xFEC00000;
630 MP_ioapic_info(&ioapic);
631
632 /*
633 * We set up most of the low 16 IO-APIC pins according to MPS rules.
634 */
635 construct_default_ioirq_mptable(mpc_default_type);
636
637 lintsrc.mpc_type = MP_LINTSRC;
638 lintsrc.mpc_irqflag = 0; /* conforming */
639 lintsrc.mpc_srcbusid = 0;
640 lintsrc.mpc_srcbusirq = 0;
641 lintsrc.mpc_destapic = MP_APIC_ALL;
642 for (i = 0; i < 2; i++) {
643 lintsrc.mpc_irqtype = linttypes[i];
644 lintsrc.mpc_destapiclint = i;
645 MP_lintsrc_info(&lintsrc);
646 }
647}
648
649static struct intel_mp_floating *mpf_found;
650
651/*
652 * Scan the memory blocks for an SMP configuration block.
653 */
654void __init get_smp_config (void)
655{
656 struct intel_mp_floating *mpf = mpf_found;
657
658 /*
1da177e4
LT		 659 * ACPI supports both logical (e.g. Hyper-Threading) and physical
660 * processors, where MPS only supports physical.
661 */
662 if (acpi_lapic && acpi_ioapic) {
663 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
664 return;
665 }
666 else if (acpi_lapic)
667 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
668
669 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
670 if (mpf->mpf_feature2 & (1<<7)) {
671 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
672 pic_mode = 1;
673 } else {
674 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
675 pic_mode = 0;
676 }
677
678 /*
679 * Now see if we need to read further.
680 */
681 if (mpf->mpf_feature1 != 0) {
682
683 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
684 construct_default_ISA_mptable(mpf->mpf_feature1);
685
686 } else if (mpf->mpf_physptr) {
687
688 /*
689 * Read the physical hardware table. Anything here will
690 * override the defaults.
691 */
7d4c8e56 692 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
1da177e4
LT		 693 smp_found_config = 0;
694 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
695 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
696 return;
697 }
698 /*
699 * If there are no explicit MP IRQ entries, then we are
700 * broken. We set up most of the low 16 IO-APIC pins to
701 * ISA defaults and hope it will work.
702 */
703 if (!mp_irq_entries) {
704 struct mpc_config_bus bus;
705
706 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
707
708 bus.mpc_type = MP_BUS;
709 bus.mpc_busid = 0;
710 memcpy(bus.mpc_bustype, "ISA ", 6);
711 MP_bus_info(&bus);
712
713 construct_default_ioirq_mptable(0);
714 }
715
716 } else
717 BUG();
718
719 printk(KERN_INFO "Processors: %d\n", num_processors);
720 /*
721 * Only use the first configuration found.
722 */
723}
724
725static int __init smp_scan_config (unsigned long base, unsigned long length)
726{
727 unsigned long *bp = phys_to_virt(base);
728 struct intel_mp_floating *mpf;
729
730 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
731 if (sizeof(*mpf) != 16)
732 printk("Error: MPF size\n");
733
734 while (length > 0) {
735 mpf = (struct intel_mp_floating *)bp;
736 if ((*bp == SMP_MAGIC_IDENT) &&
737 (mpf->mpf_length == 1) &&
738 !mpf_checksum((unsigned char *)bp, 16) &&
739 ((mpf->mpf_specification == 1)
740 || (mpf->mpf_specification == 4)) ) {
741
742 smp_found_config = 1;
743 printk(KERN_INFO "found SMP MP-table at %08lx\n",
744 virt_to_phys(mpf));
745 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
746 if (mpf->mpf_physptr) {
747 /*
748 * We cannot access to MPC table to compute
749 * table size yet, as only few megabytes from
750 * the bottom is mapped now.
751 * PC-9800's MPC table places on the very last
752 * of physical memory; so that simply reserving
753 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
754 * in reserve_bootmem.
755 */
756 unsigned long size = PAGE_SIZE;
757 unsigned long end = max_low_pfn * PAGE_SIZE;
758 if (mpf->mpf_physptr + size > end)
759 size = end - mpf->mpf_physptr;
760 reserve_bootmem(mpf->mpf_physptr, size);
761 }
762
763 mpf_found = mpf;
764 return 1;
765 }
766 bp += 4;
767 length -= 16;
768 }
769 return 0;
770}
771
772void __init find_smp_config (void)
773{
774 unsigned int address;
775
776 /*
777 * FIXME: Linux assumes you have 640K of base ram..
778 * this continues the error...
779 *
780 * 1) Scan the bottom 1K for a signature
781 * 2) Scan the top 1K of base RAM
782 * 3) Scan the 64K of bios
783 */
784 if (smp_scan_config(0x0,0x400) ||
785 smp_scan_config(639*0x400,0x400) ||
786 smp_scan_config(0xF0000,0x10000))
787 return;
788 /*
789 * If it is an SMP machine we should know now, unless the
790 * configuration is in an EISA/MCA bus machine with an
791 * extended bios data area.
792 *
793 * there is a real-mode segmented pointer pointing to the
794 * 4K EBDA area at 0x40E, calculate and scan it here.
795 *
796 * NOTE! There are Linux loaders that will corrupt the EBDA
797 * area, and as such this kind of SMP config may be less
798 * trustworthy, simply because the SMP table may have been
799 * stomped on during early boot. These loaders are buggy and
800 * should be fixed.
801 *
802 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
803 */
804
805 address = get_bios_ebda();
806 if (address)
807 smp_scan_config(address, 0x400);
808}
809
e5428ede
NP		 810int es7000_plat;
811
1da177e4
LT		 812/* --------------------------------------------------------------------------
813 ACPI-based MP Configuration
814 -------------------------------------------------------------------------- */
815
888ba6c6 816#ifdef CONFIG_ACPI
1da177e4
LT		 817
818void __init mp_register_lapic_address (
819 u64 address)
820{
821 mp_lapic_addr = (unsigned long) address;
822
823 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
824
825 if (boot_cpu_physical_apicid == -1U)
826 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
827
828 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
829}
830
831
9f40a72a 832void __devinit mp_register_lapic (
1da177e4
LT		 833 u8 id,
834 u8 enabled)
835{
836 struct mpc_config_processor processor;
837 int boot_cpu = 0;
838
839 if (MAX_APICS - id <= 0) {
840 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
841 id, MAX_APICS);
842 return;
843 }
844
845 if (id == boot_cpu_physical_apicid)
846 boot_cpu = 1;
847
848 processor.mpc_type = MP_PROCESSOR;
849 processor.mpc_apicid = id;
850 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
851 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
852 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
853 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
854 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
855 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
856 processor.mpc_reserved[0] = 0;
857 processor.mpc_reserved[1] = 0;
858
859 MP_processor_info(&processor);
860}
861
8466361a 862#ifdef CONFIG_X86_IO_APIC
1da177e4
LT		 863
864#define MP_ISA_BUS 0
865#define MP_MAX_IOAPIC_PIN 127
866
867static struct mp_ioapic_routing {
868 int apic_id;
869 int gsi_base;
870 int gsi_end;
871 u32 pin_programmed[4];
872} mp_ioapic_routing[MAX_IO_APICS];
873
874
875static int mp_find_ioapic (
876 int gsi)
877{
878 int i = 0;
879
880 /* Find the IOAPIC that manages this GSI. */
881 for (i = 0; i < nr_ioapics; i++) {
882 if ((gsi >= mp_ioapic_routing[i].gsi_base)
883 && (gsi <= mp_ioapic_routing[i].gsi_end))
884 return i;
885 }
886
887 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
888
889 return -1;
890}
891
892
893void __init mp_register_ioapic (
894 u8 id,
895 u32 address,
896 u32 gsi_base)
897{
898 int idx = 0;
6070f9ec 899 int tmpid;
1da177e4
LT		 900
901 if (nr_ioapics >= MAX_IO_APICS) {
902 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
903 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
904 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
905 }
906 if (!address) {
907 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
908 " found in MADT table, skipping!\n");
909 return;
910 }
911
912 idx = nr_ioapics++;
913
914 mp_ioapics[idx].mpc_type = MP_IOAPIC;
915 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
916 mp_ioapics[idx].mpc_apicaddr = address;
917
918 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
7c5c1e42
SL		 919 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
920 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
6070f9ec 921 tmpid = io_apic_get_unique_id(idx, id);
ca05fea6 922 else
6070f9ec
AD		 923 tmpid = id;
924 if (tmpid == -1) {
925 nr_ioapics--;
926 return;
927 }
928 mp_ioapics[idx].mpc_apicid = tmpid;
1da177e4
LT		 929 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
930
931 /*
932 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
933 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
934 */
935 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
936 mp_ioapic_routing[idx].gsi_base = gsi_base;
937 mp_ioapic_routing[idx].gsi_end = gsi_base +
938 io_apic_get_redir_entries(idx);
939
940 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
941 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
942 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
943 mp_ioapic_routing[idx].gsi_base,
944 mp_ioapic_routing[idx].gsi_end);
945
946 return;
947}
948
949
950void __init mp_override_legacy_irq (
951 u8 bus_irq,
952 u8 polarity,
953 u8 trigger,
954 u32 gsi)
955{
956 struct mpc_config_intsrc intsrc;
957 int ioapic = -1;
958 int pin = -1;
959
960 /*
961 * Convert 'gsi' to 'ioapic.pin'.
962 */
963 ioapic = mp_find_ioapic(gsi);
964 if (ioapic < 0)
965 return;
966 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
967
968 /*
969 * TBD: This check is for faulty timer entries, where the override
970 * erroneously sets the trigger to level, resulting in a HUGE
971 * increase of timer interrupts!
972 */
973 if ((bus_irq == 0) && (trigger == 3))
974 trigger = 1;
975
976 intsrc.mpc_type = MP_INTSRC;
977 intsrc.mpc_irqtype = mp_INT;
978 intsrc.mpc_irqflag = (trigger << 2) | polarity;
979 intsrc.mpc_srcbus = MP_ISA_BUS;
980 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
981 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
982 intsrc.mpc_dstirq = pin; /* INTIN# */
983
984 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
985 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
986 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
987 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
988
989 mp_irqs[mp_irq_entries] = intsrc;
990 if (++mp_irq_entries == MAX_IRQ_SOURCES)
991 panic("Max # of irq sources exceeded!\n");
992
993 return;
994}
995
1da177e4
LT		 996void __init mp_config_acpi_legacy_irqs (void)
997{
998 struct mpc_config_intsrc intsrc;
999 int i = 0;
1000 int ioapic = -1;
1001
1002 /*
1003 * Fabricate the legacy ISA bus (bus #31).
1004 */
1005 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1006 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1007
1008 /*
1009 * Older generations of ES7000 have no legacy identity mappings
1010 */
1011 if (es7000_plat == 1)
1012 return;
1013
1014 /*
1015 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1016 */
1017 ioapic = mp_find_ioapic(0);
1018 if (ioapic < 0)
1019 return;
1020
1021 intsrc.mpc_type = MP_INTSRC;
1022 intsrc.mpc_irqflag = 0; /* Conforming */
1023 intsrc.mpc_srcbus = MP_ISA_BUS;
1024 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1025
1026 /*
1027 * Use the default configuration for the IRQs 0-15. Unless
1028 * overriden by (MADT) interrupt source override entries.
1029 */
1030 for (i = 0; i < 16; i++) {
1031 int idx;
1032
1033 for (idx = 0; idx < mp_irq_entries; idx++) {
1034 struct mpc_config_intsrc *irq = mp_irqs + idx;
1035
1036 /* Do we already have a mapping for this ISA IRQ? */
1037 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1038 break;
1039
1040 /* Do we already have a mapping for this IOAPIC pin */
1041 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1042 (irq->mpc_dstirq == i))
1043 break;
1044 }
1045
1046 if (idx != mp_irq_entries) {
1047 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1048 continue; /* IRQ already used */
1049 }
1050
1051 intsrc.mpc_irqtype = mp_INT;
1052 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1053 intsrc.mpc_dstirq = i;
1054
1055 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1056 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1057 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1058 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1059 intsrc.mpc_dstirq);
1060
1061 mp_irqs[mp_irq_entries] = intsrc;
1062 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1063 panic("Max # of irq sources exceeded!\n");
1064 }
1065}
1066
c434b7a6
NP		 1067#define MAX_GSI_NUM 4096
1068
cb654695 1069int mp_register_gsi (u32 gsi, int triggering, int polarity)
1da177e4
LT		 1070{
1071 int ioapic = -1;
1072 int ioapic_pin = 0;
1073 int idx, bit = 0;
c434b7a6
NP		 1074 static int pci_irq = 16;
1075 /*
1076 * Mapping between Global System Interrups, which
1077 * represent all possible interrupts, and IRQs
1078 * assigned to actual devices.
1079 */
1080 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4 1081
1da177e4
LT		 1082 /* Don't set up the ACPI SCI because it's already set up */
1083 if (acpi_fadt.sci_int == gsi)
1084 return gsi;
1da177e4
LT		 1085
1086 ioapic = mp_find_ioapic(gsi);
1087 if (ioapic < 0) {
1088 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1089 return gsi;
1090 }
1091
1092 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1093
1094 if (ioapic_renumber_irq)
1095 gsi = ioapic_renumber_irq(ioapic, gsi);
1096
1097 /*
1098 * Avoid pin reprogramming. PRTs typically include entries
1099 * with redundant pin->gsi mappings (but unique PCI devices);
1100 * we only program the IOAPIC on the first.
1101 */
1102 bit = ioapic_pin % 32;
1103 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1104 if (idx > 3) {
1105 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1106 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1107 ioapic_pin);
1108 return gsi;
1109 }
1110 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1111 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1112 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
c434b7a6 1113 return gsi_to_irq[gsi];
1da177e4
LT		 1114 }
1115
1116 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1117
cb654695 1118 if (triggering == ACPI_LEVEL_SENSITIVE) {
c434b7a6
NP		 1119 /*
1120 * For PCI devices assign IRQs in order, avoiding gaps
1121 * due to unused I/O APIC pins.
1122 */
1123 int irq = gsi;
1124 if (gsi < MAX_GSI_NUM) {
e1afc3f5
NP		 1125 if (gsi > 15)
1126 gsi = pci_irq++;
e1afc3f5
NP		 1127 /*
1128 * Don't assign IRQ used by ACPI SCI
1129 */
1130 if (gsi == acpi_fadt.sci_int)
1131 gsi = pci_irq++;
c434b7a6
NP		 1132 gsi_to_irq[irq] = gsi;
1133 } else {
1134 printk(KERN_ERR "GSI %u is too high\n", gsi);
1135 return gsi;
1136 }
1137 }
1138
1da177e4 1139 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
cb654695
LB		 1140 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1141 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1da177e4
LT		 1142 return gsi;
1143}
1144
8466361a 1145#endif /* CONFIG_X86_IO_APIC */
888ba6c6 1146#endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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