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ACPICA: Remove duplicate table manager
[deliverable/linux.git] / arch / i386 / kernel / mpparse.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
1da177e4
LT		 17#include <linux/init.h>
18#include <linux/acpi.h>
19#include <linux/delay.h>
1da177e4
LT		 20#include <linux/bootmem.h>
21#include <linux/smp_lock.h>
22#include <linux/kernel_stat.h>
23#include <linux/mc146818rtc.h>
24#include <linux/bitops.h>
25
26#include <asm/smp.h>
27#include <asm/acpi.h>
28#include <asm/mtrr.h>
29#include <asm/mpspec.h>
30#include <asm/io_apic.h>
31
32#include <mach_apic.h>
874c4fe3 33#include <mach_apicdef.h>
1da177e4
LT		 34#include <mach_mpparse.h>
35#include <bios_ebda.h>
36
37/* Have we found an MP table */
38int smp_found_config;
4a5d107a 39unsigned int __cpuinitdata maxcpus = NR_CPUS;
1da177e4
LT		 40
41/*
42 * Various Linux-internal data structures created from the
43 * MP-table.
44 */
45int apic_version [MAX_APICS];
46int mp_bus_id_to_type [MAX_MP_BUSSES];
47int mp_bus_id_to_node [MAX_MP_BUSSES];
48int mp_bus_id_to_local [MAX_MP_BUSSES];
49int quad_local_to_mp_bus_id [NR_CPUS/4][4];
50int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
51static int mp_current_pci_id;
52
53/* I/O APIC entries */
54struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55
56/* # of MP IRQ source entries */
57struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58
59/* MP IRQ source entries */
60int mp_irq_entries;
61
62int nr_ioapics;
63
64int pic_mode;
65unsigned long mp_lapic_addr;
66
911a62d4
VP		 67unsigned int def_to_bigsmp = 0;
68
1da177e4
LT		 69/* Processor that is doing the boot up */
70unsigned int boot_cpu_physical_apicid = -1U;
1da177e4 71/* Internal processor count */
73fea175 72unsigned int __cpuinitdata num_processors;
1da177e4
LT		 73
74/* Bitmask of physically existing CPUs */
75physid_mask_t phys_cpu_present_map;
76
77u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
78
79/*
80 * Intel MP BIOS table parsing routines:
81 */
82
83
84/*
85 * Checksum an MP configuration block.
86 */
87
88static int __init mpf_checksum(unsigned char *mp, int len)
89{
90 int sum = 0;
91
92 while (len--)
93 sum += *mp++;
94
95 return sum & 0xFF;
96}
97
98/*
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
101 * doing this ....
102 */
103
104static int mpc_record;
4a5d107a 105static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
1da177e4 106
4a5d107a 107static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
1da177e4 108{
1299232b
AM		 109 int ver, apicid;
110 physid_mask_t phys_cpu;
1da177e4
LT		 111
112 if (!(m->mpc_cpuflag & CPU_ENABLED))
113 return;
114
115 apicid = mpc_apic_id(m, translation_table[mpc_record]);
116
117 if (m->mpc_featureflag&(1<<0))
118 Dprintk(" Floating point unit present.\n");
119 if (m->mpc_featureflag&(1<<7))
120 Dprintk(" Machine Exception supported.\n");
121 if (m->mpc_featureflag&(1<<8))
122 Dprintk(" 64 bit compare & exchange supported.\n");
123 if (m->mpc_featureflag&(1<<9))
124 Dprintk(" Internal APIC present.\n");
125 if (m->mpc_featureflag&(1<<11))
126 Dprintk(" SEP present.\n");
127 if (m->mpc_featureflag&(1<<12))
128 Dprintk(" MTRR present.\n");
129 if (m->mpc_featureflag&(1<<13))
130 Dprintk(" PGE present.\n");
131 if (m->mpc_featureflag&(1<<14))
132 Dprintk(" MCA present.\n");
133 if (m->mpc_featureflag&(1<<15))
134 Dprintk(" CMOV present.\n");
135 if (m->mpc_featureflag&(1<<16))
136 Dprintk(" PAT present.\n");
137 if (m->mpc_featureflag&(1<<17))
138 Dprintk(" PSE present.\n");
139 if (m->mpc_featureflag&(1<<18))
140 Dprintk(" PSN present.\n");
141 if (m->mpc_featureflag&(1<<19))
142 Dprintk(" Cache Line Flush Instruction present.\n");
143 /* 20 Reserved */
144 if (m->mpc_featureflag&(1<<21))
145 Dprintk(" Debug Trace and EMON Store present.\n");
146 if (m->mpc_featureflag&(1<<22))
147 Dprintk(" ACPI Thermal Throttle Registers present.\n");
148 if (m->mpc_featureflag&(1<<23))
149 Dprintk(" MMX present.\n");
150 if (m->mpc_featureflag&(1<<24))
151 Dprintk(" FXSR present.\n");
152 if (m->mpc_featureflag&(1<<25))
153 Dprintk(" XMM present.\n");
154 if (m->mpc_featureflag&(1<<26))
155 Dprintk(" Willamette New Instructions present.\n");
156 if (m->mpc_featureflag&(1<<27))
157 Dprintk(" Self Snoop present.\n");
158 if (m->mpc_featureflag&(1<<28))
159 Dprintk(" HT present.\n");
160 if (m->mpc_featureflag&(1<<29))
161 Dprintk(" Thermal Monitor present.\n");
162 /* 30, 31 Reserved */
163
164
165 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
166 Dprintk(" Bootup CPU\n");
167 boot_cpu_physical_apicid = m->mpc_apicid;
1da177e4
LT		 168 }
169
1da177e4
LT		 170 ver = m->mpc_apicver;
171
1da177e4
LT		 172 /*
173 * Validate version
174 */
175 if (ver == 0x0) {
1299232b
AM		 176 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
177 "fixing up to 0x10. (tell your hw vendor)\n",
178 m->mpc_apicid);
1da177e4
LT		 179 ver = 0x10;
180 }
181 apic_version[m->mpc_apicid] = ver;
6c180d94
EB		 182
183 phys_cpu = apicid_to_cpu_present(apicid);
184 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
185
186 if (num_processors >= NR_CPUS) {
187 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
188 " Processor ignored.\n", NR_CPUS);
189 return;
190 }
191
192 if (num_processors >= maxcpus) {
193 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
194 " Processor ignored.\n", maxcpus);
195 return;
196 }
197
198 cpu_set(num_processors, cpu_possible_map);
199 num_processors++;
200
6cf272ac
AR		 201 /*
202 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
203 * but we need to work other dependencies like SMP_SUSPEND etc
204 * before this can be done without some confusion.
205 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
206 * - Ashok Raj <ashok.raj@intel.com>
207 */
208 if (num_processors > 8) {
e72c8585
AR		 209 switch (boot_cpu_data.x86_vendor) {
210 case X86_VENDOR_INTEL:
211 if (!APIC_XAPIC(ver)) {
212 def_to_bigsmp = 0;
213 break;
214 }
215 /* If P4 and above fall through */
216 case X86_VENDOR_AMD:
217 def_to_bigsmp = 1;
218 }
219 }
1da177e4
LT		 220 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
221}
222
223static void __init MP_bus_info (struct mpc_config_bus *m)
224{
225 char str[7];
226
227 memcpy(str, m->mpc_bustype, 6);
228 str[6] = 0;
229
230 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
231
5e4edbb7 232#if MAX_MP_BUSSES < 256
c0ec31ad
RD		 233 if (m->mpc_busid >= MAX_MP_BUSSES) {
234 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
235 " is too large, max. supported is %d\n",
236 m->mpc_busid, str, MAX_MP_BUSSES - 1);
237 return;
238 }
5e4edbb7 239#endif
c0ec31ad 240
1da177e4
LT		 241 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
242 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
243 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
244 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
245 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
246 mpc_oem_pci_bus(m, translation_table[mpc_record]);
247 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
248 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
249 mp_current_pci_id++;
250 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
251 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
1da177e4
LT		 252 } else {
253 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
254 }
255}
256
257static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
258{
259 if (!(m->mpc_flags & MPC_APIC_USABLE))
260 return;
261
262 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
263 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
264 if (nr_ioapics >= MAX_IO_APICS) {
265 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
266 MAX_IO_APICS, nr_ioapics);
267 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
268 }
269 if (!m->mpc_apicaddr) {
270 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
271 " found in MP table, skipping!\n");
272 return;
273 }
274 mp_ioapics[nr_ioapics] = *m;
275 nr_ioapics++;
276}
277
278static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
279{
280 mp_irqs [mp_irq_entries] = *m;
281 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
282 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
283 m->mpc_irqtype, m->mpc_irqflag & 3,
284 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
285 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
286 if (++mp_irq_entries == MAX_IRQ_SOURCES)
287 panic("Max # of irq sources exceeded!!\n");
288}
289
290static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
291{
292 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
293 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
294 m->mpc_irqtype, m->mpc_irqflag & 3,
295 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
296 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
1da177e4
LT		 297}
298
299#ifdef CONFIG_X86_NUMAQ
300static void __init MP_translation_info (struct mpc_config_translation *m)
301{
302 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
303
304 if (mpc_record >= MAX_MPC_ENTRY)
305 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
306 else
307 translation_table[mpc_record] = m; /* stash this for later */
308 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
309 node_set_online(m->trans_quad);
310}
311
312/*
313 * Read/parse the MPC oem tables
314 */
315
316static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
317 unsigned short oemsize)
318{
319 int count = sizeof (*oemtable); /* the header size */
320 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
321
322 mpc_record = 0;
323 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
324 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
325 {
326 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
327 oemtable->oem_signature[0],
328 oemtable->oem_signature[1],
329 oemtable->oem_signature[2],
330 oemtable->oem_signature[3]);
331 return;
332 }
333 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
334 {
335 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
336 return;
337 }
338 while (count < oemtable->oem_length) {
339 switch (*oemptr) {
340 case MP_TRANSLATION:
341 {
342 struct mpc_config_translation *m=
343 (struct mpc_config_translation *)oemptr;
344 MP_translation_info(m);
345 oemptr += sizeof(*m);
346 count += sizeof(*m);
347 ++mpc_record;
348 break;
349 }
350 default:
351 {
352 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
353 return;
354 }
355 }
356 }
357}
358
359static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
360 char *productid)
361{
362 if (strncmp(oem, "IBM NUMA", 8))
363 printk("Warning! May not be a NUMA-Q system!\n");
364 if (mpc->mpc_oemptr)
365 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
366 mpc->mpc_oemsize);
367}
368#endif /* CONFIG_X86_NUMAQ */
369
370/*
371 * Read/parse the MPC
372 */
373
374static int __init smp_read_mpc(struct mp_config_table *mpc)
375{
376 char str[16];
377 char oem[10];
378 int count=sizeof(*mpc);
379 unsigned char *mpt=((unsigned char *)mpc)+count;
380
381 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
382 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
383 *(u32 *)mpc->mpc_signature);
384 return 0;
385 }
386 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
387 printk(KERN_ERR "SMP mptable: checksum error!\n");
388 return 0;
389 }
390 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
391 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
392 mpc->mpc_spec);
393 return 0;
394 }
395 if (!mpc->mpc_lapic) {
396 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
397 return 0;
398 }
399 memcpy(oem,mpc->mpc_oem,8);
400 oem[8]=0;
401 printk(KERN_INFO "OEM ID: %s ",oem);
402
403 memcpy(str,mpc->mpc_productid,12);
404 str[12]=0;
405 printk("Product ID: %s ",str);
406
407 mps_oem_check(mpc, oem, str);
408
409 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
410
411 /*
412 * Save the local APIC address (it might be non-default) -- but only
413 * if we're not using ACPI.
414 */
415 if (!acpi_lapic)
416 mp_lapic_addr = mpc->mpc_lapic;
417
418 /*
419 * Now process the configuration blocks.
420 */
421 mpc_record = 0;
422 while (count < mpc->mpc_length) {
423 switch(*mpt) {
424 case MP_PROCESSOR:
425 {
426 struct mpc_config_processor *m=
427 (struct mpc_config_processor *)mpt;
428 /* ACPI may have already provided this data */
429 if (!acpi_lapic)
430 MP_processor_info(m);
431 mpt += sizeof(*m);
432 count += sizeof(*m);
433 break;
434 }
435 case MP_BUS:
436 {
437 struct mpc_config_bus *m=
438 (struct mpc_config_bus *)mpt;
439 MP_bus_info(m);
440 mpt += sizeof(*m);
441 count += sizeof(*m);
442 break;
443 }
444 case MP_IOAPIC:
445 {
446 struct mpc_config_ioapic *m=
447 (struct mpc_config_ioapic *)mpt;
448 MP_ioapic_info(m);
449 mpt+=sizeof(*m);
450 count+=sizeof(*m);
451 break;
452 }
453 case MP_INTSRC:
454 {
455 struct mpc_config_intsrc *m=
456 (struct mpc_config_intsrc *)mpt;
457
458 MP_intsrc_info(m);
459 mpt+=sizeof(*m);
460 count+=sizeof(*m);
461 break;
462 }
463 case MP_LINTSRC:
464 {
465 struct mpc_config_lintsrc *m=
466 (struct mpc_config_lintsrc *)mpt;
467 MP_lintsrc_info(m);
468 mpt+=sizeof(*m);
469 count+=sizeof(*m);
470 break;
471 }
472 default:
473 {
474 count = mpc->mpc_length;
475 break;
476 }
477 }
478 ++mpc_record;
479 }
480 clustered_apic_check();
481 if (!num_processors)
482 printk(KERN_ERR "SMP mptable: no processors registered!\n");
483 return num_processors;
484}
485
486static int __init ELCR_trigger(unsigned int irq)
487{
488 unsigned int port;
489
490 port = 0x4d0 + (irq >> 3);
491 return (inb(port) >> (irq & 7)) & 1;
492}
493
494static void __init construct_default_ioirq_mptable(int mpc_default_type)
495{
496 struct mpc_config_intsrc intsrc;
497 int i;
498 int ELCR_fallback = 0;
499
500 intsrc.mpc_type = MP_INTSRC;
501 intsrc.mpc_irqflag = 0; /* conforming */
502 intsrc.mpc_srcbus = 0;
503 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
504
505 intsrc.mpc_irqtype = mp_INT;
506
507 /*
508 * If true, we have an ISA/PCI system with no IRQ entries
509 * in the MP table. To prevent the PCI interrupts from being set up
510 * incorrectly, we try to use the ELCR. The sanity check to see if
511 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
512 * never be level sensitive, so we simply see if the ELCR agrees.
513 * If it does, we assume it's valid.
514 */
515 if (mpc_default_type == 5) {
516 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
517
518 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
519 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
520 else {
521 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
522 ELCR_fallback = 1;
523 }
524 }
525
526 for (i = 0; i < 16; i++) {
527 switch (mpc_default_type) {
528 case 2:
529 if (i == 0 || i == 13)
530 continue; /* IRQ0 & IRQ13 not connected */
531 /* fall through */
532 default:
533 if (i == 2)
534 continue; /* IRQ2 is never connected */
535 }
536
537 if (ELCR_fallback) {
538 /*
539 * If the ELCR indicates a level-sensitive interrupt, we
540 * copy that information over to the MP table in the
541 * irqflag field (level sensitive, active high polarity).
542 */
543 if (ELCR_trigger(i))
544 intsrc.mpc_irqflag = 13;
545 else
546 intsrc.mpc_irqflag = 0;
547 }
548
549 intsrc.mpc_srcbusirq = i;
550 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
551 MP_intsrc_info(&intsrc);
552 }
553
554 intsrc.mpc_irqtype = mp_ExtINT;
555 intsrc.mpc_srcbusirq = 0;
556 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
557 MP_intsrc_info(&intsrc);
558}
559
560static inline void __init construct_default_ISA_mptable(int mpc_default_type)
561{
562 struct mpc_config_processor processor;
563 struct mpc_config_bus bus;
564 struct mpc_config_ioapic ioapic;
565 struct mpc_config_lintsrc lintsrc;
566 int linttypes[2] = { mp_ExtINT, mp_NMI };
567 int i;
568
569 /*
570 * local APIC has default address
571 */
572 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
573
574 /*
575 * 2 CPUs, numbered 0 & 1.
576 */
577 processor.mpc_type = MP_PROCESSOR;
578 /* Either an integrated APIC or a discrete 82489DX. */
579 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
580 processor.mpc_cpuflag = CPU_ENABLED;
581 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
582 (boot_cpu_data.x86_model << 4) |
583 boot_cpu_data.x86_mask;
584 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
585 processor.mpc_reserved[0] = 0;
586 processor.mpc_reserved[1] = 0;
587 for (i = 0; i < 2; i++) {
588 processor.mpc_apicid = i;
589 MP_processor_info(&processor);
590 }
591
592 bus.mpc_type = MP_BUS;
593 bus.mpc_busid = 0;
594 switch (mpc_default_type) {
595 default:
596 printk("???\n");
597 printk(KERN_ERR "Unknown standard configuration %d\n",
598 mpc_default_type);
599 /* fall through */
600 case 1:
601 case 5:
602 memcpy(bus.mpc_bustype, "ISA ", 6);
603 break;
604 case 2:
605 case 6:
606 case 3:
607 memcpy(bus.mpc_bustype, "EISA ", 6);
608 break;
609 case 4:
610 case 7:
611 memcpy(bus.mpc_bustype, "MCA ", 6);
612 }
613 MP_bus_info(&bus);
614 if (mpc_default_type > 4) {
615 bus.mpc_busid = 1;
616 memcpy(bus.mpc_bustype, "PCI ", 6);
617 MP_bus_info(&bus);
618 }
619
620 ioapic.mpc_type = MP_IOAPIC;
621 ioapic.mpc_apicid = 2;
622 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
623 ioapic.mpc_flags = MPC_APIC_USABLE;
624 ioapic.mpc_apicaddr = 0xFEC00000;
625 MP_ioapic_info(&ioapic);
626
627 /*
628 * We set up most of the low 16 IO-APIC pins according to MPS rules.
629 */
630 construct_default_ioirq_mptable(mpc_default_type);
631
632 lintsrc.mpc_type = MP_LINTSRC;
633 lintsrc.mpc_irqflag = 0; /* conforming */
634 lintsrc.mpc_srcbusid = 0;
635 lintsrc.mpc_srcbusirq = 0;
636 lintsrc.mpc_destapic = MP_APIC_ALL;
637 for (i = 0; i < 2; i++) {
638 lintsrc.mpc_irqtype = linttypes[i];
639 lintsrc.mpc_destapiclint = i;
640 MP_lintsrc_info(&lintsrc);
641 }
642}
643
644static struct intel_mp_floating *mpf_found;
645
646/*
647 * Scan the memory blocks for an SMP configuration block.
648 */
649void __init get_smp_config (void)
650{
651 struct intel_mp_floating *mpf = mpf_found;
652
653 /*
1da177e4
LT		 654 * ACPI supports both logical (e.g. Hyper-Threading) and physical
655 * processors, where MPS only supports physical.
656 */
657 if (acpi_lapic && acpi_ioapic) {
658 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
659 return;
660 }
661 else if (acpi_lapic)
662 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
663
664 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
665 if (mpf->mpf_feature2 & (1<<7)) {
666 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
667 pic_mode = 1;
668 } else {
669 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
670 pic_mode = 0;
671 }
672
673 /*
674 * Now see if we need to read further.
675 */
676 if (mpf->mpf_feature1 != 0) {
677
678 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
679 construct_default_ISA_mptable(mpf->mpf_feature1);
680
681 } else if (mpf->mpf_physptr) {
682
683 /*
684 * Read the physical hardware table. Anything here will
685 * override the defaults.
686 */
7d4c8e56 687 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
1da177e4
LT		 688 smp_found_config = 0;
689 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
690 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
691 return;
692 }
693 /*
694 * If there are no explicit MP IRQ entries, then we are
695 * broken. We set up most of the low 16 IO-APIC pins to
696 * ISA defaults and hope it will work.
697 */
698 if (!mp_irq_entries) {
699 struct mpc_config_bus bus;
700
701 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
702
703 bus.mpc_type = MP_BUS;
704 bus.mpc_busid = 0;
705 memcpy(bus.mpc_bustype, "ISA ", 6);
706 MP_bus_info(&bus);
707
708 construct_default_ioirq_mptable(0);
709 }
710
711 } else
712 BUG();
713
714 printk(KERN_INFO "Processors: %d\n", num_processors);
715 /*
716 * Only use the first configuration found.
717 */
718}
719
720static int __init smp_scan_config (unsigned long base, unsigned long length)
721{
722 unsigned long *bp = phys_to_virt(base);
723 struct intel_mp_floating *mpf;
724
725 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
726 if (sizeof(*mpf) != 16)
727 printk("Error: MPF size\n");
728
729 while (length > 0) {
730 mpf = (struct intel_mp_floating *)bp;
731 if ((*bp == SMP_MAGIC_IDENT) &&
732 (mpf->mpf_length == 1) &&
733 !mpf_checksum((unsigned char *)bp, 16) &&
734 ((mpf->mpf_specification == 1)
735 || (mpf->mpf_specification == 4)) ) {
736
737 smp_found_config = 1;
738 printk(KERN_INFO "found SMP MP-table at %08lx\n",
739 virt_to_phys(mpf));
740 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
741 if (mpf->mpf_physptr) {
742 /*
743 * We cannot access to MPC table to compute
744 * table size yet, as only few megabytes from
745 * the bottom is mapped now.
746 * PC-9800's MPC table places on the very last
747 * of physical memory; so that simply reserving
748 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
749 * in reserve_bootmem.
750 */
751 unsigned long size = PAGE_SIZE;
752 unsigned long end = max_low_pfn * PAGE_SIZE;
753 if (mpf->mpf_physptr + size > end)
754 size = end - mpf->mpf_physptr;
755 reserve_bootmem(mpf->mpf_physptr, size);
756 }
757
758 mpf_found = mpf;
759 return 1;
760 }
761 bp += 4;
762 length -= 16;
763 }
764 return 0;
765}
766
767void __init find_smp_config (void)
768{
769 unsigned int address;
770
771 /*
772 * FIXME: Linux assumes you have 640K of base ram..
773 * this continues the error...
774 *
775 * 1) Scan the bottom 1K for a signature
776 * 2) Scan the top 1K of base RAM
777 * 3) Scan the 64K of bios
778 */
779 if (smp_scan_config(0x0,0x400) ||
780 smp_scan_config(639*0x400,0x400) ||
781 smp_scan_config(0xF0000,0x10000))
782 return;
783 /*
784 * If it is an SMP machine we should know now, unless the
785 * configuration is in an EISA/MCA bus machine with an
786 * extended bios data area.
787 *
788 * there is a real-mode segmented pointer pointing to the
789 * 4K EBDA area at 0x40E, calculate and scan it here.
790 *
791 * NOTE! There are Linux loaders that will corrupt the EBDA
792 * area, and as such this kind of SMP config may be less
793 * trustworthy, simply because the SMP table may have been
794 * stomped on during early boot. These loaders are buggy and
795 * should be fixed.
796 *
797 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
798 */
799
800 address = get_bios_ebda();
801 if (address)
802 smp_scan_config(address, 0x400);
803}
804
e5428ede
NP		 805int es7000_plat;
806
1da177e4
LT		 807/* --------------------------------------------------------------------------
808 ACPI-based MP Configuration
809 -------------------------------------------------------------------------- */
810
888ba6c6 811#ifdef CONFIG_ACPI
1da177e4 812
19f03ffe 813void __init mp_register_lapic_address(u64 address)
1da177e4
LT		 814{
815 mp_lapic_addr = (unsigned long) address;
816
817 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
818
819 if (boot_cpu_physical_apicid == -1U)
820 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
821
822 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
823}
824
4a5d107a 825void __cpuinit mp_register_lapic (u8 id, u8 enabled)
1da177e4
LT		 826{
827 struct mpc_config_processor processor;
19f03ffe 828 int boot_cpu = 0;
1da177e4
LT		 829
830 if (MAX_APICS - id <= 0) {
831 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
832 id, MAX_APICS);
833 return;
834 }
835
836 if (id == boot_cpu_physical_apicid)
837 boot_cpu = 1;
838
839 processor.mpc_type = MP_PROCESSOR;
840 processor.mpc_apicid = id;
841 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
842 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
843 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
844 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
845 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
846 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
847 processor.mpc_reserved[0] = 0;
848 processor.mpc_reserved[1] = 0;
849
850 MP_processor_info(&processor);
851}
852
8466361a 853#ifdef CONFIG_X86_IO_APIC
1da177e4
LT		 854
855#define MP_ISA_BUS 0
856#define MP_MAX_IOAPIC_PIN 127
857
858static struct mp_ioapic_routing {
859 int apic_id;
860 int gsi_base;
861 int gsi_end;
862 u32 pin_programmed[4];
863} mp_ioapic_routing[MAX_IO_APICS];
864
19f03ffe 865static int mp_find_ioapic (int gsi)
1da177e4 866{
19f03ffe 867 int i = 0;
1da177e4
LT		 868
869 /* Find the IOAPIC that manages this GSI. */
870 for (i = 0; i < nr_ioapics; i++) {
871 if ((gsi >= mp_ioapic_routing[i].gsi_base)
872 && (gsi <= mp_ioapic_routing[i].gsi_end))
873 return i;
874 }
875
876 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
877
878 return -1;
879}
1da177e4 880
19f03ffe 881void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
1da177e4 882{
19f03ffe
AK		 883 int idx = 0;
884 int tmpid;
1da177e4
LT		 885
886 if (nr_ioapics >= MAX_IO_APICS) {
887 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
888 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
889 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
890 }
891 if (!address) {
892 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
893 " found in MADT table, skipping!\n");
894 return;
895 }
896
897 idx = nr_ioapics++;
898
899 mp_ioapics[idx].mpc_type = MP_IOAPIC;
900 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
901 mp_ioapics[idx].mpc_apicaddr = address;
902
903 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
7c5c1e42
SL		 904 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
905 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
6070f9ec 906 tmpid = io_apic_get_unique_id(idx, id);
ca05fea6 907 else
6070f9ec
AD		 908 tmpid = id;
909 if (tmpid == -1) {
910 nr_ioapics--;
911 return;
912 }
913 mp_ioapics[idx].mpc_apicid = tmpid;
1da177e4
LT		 914 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
915
916 /*
917 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
918 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
919 */
920 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
921 mp_ioapic_routing[idx].gsi_base = gsi_base;
922 mp_ioapic_routing[idx].gsi_end = gsi_base +
923 io_apic_get_redir_entries(idx);
924
925 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
926 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
927 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
928 mp_ioapic_routing[idx].gsi_base,
929 mp_ioapic_routing[idx].gsi_end);
1da177e4
LT		 930}
931
19f03ffe
AK		 932void __init
933mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
1da177e4
LT		 934{
935 struct mpc_config_intsrc intsrc;
936 int ioapic = -1;
937 int pin = -1;
938
939 /*
940 * Convert 'gsi' to 'ioapic.pin'.
941 */
942 ioapic = mp_find_ioapic(gsi);
943 if (ioapic < 0)
944 return;
945 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
946
947 /*
948 * TBD: This check is for faulty timer entries, where the override
949 * erroneously sets the trigger to level, resulting in a HUGE
950 * increase of timer interrupts!
951 */
952 if ((bus_irq == 0) && (trigger == 3))
953 trigger = 1;
954
955 intsrc.mpc_type = MP_INTSRC;
956 intsrc.mpc_irqtype = mp_INT;
957 intsrc.mpc_irqflag = (trigger << 2) | polarity;
958 intsrc.mpc_srcbus = MP_ISA_BUS;
959 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
960 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
961 intsrc.mpc_dstirq = pin; /* INTIN# */
962
963 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
964 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
965 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
966 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
967
968 mp_irqs[mp_irq_entries] = intsrc;
969 if (++mp_irq_entries == MAX_IRQ_SOURCES)
970 panic("Max # of irq sources exceeded!\n");
1da177e4
LT		 971}
972
1da177e4
LT		 973void __init mp_config_acpi_legacy_irqs (void)
974{
975 struct mpc_config_intsrc intsrc;
19f03ffe
AK		 976 int i = 0;
977 int ioapic = -1;
1da177e4
LT		 978
979 /*
980 * Fabricate the legacy ISA bus (bus #31).
981 */
982 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
983 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
984
985 /*
986 * Older generations of ES7000 have no legacy identity mappings
987 */
988 if (es7000_plat == 1)
989 return;
990
991 /*
992 * Locate the IOAPIC that manages the ISA IRQs (0-15).
993 */
994 ioapic = mp_find_ioapic(0);
995 if (ioapic < 0)
996 return;
997
998 intsrc.mpc_type = MP_INTSRC;
999 intsrc.mpc_irqflag = 0; /* Conforming */
1000 intsrc.mpc_srcbus = MP_ISA_BUS;
1001 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1002
1003 /*
1004 * Use the default configuration for the IRQs 0-15. Unless
1005 * overriden by (MADT) interrupt source override entries.
1006 */
1007 for (i = 0; i < 16; i++) {
1008 int idx;
1009
1010 for (idx = 0; idx < mp_irq_entries; idx++) {
1011 struct mpc_config_intsrc *irq = mp_irqs + idx;
1012
1013 /* Do we already have a mapping for this ISA IRQ? */
1014 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1015 break;
1016
1017 /* Do we already have a mapping for this IOAPIC pin */
1018 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1019 (irq->mpc_dstirq == i))
1020 break;
1021 }
1022
1023 if (idx != mp_irq_entries) {
1024 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1025 continue; /* IRQ already used */
1026 }
1027
1028 intsrc.mpc_irqtype = mp_INT;
1029 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1030 intsrc.mpc_dstirq = i;
1031
1032 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1033 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1034 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1035 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1036 intsrc.mpc_dstirq);
1037
1038 mp_irqs[mp_irq_entries] = intsrc;
1039 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1040 panic("Max # of irq sources exceeded!\n");
1041 }
1042}
1043
c434b7a6
NP		 1044#define MAX_GSI_NUM 4096
1045
19f03ffe 1046int mp_register_gsi(u32 gsi, int triggering, int polarity)
1da177e4 1047{
19f03ffe
AK		 1048 int ioapic = -1;
1049 int ioapic_pin = 0;
1050 int idx, bit = 0;
1051 static int pci_irq = 16;
c434b7a6
NP		 1052 /*
1053 * Mapping between Global System Interrups, which
1054 * represent all possible interrupts, and IRQs
1055 * assigned to actual devices.
1056 */
1057 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4 1058
1da177e4
LT		 1059 /* Don't set up the ACPI SCI because it's already set up */
1060 if (acpi_fadt.sci_int == gsi)
1061 return gsi;
1da177e4
LT		 1062
1063 ioapic = mp_find_ioapic(gsi);
1064 if (ioapic < 0) {
1065 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1066 return gsi;
1067 }
1068
1069 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1070
1071 if (ioapic_renumber_irq)
1072 gsi = ioapic_renumber_irq(ioapic, gsi);
1073
1074 /*
1075 * Avoid pin reprogramming. PRTs typically include entries
1076 * with redundant pin->gsi mappings (but unique PCI devices);
1077 * we only program the IOAPIC on the first.
1078 */
1079 bit = ioapic_pin % 32;
1080 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1081 if (idx > 3) {
1082 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1083 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1084 ioapic_pin);
1085 return gsi;
1086 }
1087 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1088 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1089 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
c434b7a6 1090 return gsi_to_irq[gsi];
1da177e4
LT		 1091 }
1092
1093 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1094
cb654695 1095 if (triggering == ACPI_LEVEL_SENSITIVE) {
c434b7a6
NP		 1096 /*
1097 * For PCI devices assign IRQs in order, avoiding gaps
1098 * due to unused I/O APIC pins.
1099 */
1100 int irq = gsi;
1101 if (gsi < MAX_GSI_NUM) {
e0c1e9bf
KM		 1102 /*
1103 * Retain the VIA chipset work-around (gsi > 15), but
1104 * avoid a problem where the 8254 timer (IRQ0) is setup
1105 * via an override (so it's not on pin 0 of the ioapic),
1106 * and at the same time, the pin 0 interrupt is a PCI
1107 * type. The gsi > 15 test could cause these two pins
1108 * to be shared as IRQ0, and they are not shareable.
1109 * So test for this condition, and if necessary, avoid
1110 * the pin collision.
1111 */
1112 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
e1afc3f5 1113 gsi = pci_irq++;
e1afc3f5
NP		 1114 /*
1115 * Don't assign IRQ used by ACPI SCI
1116 */
1117 if (gsi == acpi_fadt.sci_int)
1118 gsi = pci_irq++;
c434b7a6
NP		 1119 gsi_to_irq[irq] = gsi;
1120 } else {
1121 printk(KERN_ERR "GSI %u is too high\n", gsi);
1122 return gsi;
1123 }
1124 }
1125
1da177e4 1126 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
cb654695
LB		 1127 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1128 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1da177e4
LT		 1129 return gsi;
1130}
1131
8466361a 1132#endif /* CONFIG_X86_IO_APIC */
888ba6c6 1133#endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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