Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/i386/nmi.c | |
3 | * | |
4 | * NMI watchdog support on APIC systems | |
5 | * | |
6 | * Started by Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes: | |
9 | * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog. | |
10 | * Mikael Pettersson : Power Management for local APIC NMI watchdog. | |
11 | * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog. | |
12 | * Pavel Machek and | |
13 | * Mikael Pettersson : PM converted to driver model. Disable/enable API. | |
14 | */ | |
15 | ||
16 | #include <linux/config.h> | |
1da177e4 | 17 | #include <linux/delay.h> |
1da177e4 | 18 | #include <linux/interrupt.h> |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/nmi.h> | |
21 | #include <linux/sysdev.h> | |
22 | #include <linux/sysctl.h> | |
3e4ff115 | 23 | #include <linux/percpu.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
1da177e4 LT |
26 | #include <asm/nmi.h> |
27 | ||
28 | #include "mach_traps.h" | |
29 | ||
30 | unsigned int nmi_watchdog = NMI_NONE; | |
31 | extern int unknown_nmi_panic; | |
32 | static unsigned int nmi_hz = HZ; | |
33 | static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */ | |
34 | static unsigned int nmi_p4_cccr_val; | |
35 | extern void show_registers(struct pt_regs *regs); | |
36 | ||
37 | /* | |
38 | * lapic_nmi_owner tracks the ownership of the lapic NMI hardware: | |
39 | * - it may be reserved by some other driver, or not | |
40 | * - when not reserved by some other driver, it may be used for | |
41 | * the NMI watchdog, or not | |
42 | * | |
43 | * This is maintained separately from nmi_active because the NMI | |
44 | * watchdog may also be driven from the I/O APIC timer. | |
45 | */ | |
46 | static DEFINE_SPINLOCK(lapic_nmi_owner_lock); | |
47 | static unsigned int lapic_nmi_owner; | |
48 | #define LAPIC_NMI_WATCHDOG (1<<0) | |
49 | #define LAPIC_NMI_RESERVED (1<<1) | |
50 | ||
51 | /* nmi_active: | |
52 | * +1: the lapic NMI watchdog is active, but can be disabled | |
53 | * 0: the lapic NMI watchdog has not been set up, and cannot | |
54 | * be enabled | |
55 | * -1: the lapic NMI watchdog is disabled, but can be enabled | |
56 | */ | |
57 | int nmi_active; | |
58 | ||
59 | #define K7_EVNTSEL_ENABLE (1 << 22) | |
60 | #define K7_EVNTSEL_INT (1 << 20) | |
61 | #define K7_EVNTSEL_OS (1 << 17) | |
62 | #define K7_EVNTSEL_USR (1 << 16) | |
63 | #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76 | |
64 | #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING | |
65 | ||
66 | #define P6_EVNTSEL0_ENABLE (1 << 22) | |
67 | #define P6_EVNTSEL_INT (1 << 20) | |
68 | #define P6_EVNTSEL_OS (1 << 17) | |
69 | #define P6_EVNTSEL_USR (1 << 16) | |
70 | #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79 | |
71 | #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED | |
72 | ||
73 | #define MSR_P4_MISC_ENABLE 0x1A0 | |
74 | #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7) | |
75 | #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12) | |
76 | #define MSR_P4_PERFCTR0 0x300 | |
77 | #define MSR_P4_CCCR0 0x360 | |
78 | #define P4_ESCR_EVENT_SELECT(N) ((N)<<25) | |
79 | #define P4_ESCR_OS (1<<3) | |
80 | #define P4_ESCR_USR (1<<2) | |
81 | #define P4_CCCR_OVF_PMI0 (1<<26) | |
82 | #define P4_CCCR_OVF_PMI1 (1<<27) | |
83 | #define P4_CCCR_THRESHOLD(N) ((N)<<20) | |
84 | #define P4_CCCR_COMPLEMENT (1<<19) | |
85 | #define P4_CCCR_COMPARE (1<<18) | |
86 | #define P4_CCCR_REQUIRED (3<<16) | |
87 | #define P4_CCCR_ESCR_SELECT(N) ((N)<<13) | |
88 | #define P4_CCCR_ENABLE (1<<12) | |
89 | /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter | |
90 | CRU_ESCR0 (with any non-null event selector) through a complemented | |
91 | max threshold. [IA32-Vol3, Section 14.9.9] */ | |
92 | #define MSR_P4_IQ_COUNTER0 0x30C | |
93 | #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR) | |
94 | #define P4_NMI_IQ_CCCR0 \ | |
95 | (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \ | |
96 | P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE) | |
97 | ||
29b70081 EB |
98 | #ifdef CONFIG_SMP |
99 | /* The performance counters used by NMI_LOCAL_APIC don't trigger when | |
100 | * the CPU is idle. To make sure the NMI watchdog really ticks on all | |
101 | * CPUs during the test make them busy. | |
102 | */ | |
103 | static __init void nmi_cpu_busy(void *data) | |
104 | { | |
105 | volatile int *endflag = data; | |
106 | local_irq_enable(); | |
107 | /* Intentionally don't use cpu_relax here. This is | |
108 | to make sure that the performance counter really ticks, | |
109 | even if there is a simulator or similar that catches the | |
110 | pause instruction. On a real HT machine this is fine because | |
111 | all other CPUs are busy with "useless" delay loops and don't | |
112 | care if they get somewhat less cycles. */ | |
113 | while (*endflag == 0) | |
114 | barrier(); | |
115 | } | |
116 | #endif | |
117 | ||
67701ae9 | 118 | static int __init check_nmi_watchdog(void) |
1da177e4 | 119 | { |
29b70081 EB |
120 | volatile int endflag = 0; |
121 | unsigned int *prev_nmi_count; | |
1da177e4 LT |
122 | int cpu; |
123 | ||
67701ae9 JV |
124 | if (nmi_watchdog == NMI_NONE) |
125 | return 0; | |
126 | ||
29b70081 EB |
127 | prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL); |
128 | if (!prev_nmi_count) | |
129 | return -1; | |
130 | ||
67701ae9 | 131 | printk(KERN_INFO "Testing NMI watchdog ... "); |
1da177e4 | 132 | |
29b70081 EB |
133 | if (nmi_watchdog == NMI_LOCAL_APIC) |
134 | smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0); | |
135 | ||
c8912599 | 136 | for_each_possible_cpu(cpu) |
1da177e4 LT |
137 | prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count; |
138 | local_irq_enable(); | |
139 | mdelay((10*1000)/nmi_hz); // wait 10 ticks | |
140 | ||
c8912599 | 141 | for_each_possible_cpu(cpu) { |
1da177e4 LT |
142 | #ifdef CONFIG_SMP |
143 | /* Check cpu_callin_map here because that is set | |
144 | after the timer is started. */ | |
145 | if (!cpu_isset(cpu, cpu_callin_map)) | |
146 | continue; | |
147 | #endif | |
148 | if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) { | |
29b70081 EB |
149 | endflag = 1; |
150 | printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n", | |
151 | cpu, | |
152 | prev_nmi_count[cpu], | |
153 | nmi_count(cpu)); | |
1da177e4 LT |
154 | nmi_active = 0; |
155 | lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG; | |
29b70081 | 156 | kfree(prev_nmi_count); |
1da177e4 LT |
157 | return -1; |
158 | } | |
159 | } | |
29b70081 | 160 | endflag = 1; |
1da177e4 LT |
161 | printk("OK.\n"); |
162 | ||
163 | /* now that we know it works we can reduce NMI frequency to | |
164 | something more reasonable; makes a difference in some configs */ | |
165 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
166 | nmi_hz = 1; | |
167 | ||
29b70081 | 168 | kfree(prev_nmi_count); |
1da177e4 LT |
169 | return 0; |
170 | } | |
67701ae9 JV |
171 | /* This needs to happen later in boot so counters are working */ |
172 | late_initcall(check_nmi_watchdog); | |
1da177e4 LT |
173 | |
174 | static int __init setup_nmi_watchdog(char *str) | |
175 | { | |
176 | int nmi; | |
177 | ||
178 | get_option(&str, &nmi); | |
179 | ||
180 | if (nmi >= NMI_INVALID) | |
181 | return 0; | |
182 | if (nmi == NMI_NONE) | |
183 | nmi_watchdog = nmi; | |
184 | /* | |
185 | * If any other x86 CPU has a local APIC, then | |
186 | * please test the NMI stuff there and send me the | |
187 | * missing bits. Right now Intel P6/P4 and AMD K7 only. | |
188 | */ | |
189 | if ((nmi == NMI_LOCAL_APIC) && | |
190 | (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
191 | (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15)) | |
192 | nmi_watchdog = nmi; | |
193 | if ((nmi == NMI_LOCAL_APIC) && | |
194 | (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && | |
195 | (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15)) | |
196 | nmi_watchdog = nmi; | |
197 | /* | |
198 | * We can enable the IO-APIC watchdog | |
199 | * unconditionally. | |
200 | */ | |
201 | if (nmi == NMI_IO_APIC) { | |
202 | nmi_active = 1; | |
203 | nmi_watchdog = nmi; | |
204 | } | |
205 | return 1; | |
206 | } | |
207 | ||
208 | __setup("nmi_watchdog=", setup_nmi_watchdog); | |
209 | ||
210 | static void disable_lapic_nmi_watchdog(void) | |
211 | { | |
212 | if (nmi_active <= 0) | |
213 | return; | |
214 | switch (boot_cpu_data.x86_vendor) { | |
215 | case X86_VENDOR_AMD: | |
216 | wrmsr(MSR_K7_EVNTSEL0, 0, 0); | |
217 | break; | |
218 | case X86_VENDOR_INTEL: | |
219 | switch (boot_cpu_data.x86) { | |
220 | case 6: | |
221 | if (boot_cpu_data.x86_model > 0xd) | |
222 | break; | |
223 | ||
224 | wrmsr(MSR_P6_EVNTSEL0, 0, 0); | |
225 | break; | |
226 | case 15: | |
cd3716ab | 227 | if (boot_cpu_data.x86_model > 0x4) |
1da177e4 LT |
228 | break; |
229 | ||
230 | wrmsr(MSR_P4_IQ_CCCR0, 0, 0); | |
231 | wrmsr(MSR_P4_CRU_ESCR0, 0, 0); | |
232 | break; | |
233 | } | |
234 | break; | |
235 | } | |
236 | nmi_active = -1; | |
237 | /* tell do_nmi() and others that we're not active any more */ | |
238 | nmi_watchdog = 0; | |
239 | } | |
240 | ||
241 | static void enable_lapic_nmi_watchdog(void) | |
242 | { | |
243 | if (nmi_active < 0) { | |
244 | nmi_watchdog = NMI_LOCAL_APIC; | |
245 | setup_apic_nmi_watchdog(); | |
246 | } | |
247 | } | |
248 | ||
249 | int reserve_lapic_nmi(void) | |
250 | { | |
251 | unsigned int old_owner; | |
252 | ||
253 | spin_lock(&lapic_nmi_owner_lock); | |
254 | old_owner = lapic_nmi_owner; | |
255 | lapic_nmi_owner |= LAPIC_NMI_RESERVED; | |
256 | spin_unlock(&lapic_nmi_owner_lock); | |
257 | if (old_owner & LAPIC_NMI_RESERVED) | |
258 | return -EBUSY; | |
259 | if (old_owner & LAPIC_NMI_WATCHDOG) | |
260 | disable_lapic_nmi_watchdog(); | |
261 | return 0; | |
262 | } | |
263 | ||
264 | void release_lapic_nmi(void) | |
265 | { | |
266 | unsigned int new_owner; | |
267 | ||
268 | spin_lock(&lapic_nmi_owner_lock); | |
269 | new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED; | |
270 | lapic_nmi_owner = new_owner; | |
271 | spin_unlock(&lapic_nmi_owner_lock); | |
272 | if (new_owner & LAPIC_NMI_WATCHDOG) | |
273 | enable_lapic_nmi_watchdog(); | |
274 | } | |
275 | ||
276 | void disable_timer_nmi_watchdog(void) | |
277 | { | |
278 | if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0)) | |
279 | return; | |
280 | ||
281 | unset_nmi_callback(); | |
282 | nmi_active = -1; | |
283 | nmi_watchdog = NMI_NONE; | |
284 | } | |
285 | ||
286 | void enable_timer_nmi_watchdog(void) | |
287 | { | |
288 | if (nmi_active < 0) { | |
289 | nmi_watchdog = NMI_IO_APIC; | |
290 | touch_nmi_watchdog(); | |
291 | nmi_active = 1; | |
292 | } | |
293 | } | |
294 | ||
295 | #ifdef CONFIG_PM | |
296 | ||
297 | static int nmi_pm_active; /* nmi_active before suspend */ | |
298 | ||
438510f6 | 299 | static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
300 | { |
301 | nmi_pm_active = nmi_active; | |
302 | disable_lapic_nmi_watchdog(); | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static int lapic_nmi_resume(struct sys_device *dev) | |
307 | { | |
308 | if (nmi_pm_active > 0) | |
309 | enable_lapic_nmi_watchdog(); | |
310 | return 0; | |
311 | } | |
312 | ||
313 | ||
314 | static struct sysdev_class nmi_sysclass = { | |
315 | set_kset_name("lapic_nmi"), | |
316 | .resume = lapic_nmi_resume, | |
317 | .suspend = lapic_nmi_suspend, | |
318 | }; | |
319 | ||
320 | static struct sys_device device_lapic_nmi = { | |
321 | .id = 0, | |
322 | .cls = &nmi_sysclass, | |
323 | }; | |
324 | ||
325 | static int __init init_lapic_nmi_sysfs(void) | |
326 | { | |
327 | int error; | |
328 | ||
329 | if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC) | |
330 | return 0; | |
331 | ||
332 | error = sysdev_class_register(&nmi_sysclass); | |
333 | if (!error) | |
334 | error = sysdev_register(&device_lapic_nmi); | |
335 | return error; | |
336 | } | |
337 | /* must come after the local APIC's device_initcall() */ | |
338 | late_initcall(init_lapic_nmi_sysfs); | |
339 | ||
340 | #endif /* CONFIG_PM */ | |
341 | ||
342 | /* | |
343 | * Activate the NMI watchdog via the local APIC. | |
344 | * Original code written by Keith Owens. | |
345 | */ | |
346 | ||
347 | static void clear_msr_range(unsigned int base, unsigned int n) | |
348 | { | |
349 | unsigned int i; | |
350 | ||
351 | for(i = 0; i < n; ++i) | |
352 | wrmsr(base+i, 0, 0); | |
353 | } | |
354 | ||
b884e257 | 355 | static void write_watchdog_counter(const char *descr) |
7fbb4f6e JB |
356 | { |
357 | u64 count = (u64)cpu_khz * 1000; | |
358 | ||
359 | do_div(count, nmi_hz); | |
360 | if(descr) | |
361 | Dprintk("setting %s to -0x%08Lx\n", descr, count); | |
362 | wrmsrl(nmi_perfctr_msr, 0 - count); | |
363 | } | |
364 | ||
1da177e4 LT |
365 | static void setup_k7_watchdog(void) |
366 | { | |
367 | unsigned int evntsel; | |
368 | ||
369 | nmi_perfctr_msr = MSR_K7_PERFCTR0; | |
370 | ||
371 | clear_msr_range(MSR_K7_EVNTSEL0, 4); | |
372 | clear_msr_range(MSR_K7_PERFCTR0, 4); | |
373 | ||
374 | evntsel = K7_EVNTSEL_INT | |
375 | | K7_EVNTSEL_OS | |
376 | | K7_EVNTSEL_USR | |
377 | | K7_NMI_EVENT; | |
378 | ||
379 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); | |
7fbb4f6e | 380 | write_watchdog_counter("K7_PERFCTR0"); |
1da177e4 LT |
381 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
382 | evntsel |= K7_EVNTSEL_ENABLE; | |
383 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); | |
384 | } | |
385 | ||
386 | static void setup_p6_watchdog(void) | |
387 | { | |
388 | unsigned int evntsel; | |
389 | ||
390 | nmi_perfctr_msr = MSR_P6_PERFCTR0; | |
391 | ||
392 | clear_msr_range(MSR_P6_EVNTSEL0, 2); | |
393 | clear_msr_range(MSR_P6_PERFCTR0, 2); | |
394 | ||
395 | evntsel = P6_EVNTSEL_INT | |
396 | | P6_EVNTSEL_OS | |
397 | | P6_EVNTSEL_USR | |
398 | | P6_NMI_EVENT; | |
399 | ||
400 | wrmsr(MSR_P6_EVNTSEL0, evntsel, 0); | |
7fbb4f6e | 401 | write_watchdog_counter("P6_PERFCTR0"); |
1da177e4 LT |
402 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
403 | evntsel |= P6_EVNTSEL0_ENABLE; | |
404 | wrmsr(MSR_P6_EVNTSEL0, evntsel, 0); | |
405 | } | |
406 | ||
407 | static int setup_p4_watchdog(void) | |
408 | { | |
409 | unsigned int misc_enable, dummy; | |
410 | ||
411 | rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy); | |
412 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL)) | |
413 | return 0; | |
414 | ||
415 | nmi_perfctr_msr = MSR_P4_IQ_COUNTER0; | |
416 | nmi_p4_cccr_val = P4_NMI_IQ_CCCR0; | |
417 | #ifdef CONFIG_SMP | |
418 | if (smp_num_siblings == 2) | |
419 | nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1; | |
420 | #endif | |
421 | ||
422 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL)) | |
423 | clear_msr_range(0x3F1, 2); | |
424 | /* MSR 0x3F0 seems to have a default value of 0xFC00, but current | |
425 | docs doesn't fully define it, so leave it alone for now. */ | |
426 | if (boot_cpu_data.x86_model >= 0x3) { | |
427 | /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */ | |
428 | clear_msr_range(0x3A0, 26); | |
429 | clear_msr_range(0x3BC, 3); | |
430 | } else { | |
431 | clear_msr_range(0x3A0, 31); | |
432 | } | |
433 | clear_msr_range(0x3C0, 6); | |
434 | clear_msr_range(0x3C8, 6); | |
435 | clear_msr_range(0x3E0, 2); | |
436 | clear_msr_range(MSR_P4_CCCR0, 18); | |
437 | clear_msr_range(MSR_P4_PERFCTR0, 18); | |
438 | ||
439 | wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); | |
440 | wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); | |
7fbb4f6e | 441 | write_watchdog_counter("P4_IQ_COUNTER0"); |
1da177e4 LT |
442 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
443 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); | |
444 | return 1; | |
445 | } | |
446 | ||
447 | void setup_apic_nmi_watchdog (void) | |
448 | { | |
449 | switch (boot_cpu_data.x86_vendor) { | |
450 | case X86_VENDOR_AMD: | |
451 | if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15) | |
452 | return; | |
453 | setup_k7_watchdog(); | |
454 | break; | |
455 | case X86_VENDOR_INTEL: | |
456 | switch (boot_cpu_data.x86) { | |
457 | case 6: | |
458 | if (boot_cpu_data.x86_model > 0xd) | |
459 | return; | |
460 | ||
461 | setup_p6_watchdog(); | |
462 | break; | |
463 | case 15: | |
cd3716ab | 464 | if (boot_cpu_data.x86_model > 0x4) |
1da177e4 LT |
465 | return; |
466 | ||
467 | if (!setup_p4_watchdog()) | |
468 | return; | |
469 | break; | |
470 | default: | |
471 | return; | |
472 | } | |
473 | break; | |
474 | default: | |
475 | return; | |
476 | } | |
477 | lapic_nmi_owner = LAPIC_NMI_WATCHDOG; | |
478 | nmi_active = 1; | |
479 | } | |
480 | ||
481 | /* | |
482 | * the best way to detect whether a CPU has a 'hard lockup' problem | |
483 | * is to check it's local APIC timer IRQ counts. If they are not | |
484 | * changing then that CPU has some problem. | |
485 | * | |
486 | * as these watchdog NMI IRQs are generated on every CPU, we only | |
487 | * have to check the current processor. | |
488 | * | |
489 | * since NMIs don't listen to _any_ locks, we have to be extremely | |
490 | * careful not to rely on unsafe variables. The printk might lock | |
491 | * up though, so we have to break up any console locks first ... | |
492 | * [when there will be more tty-related locks, break them up | |
493 | * here too!] | |
494 | */ | |
495 | ||
496 | static unsigned int | |
497 | last_irq_sums [NR_CPUS], | |
498 | alert_counter [NR_CPUS]; | |
499 | ||
500 | void touch_nmi_watchdog (void) | |
501 | { | |
502 | int i; | |
503 | ||
504 | /* | |
505 | * Just reset the alert counters, (other CPUs might be | |
506 | * spinning on locks we hold): | |
507 | */ | |
c8912599 | 508 | for_each_possible_cpu(i) |
1da177e4 | 509 | alert_counter[i] = 0; |
8446f1d3 IM |
510 | |
511 | /* | |
512 | * Tickle the softlockup detector too: | |
513 | */ | |
514 | touch_softlockup_watchdog(); | |
1da177e4 LT |
515 | } |
516 | ||
517 | extern void die_nmi(struct pt_regs *, const char *msg); | |
518 | ||
519 | void nmi_watchdog_tick (struct pt_regs * regs) | |
520 | { | |
521 | ||
522 | /* | |
523 | * Since current_thread_info()-> is always on the stack, and we | |
524 | * always switch the stack NMI-atomically, it's safe to use | |
525 | * smp_processor_id(). | |
526 | */ | |
b791ccef JJ |
527 | unsigned int sum; |
528 | int cpu = smp_processor_id(); | |
1da177e4 LT |
529 | |
530 | sum = per_cpu(irq_stat, cpu).apic_timer_irqs; | |
531 | ||
532 | if (last_irq_sums[cpu] == sum) { | |
533 | /* | |
534 | * Ayiee, looks like this CPU is stuck ... | |
535 | * wait a few IRQs (5 seconds) before doing the oops ... | |
536 | */ | |
537 | alert_counter[cpu]++; | |
538 | if (alert_counter[cpu] == 5*nmi_hz) | |
748f2edb GA |
539 | /* |
540 | * die_nmi will return ONLY if NOTIFY_STOP happens.. | |
541 | */ | |
91368d73 | 542 | die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP"); |
b884e257 | 543 | } else { |
1da177e4 LT |
544 | last_irq_sums[cpu] = sum; |
545 | alert_counter[cpu] = 0; | |
546 | } | |
547 | if (nmi_perfctr_msr) { | |
548 | if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) { | |
549 | /* | |
550 | * P4 quirks: | |
551 | * - An overflown perfctr will assert its interrupt | |
552 | * until the OVF flag in its CCCR is cleared. | |
553 | * - LVTPC is masked on interrupt and must be | |
554 | * unmasked by the LVTPC handler. | |
555 | */ | |
556 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); | |
557 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
558 | } | |
559 | else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) { | |
560 | /* Only P6 based Pentium M need to re-unmask | |
561 | * the apic vector but it doesn't hurt | |
562 | * other P6 variant */ | |
563 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
564 | } | |
7fbb4f6e | 565 | write_watchdog_counter(NULL); |
1da177e4 LT |
566 | } |
567 | } | |
568 | ||
569 | #ifdef CONFIG_SYSCTL | |
570 | ||
571 | static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu) | |
572 | { | |
573 | unsigned char reason = get_nmi_reason(); | |
574 | char buf[64]; | |
575 | ||
576 | if (!(reason & 0xc0)) { | |
577 | sprintf(buf, "NMI received for unknown reason %02x\n", reason); | |
578 | die_nmi(regs, buf); | |
579 | } | |
580 | return 0; | |
581 | } | |
582 | ||
583 | /* | |
584 | * proc handler for /proc/sys/kernel/unknown_nmi_panic | |
585 | */ | |
586 | int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file, | |
587 | void __user *buffer, size_t *length, loff_t *ppos) | |
588 | { | |
589 | int old_state; | |
590 | ||
591 | old_state = unknown_nmi_panic; | |
592 | proc_dointvec(table, write, file, buffer, length, ppos); | |
593 | if (!!old_state == !!unknown_nmi_panic) | |
594 | return 0; | |
595 | ||
596 | if (unknown_nmi_panic) { | |
597 | if (reserve_lapic_nmi() < 0) { | |
598 | unknown_nmi_panic = 0; | |
599 | return -EBUSY; | |
600 | } else { | |
601 | set_nmi_callback(unknown_nmi_panic_callback); | |
602 | } | |
603 | } else { | |
604 | release_lapic_nmi(); | |
605 | unset_nmi_callback(); | |
606 | } | |
607 | return 0; | |
608 | } | |
609 | ||
610 | #endif | |
611 | ||
612 | EXPORT_SYMBOL(nmi_active); | |
613 | EXPORT_SYMBOL(nmi_watchdog); | |
614 | EXPORT_SYMBOL(reserve_lapic_nmi); | |
615 | EXPORT_SYMBOL(release_lapic_nmi); | |
616 | EXPORT_SYMBOL(disable_timer_nmi_watchdog); | |
617 | EXPORT_SYMBOL(enable_timer_nmi_watchdog); |