Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/config.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/kernel.h> | |
40 | ||
41 | #include <linux/mm.h> | |
42 | #include <linux/sched.h> | |
43 | #include <linux/kernel_stat.h> | |
44 | #include <linux/smp_lock.h> | |
1da177e4 | 45 | #include <linux/bootmem.h> |
f3705136 ZM |
46 | #include <linux/notifier.h> |
47 | #include <linux/cpu.h> | |
48 | #include <linux/percpu.h> | |
1da177e4 LT |
49 | |
50 | #include <linux/delay.h> | |
51 | #include <linux/mc146818rtc.h> | |
52 | #include <asm/tlbflush.h> | |
53 | #include <asm/desc.h> | |
54 | #include <asm/arch_hooks.h> | |
55 | ||
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
59 | ||
60 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 61 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
129f6946 AD |
65 | #ifdef CONFIG_X86_HT |
66 | EXPORT_SYMBOL(smp_num_siblings); | |
67 | #endif | |
d720803a LS |
68 | |
69 | /* Package ID of each logical CPU */ | |
6c036527 | 70 | int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID}; |
d720803a LS |
71 | |
72 | /* Core ID of each logical CPU */ | |
6c036527 | 73 | int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID}; |
1da177e4 | 74 | |
94605eff | 75 | /* representing HT siblings of each logical CPU */ |
6c036527 | 76 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
77 | EXPORT_SYMBOL(cpu_sibling_map); |
78 | ||
94605eff | 79 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 80 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
81 | EXPORT_SYMBOL(cpu_core_map); |
82 | ||
1da177e4 | 83 | /* bitmap of online cpus */ |
6c036527 | 84 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 85 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
86 | |
87 | cpumask_t cpu_callin_map; | |
88 | cpumask_t cpu_callout_map; | |
129f6946 | 89 | EXPORT_SYMBOL(cpu_callout_map); |
9f40a72a NP |
90 | #ifdef CONFIG_HOTPLUG_CPU |
91 | cpumask_t cpu_possible_map = CPU_MASK_ALL; | |
92 | #else | |
4ad8d383 | 93 | cpumask_t cpu_possible_map; |
9f40a72a | 94 | #endif |
4ad8d383 | 95 | EXPORT_SYMBOL(cpu_possible_map); |
1da177e4 LT |
96 | static cpumask_t smp_commenced_mask; |
97 | ||
e1367daf LS |
98 | /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there |
99 | * is no way to resync one AP against BP. TBD: for prescott and above, we | |
100 | * should use IA64's algorithm | |
101 | */ | |
102 | static int __devinitdata tsc_sync_disabled; | |
103 | ||
1da177e4 LT |
104 | /* Per CPU bogomips and other parameters */ |
105 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 106 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 107 | |
6c036527 | 108 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
109 | { [0 ... NR_CPUS-1] = 0xff }; |
110 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
111 | ||
112 | /* | |
113 | * Trampoline 80x86 program as an array. | |
114 | */ | |
115 | ||
116 | extern unsigned char trampoline_data []; | |
117 | extern unsigned char trampoline_end []; | |
118 | static unsigned char *trampoline_base; | |
119 | static int trampoline_exec; | |
120 | ||
121 | static void map_cpu_to_logical_apicid(void); | |
122 | ||
f3705136 ZM |
123 | /* State of each CPU. */ |
124 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
125 | ||
1da177e4 LT |
126 | /* |
127 | * Currently trivial. Write the real->protected mode | |
128 | * bootstrap into the page concerned. The caller | |
129 | * has made sure it's suitably aligned. | |
130 | */ | |
131 | ||
0bb3184d | 132 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
133 | { |
134 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
135 | return virt_to_phys(trampoline_base); | |
136 | } | |
137 | ||
138 | /* | |
139 | * We are called very early to get the low memory for the | |
140 | * SMP bootup trampoline page. | |
141 | */ | |
142 | void __init smp_alloc_memory(void) | |
143 | { | |
144 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
145 | /* | |
146 | * Has to be in very low memory so we can execute | |
147 | * real-mode AP code. | |
148 | */ | |
149 | if (__pa(trampoline_base) >= 0x9F000) | |
150 | BUG(); | |
151 | /* | |
152 | * Make the SMP trampoline executable: | |
153 | */ | |
154 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
155 | } | |
156 | ||
157 | /* | |
158 | * The bootstrap kernel entry code has set these up. Save them for | |
159 | * a given CPU | |
160 | */ | |
161 | ||
0bb3184d | 162 | static void __devinit smp_store_cpu_info(int id) |
1da177e4 LT |
163 | { |
164 | struct cpuinfo_x86 *c = cpu_data + id; | |
165 | ||
166 | *c = boot_cpu_data; | |
167 | if (id!=0) | |
168 | identify_cpu(c); | |
169 | /* | |
170 | * Mask B, Pentium, but not Pentium MMX | |
171 | */ | |
172 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
173 | c->x86 == 5 && | |
174 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
175 | c->x86_model <= 3) | |
176 | /* | |
177 | * Remember we have B step Pentia with bugs | |
178 | */ | |
179 | smp_b_stepping = 1; | |
180 | ||
181 | /* | |
182 | * Certain Athlons might work (for various values of 'work') in SMP | |
183 | * but they are not certified as MP capable. | |
184 | */ | |
185 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
186 | ||
187 | /* Athlon 660/661 is valid. */ | |
188 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
189 | goto valid_k7; | |
190 | ||
191 | /* Duron 670 is valid */ | |
192 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
193 | goto valid_k7; | |
194 | ||
195 | /* | |
196 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
197 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
198 | * have the MP bit set. | |
199 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
200 | */ | |
201 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
202 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
203 | (c->x86_model> 7)) | |
204 | if (cpu_has_mp) | |
205 | goto valid_k7; | |
206 | ||
207 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 208 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
209 | } |
210 | ||
211 | valid_k7: | |
212 | ; | |
213 | } | |
214 | ||
215 | /* | |
216 | * TSC synchronization. | |
217 | * | |
218 | * We first check whether all CPUs have their TSC's synchronized, | |
219 | * then we print a warning if not, and always resync. | |
220 | */ | |
221 | ||
222 | static atomic_t tsc_start_flag = ATOMIC_INIT(0); | |
223 | static atomic_t tsc_count_start = ATOMIC_INIT(0); | |
224 | static atomic_t tsc_count_stop = ATOMIC_INIT(0); | |
225 | static unsigned long long tsc_values[NR_CPUS]; | |
226 | ||
227 | #define NR_LOOPS 5 | |
228 | ||
229 | static void __init synchronize_tsc_bp (void) | |
230 | { | |
231 | int i; | |
232 | unsigned long long t0; | |
233 | unsigned long long sum, avg; | |
234 | long long delta; | |
a3a255e7 | 235 | unsigned int one_usec; |
1da177e4 LT |
236 | int buggy = 0; |
237 | ||
238 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
239 | ||
240 | /* convert from kcyc/sec to cyc/usec */ | |
241 | one_usec = cpu_khz / 1000; | |
242 | ||
243 | atomic_set(&tsc_start_flag, 1); | |
244 | wmb(); | |
245 | ||
246 | /* | |
247 | * We loop a few times to get a primed instruction cache, | |
248 | * then the last pass is more or less synchronized and | |
249 | * the BP and APs set their cycle counters to zero all at | |
250 | * once. This reduces the chance of having random offsets | |
251 | * between the processors, and guarantees that the maximum | |
252 | * delay between the cycle counters is never bigger than | |
253 | * the latency of information-passing (cachelines) between | |
254 | * two CPUs. | |
255 | */ | |
256 | for (i = 0; i < NR_LOOPS; i++) { | |
257 | /* | |
258 | * all APs synchronize but they loop on '== num_cpus' | |
259 | */ | |
260 | while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) | |
261 | mb(); | |
262 | atomic_set(&tsc_count_stop, 0); | |
263 | wmb(); | |
264 | /* | |
265 | * this lets the APs save their current TSC: | |
266 | */ | |
267 | atomic_inc(&tsc_count_start); | |
268 | ||
269 | rdtscll(tsc_values[smp_processor_id()]); | |
270 | /* | |
271 | * We clear the TSC in the last loop: | |
272 | */ | |
273 | if (i == NR_LOOPS-1) | |
274 | write_tsc(0, 0); | |
275 | ||
276 | /* | |
277 | * Wait for all APs to leave the synchronization point: | |
278 | */ | |
279 | while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) | |
280 | mb(); | |
281 | atomic_set(&tsc_count_start, 0); | |
282 | wmb(); | |
283 | atomic_inc(&tsc_count_stop); | |
284 | } | |
285 | ||
286 | sum = 0; | |
287 | for (i = 0; i < NR_CPUS; i++) { | |
288 | if (cpu_isset(i, cpu_callout_map)) { | |
289 | t0 = tsc_values[i]; | |
290 | sum += t0; | |
291 | } | |
292 | } | |
293 | avg = sum; | |
294 | do_div(avg, num_booting_cpus()); | |
295 | ||
296 | sum = 0; | |
297 | for (i = 0; i < NR_CPUS; i++) { | |
298 | if (!cpu_isset(i, cpu_callout_map)) | |
299 | continue; | |
300 | delta = tsc_values[i] - avg; | |
301 | if (delta < 0) | |
302 | delta = -delta; | |
303 | /* | |
304 | * We report bigger than 2 microseconds clock differences. | |
305 | */ | |
306 | if (delta > 2*one_usec) { | |
307 | long realdelta; | |
308 | if (!buggy) { | |
309 | buggy = 1; | |
310 | printk("\n"); | |
311 | } | |
312 | realdelta = delta; | |
313 | do_div(realdelta, one_usec); | |
314 | if (tsc_values[i] < avg) | |
315 | realdelta = -realdelta; | |
316 | ||
317 | printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta); | |
318 | } | |
319 | ||
320 | sum += delta; | |
321 | } | |
322 | if (!buggy) | |
323 | printk("passed.\n"); | |
324 | } | |
325 | ||
326 | static void __init synchronize_tsc_ap (void) | |
327 | { | |
328 | int i; | |
329 | ||
330 | /* | |
331 | * Not every cpu is online at the time | |
332 | * this gets called, so we first wait for the BP to | |
333 | * finish SMP initialization: | |
334 | */ | |
335 | while (!atomic_read(&tsc_start_flag)) mb(); | |
336 | ||
337 | for (i = 0; i < NR_LOOPS; i++) { | |
338 | atomic_inc(&tsc_count_start); | |
339 | while (atomic_read(&tsc_count_start) != num_booting_cpus()) | |
340 | mb(); | |
341 | ||
342 | rdtscll(tsc_values[smp_processor_id()]); | |
343 | if (i == NR_LOOPS-1) | |
344 | write_tsc(0, 0); | |
345 | ||
346 | atomic_inc(&tsc_count_stop); | |
347 | while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb(); | |
348 | } | |
349 | } | |
350 | #undef NR_LOOPS | |
351 | ||
352 | extern void calibrate_delay(void); | |
353 | ||
354 | static atomic_t init_deasserted; | |
355 | ||
0bb3184d | 356 | static void __devinit smp_callin(void) |
1da177e4 LT |
357 | { |
358 | int cpuid, phys_id; | |
359 | unsigned long timeout; | |
360 | ||
361 | /* | |
362 | * If waken up by an INIT in an 82489DX configuration | |
363 | * we may get here before an INIT-deassert IPI reaches | |
364 | * our local APIC. We have to wait for the IPI or we'll | |
365 | * lock up on an APIC access. | |
366 | */ | |
367 | wait_for_init_deassert(&init_deasserted); | |
368 | ||
369 | /* | |
370 | * (This works even if the APIC is not enabled.) | |
371 | */ | |
372 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
373 | cpuid = smp_processor_id(); | |
374 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
375 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
376 | phys_id, cpuid); | |
377 | BUG(); | |
378 | } | |
379 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
380 | ||
381 | /* | |
382 | * STARTUP IPIs are fragile beasts as they might sometimes | |
383 | * trigger some glue motherboard logic. Complete APIC bus | |
384 | * silence for 1 second, this overestimates the time the | |
385 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
386 | * by a factor of two. This should be enough. | |
387 | */ | |
388 | ||
389 | /* | |
390 | * Waiting 2s total for startup (udelay is not yet working) | |
391 | */ | |
392 | timeout = jiffies + 2*HZ; | |
393 | while (time_before(jiffies, timeout)) { | |
394 | /* | |
395 | * Has the boot CPU finished it's STARTUP sequence? | |
396 | */ | |
397 | if (cpu_isset(cpuid, cpu_callout_map)) | |
398 | break; | |
399 | rep_nop(); | |
400 | } | |
401 | ||
402 | if (!time_before(jiffies, timeout)) { | |
403 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
404 | cpuid); | |
405 | BUG(); | |
406 | } | |
407 | ||
408 | /* | |
409 | * the boot CPU has finished the init stage and is spinning | |
410 | * on callin_map until we finish. We are free to set up this | |
411 | * CPU, first the APIC. (this is probably redundant on most | |
412 | * boards) | |
413 | */ | |
414 | ||
415 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
416 | smp_callin_clear_local_apic(); | |
417 | setup_local_APIC(); | |
418 | map_cpu_to_logical_apicid(); | |
419 | ||
420 | /* | |
421 | * Get our bogomips. | |
422 | */ | |
423 | calibrate_delay(); | |
424 | Dprintk("Stack at about %p\n",&cpuid); | |
425 | ||
426 | /* | |
427 | * Save our processor parameters | |
428 | */ | |
429 | smp_store_cpu_info(cpuid); | |
430 | ||
431 | disable_APIC_timer(); | |
432 | ||
433 | /* | |
434 | * Allow the master to continue. | |
435 | */ | |
436 | cpu_set(cpuid, cpu_callin_map); | |
437 | ||
438 | /* | |
439 | * Synchronize the TSC with the BP | |
440 | */ | |
e1367daf | 441 | if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) |
1da177e4 LT |
442 | synchronize_tsc_ap(); |
443 | } | |
444 | ||
445 | static int cpucount; | |
446 | ||
94605eff SS |
447 | /* representing cpus for which sibling maps can be computed */ |
448 | static cpumask_t cpu_sibling_setup_map; | |
449 | ||
d720803a LS |
450 | static inline void |
451 | set_cpu_sibling_map(int cpu) | |
452 | { | |
453 | int i; | |
94605eff SS |
454 | struct cpuinfo_x86 *c = cpu_data; |
455 | ||
456 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
457 | |
458 | if (smp_num_siblings > 1) { | |
94605eff SS |
459 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
460 | if (phys_proc_id[cpu] == phys_proc_id[i] && | |
461 | cpu_core_id[cpu] == cpu_core_id[i]) { | |
d720803a LS |
462 | cpu_set(i, cpu_sibling_map[cpu]); |
463 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
464 | cpu_set(i, cpu_core_map[cpu]); |
465 | cpu_set(cpu, cpu_core_map[i]); | |
d720803a LS |
466 | } |
467 | } | |
468 | } else { | |
469 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
470 | } | |
471 | ||
94605eff | 472 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 473 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
474 | c[cpu].booted_cores = 1; |
475 | return; | |
476 | } | |
477 | ||
478 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
479 | if (phys_proc_id[cpu] == phys_proc_id[i]) { | |
480 | cpu_set(i, cpu_core_map[cpu]); | |
481 | cpu_set(cpu, cpu_core_map[i]); | |
482 | /* | |
483 | * Does this new cpu bringup a new core? | |
484 | */ | |
485 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
486 | /* | |
487 | * for each core in package, increment | |
488 | * the booted_cores for this new cpu | |
489 | */ | |
490 | if (first_cpu(cpu_sibling_map[i]) == i) | |
491 | c[cpu].booted_cores++; | |
492 | /* | |
493 | * increment the core count for all | |
494 | * the other cpus in this package | |
495 | */ | |
496 | if (i != cpu) | |
497 | c[i].booted_cores++; | |
498 | } else if (i != cpu && !c[cpu].booted_cores) | |
499 | c[cpu].booted_cores = c[i].booted_cores; | |
500 | } | |
d720803a LS |
501 | } |
502 | } | |
503 | ||
1da177e4 LT |
504 | /* |
505 | * Activate a secondary processor. | |
506 | */ | |
0bb3184d | 507 | static void __devinit start_secondary(void *unused) |
1da177e4 LT |
508 | { |
509 | /* | |
510 | * Dont put anything before smp_callin(), SMP | |
511 | * booting is too fragile that we want to limit the | |
512 | * things done here to the most necessary things. | |
513 | */ | |
514 | cpu_init(); | |
5bfb5d69 | 515 | preempt_disable(); |
1da177e4 LT |
516 | smp_callin(); |
517 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
518 | rep_nop(); | |
519 | setup_secondary_APIC_clock(); | |
520 | if (nmi_watchdog == NMI_IO_APIC) { | |
521 | disable_8259A_irq(0); | |
522 | enable_NMI_through_LVT0(NULL); | |
523 | enable_8259A_irq(0); | |
524 | } | |
525 | enable_APIC_timer(); | |
526 | /* | |
527 | * low-memory mappings have been cleared, flush them from | |
528 | * the local TLBs too. | |
529 | */ | |
530 | local_flush_tlb(); | |
6fe940d6 | 531 | |
d720803a LS |
532 | /* This must be done before setting cpu_online_map */ |
533 | set_cpu_sibling_map(raw_smp_processor_id()); | |
534 | wmb(); | |
535 | ||
6fe940d6 LS |
536 | /* |
537 | * We need to hold call_lock, so there is no inconsistency | |
538 | * between the time smp_call_function() determines number of | |
539 | * IPI receipients, and the time when the determination is made | |
540 | * for which cpus receive the IPI. Holding this | |
541 | * lock helps us to not include this cpu in a currently in progress | |
542 | * smp_call_function(). | |
543 | */ | |
544 | lock_ipi_call_lock(); | |
1da177e4 | 545 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 546 | unlock_ipi_call_lock(); |
e1367daf | 547 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
548 | |
549 | /* We can take interrupts now: we're officially "up". */ | |
550 | local_irq_enable(); | |
551 | ||
552 | wmb(); | |
553 | cpu_idle(); | |
554 | } | |
555 | ||
556 | /* | |
557 | * Everything has been set up for the secondary | |
558 | * CPUs - they just need to reload everything | |
559 | * from the task structure | |
560 | * This function must not return. | |
561 | */ | |
0bb3184d | 562 | void __devinit initialize_secondary(void) |
1da177e4 LT |
563 | { |
564 | /* | |
565 | * We don't actually need to load the full TSS, | |
566 | * basically just the stack pointer and the eip. | |
567 | */ | |
568 | ||
569 | asm volatile( | |
570 | "movl %0,%%esp\n\t" | |
571 | "jmp *%1" | |
572 | : | |
573 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
574 | } | |
575 | ||
576 | extern struct { | |
577 | void * esp; | |
578 | unsigned short ss; | |
579 | } stack_start; | |
580 | ||
581 | #ifdef CONFIG_NUMA | |
582 | ||
583 | /* which logical CPUs are on which nodes */ | |
6c036527 | 584 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 LT |
585 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
586 | /* which node each logical CPU is on */ | |
6c036527 | 587 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
588 | EXPORT_SYMBOL(cpu_2_node); |
589 | ||
590 | /* set up a mapping between cpu and node. */ | |
591 | static inline void map_cpu_to_node(int cpu, int node) | |
592 | { | |
593 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
594 | cpu_set(cpu, node_2_cpu_mask[node]); | |
595 | cpu_2_node[cpu] = node; | |
596 | } | |
597 | ||
598 | /* undo a mapping between cpu and node. */ | |
599 | static inline void unmap_cpu_to_node(int cpu) | |
600 | { | |
601 | int node; | |
602 | ||
603 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
604 | for (node = 0; node < MAX_NUMNODES; node ++) | |
605 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
606 | cpu_2_node[cpu] = 0; | |
607 | } | |
608 | #else /* !CONFIG_NUMA */ | |
609 | ||
610 | #define map_cpu_to_node(cpu, node) ({}) | |
611 | #define unmap_cpu_to_node(cpu) ({}) | |
612 | ||
613 | #endif /* CONFIG_NUMA */ | |
614 | ||
6c036527 | 615 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
616 | |
617 | static void map_cpu_to_logical_apicid(void) | |
618 | { | |
619 | int cpu = smp_processor_id(); | |
620 | int apicid = logical_smp_processor_id(); | |
621 | ||
622 | cpu_2_logical_apicid[cpu] = apicid; | |
623 | map_cpu_to_node(cpu, apicid_to_node(apicid)); | |
624 | } | |
625 | ||
626 | static void unmap_cpu_to_logical_apicid(int cpu) | |
627 | { | |
628 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
629 | unmap_cpu_to_node(cpu); | |
630 | } | |
631 | ||
632 | #if APIC_DEBUG | |
633 | static inline void __inquire_remote_apic(int apicid) | |
634 | { | |
635 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
636 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
637 | int timeout, status; | |
638 | ||
639 | printk("Inquiring remote APIC #%d...\n", apicid); | |
640 | ||
38e548ee | 641 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
642 | printk("... APIC #%d %s: ", apicid, names[i]); |
643 | ||
644 | /* | |
645 | * Wait for idle. | |
646 | */ | |
647 | apic_wait_icr_idle(); | |
648 | ||
649 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
650 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
651 | ||
652 | timeout = 0; | |
653 | do { | |
654 | udelay(100); | |
655 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
656 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
657 | ||
658 | switch (status) { | |
659 | case APIC_ICR_RR_VALID: | |
660 | status = apic_read(APIC_RRR); | |
661 | printk("%08x\n", status); | |
662 | break; | |
663 | default: | |
664 | printk("failed\n"); | |
665 | } | |
666 | } | |
667 | } | |
668 | #endif | |
669 | ||
670 | #ifdef WAKE_SECONDARY_VIA_NMI | |
671 | /* | |
672 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
673 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
674 | * won't ... remember to clear down the APIC, etc later. | |
675 | */ | |
0bb3184d | 676 | static int __devinit |
1da177e4 LT |
677 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
678 | { | |
679 | unsigned long send_status = 0, accept_status = 0; | |
680 | int timeout, maxlvt; | |
681 | ||
682 | /* Target chip */ | |
683 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
684 | ||
685 | /* Boot on the stack */ | |
686 | /* Kick the second */ | |
687 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
688 | ||
689 | Dprintk("Waiting for send to finish...\n"); | |
690 | timeout = 0; | |
691 | do { | |
692 | Dprintk("+"); | |
693 | udelay(100); | |
694 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
695 | } while (send_status && (timeout++ < 1000)); | |
696 | ||
697 | /* | |
698 | * Give the other CPU some time to accept the IPI. | |
699 | */ | |
700 | udelay(200); | |
701 | /* | |
702 | * Due to the Pentium erratum 3AP. | |
703 | */ | |
704 | maxlvt = get_maxlvt(); | |
705 | if (maxlvt > 3) { | |
706 | apic_read_around(APIC_SPIV); | |
707 | apic_write(APIC_ESR, 0); | |
708 | } | |
709 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
710 | Dprintk("NMI sent.\n"); | |
711 | ||
712 | if (send_status) | |
713 | printk("APIC never delivered???\n"); | |
714 | if (accept_status) | |
715 | printk("APIC delivery error (%lx).\n", accept_status); | |
716 | ||
717 | return (send_status | accept_status); | |
718 | } | |
719 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
720 | ||
721 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 722 | static int __devinit |
1da177e4 LT |
723 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
724 | { | |
725 | unsigned long send_status = 0, accept_status = 0; | |
726 | int maxlvt, timeout, num_starts, j; | |
727 | ||
728 | /* | |
729 | * Be paranoid about clearing APIC errors. | |
730 | */ | |
731 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
732 | apic_read_around(APIC_SPIV); | |
733 | apic_write(APIC_ESR, 0); | |
734 | apic_read(APIC_ESR); | |
735 | } | |
736 | ||
737 | Dprintk("Asserting INIT.\n"); | |
738 | ||
739 | /* | |
740 | * Turn INIT on target chip | |
741 | */ | |
742 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
743 | ||
744 | /* | |
745 | * Send IPI | |
746 | */ | |
747 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
748 | | APIC_DM_INIT); | |
749 | ||
750 | Dprintk("Waiting for send to finish...\n"); | |
751 | timeout = 0; | |
752 | do { | |
753 | Dprintk("+"); | |
754 | udelay(100); | |
755 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
756 | } while (send_status && (timeout++ < 1000)); | |
757 | ||
758 | mdelay(10); | |
759 | ||
760 | Dprintk("Deasserting INIT.\n"); | |
761 | ||
762 | /* Target chip */ | |
763 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
764 | ||
765 | /* Send IPI */ | |
766 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
767 | ||
768 | Dprintk("Waiting for send to finish...\n"); | |
769 | timeout = 0; | |
770 | do { | |
771 | Dprintk("+"); | |
772 | udelay(100); | |
773 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
774 | } while (send_status && (timeout++ < 1000)); | |
775 | ||
776 | atomic_set(&init_deasserted, 1); | |
777 | ||
778 | /* | |
779 | * Should we send STARTUP IPIs ? | |
780 | * | |
781 | * Determine this based on the APIC version. | |
782 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
783 | */ | |
784 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
785 | num_starts = 2; | |
786 | else | |
787 | num_starts = 0; | |
788 | ||
789 | /* | |
790 | * Run STARTUP IPI loop. | |
791 | */ | |
792 | Dprintk("#startup loops: %d.\n", num_starts); | |
793 | ||
794 | maxlvt = get_maxlvt(); | |
795 | ||
796 | for (j = 1; j <= num_starts; j++) { | |
797 | Dprintk("Sending STARTUP #%d.\n",j); | |
798 | apic_read_around(APIC_SPIV); | |
799 | apic_write(APIC_ESR, 0); | |
800 | apic_read(APIC_ESR); | |
801 | Dprintk("After apic_write.\n"); | |
802 | ||
803 | /* | |
804 | * STARTUP IPI | |
805 | */ | |
806 | ||
807 | /* Target chip */ | |
808 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
809 | ||
810 | /* Boot on the stack */ | |
811 | /* Kick the second */ | |
812 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
813 | | (start_eip >> 12)); | |
814 | ||
815 | /* | |
816 | * Give the other CPU some time to accept the IPI. | |
817 | */ | |
818 | udelay(300); | |
819 | ||
820 | Dprintk("Startup point 1.\n"); | |
821 | ||
822 | Dprintk("Waiting for send to finish...\n"); | |
823 | timeout = 0; | |
824 | do { | |
825 | Dprintk("+"); | |
826 | udelay(100); | |
827 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
828 | } while (send_status && (timeout++ < 1000)); | |
829 | ||
830 | /* | |
831 | * Give the other CPU some time to accept the IPI. | |
832 | */ | |
833 | udelay(200); | |
834 | /* | |
835 | * Due to the Pentium erratum 3AP. | |
836 | */ | |
837 | if (maxlvt > 3) { | |
838 | apic_read_around(APIC_SPIV); | |
839 | apic_write(APIC_ESR, 0); | |
840 | } | |
841 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
842 | if (send_status || accept_status) | |
843 | break; | |
844 | } | |
845 | Dprintk("After Startup.\n"); | |
846 | ||
847 | if (send_status) | |
848 | printk("APIC never delivered???\n"); | |
849 | if (accept_status) | |
850 | printk("APIC delivery error (%lx).\n", accept_status); | |
851 | ||
852 | return (send_status | accept_status); | |
853 | } | |
854 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
855 | ||
856 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
857 | static inline int alloc_cpu_id(void) |
858 | { | |
859 | cpumask_t tmp_map; | |
860 | int cpu; | |
861 | cpus_complement(tmp_map, cpu_present_map); | |
862 | cpu = first_cpu(tmp_map); | |
863 | if (cpu >= NR_CPUS) | |
864 | return -ENODEV; | |
865 | return cpu; | |
866 | } | |
867 | ||
868 | #ifdef CONFIG_HOTPLUG_CPU | |
869 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
870 | static inline struct task_struct * alloc_idle_task(int cpu) | |
871 | { | |
872 | struct task_struct *idle; | |
873 | ||
874 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
875 | /* initialize thread_struct. we really want to avoid destroy | |
876 | * idle tread | |
877 | */ | |
878 | idle->thread.esp = (unsigned long)(((struct pt_regs *) | |
879 | (THREAD_SIZE + (unsigned long) idle->thread_info)) - 1); | |
880 | init_idle(idle, cpu); | |
881 | return idle; | |
882 | } | |
883 | idle = fork_idle(cpu); | |
884 | ||
885 | if (!IS_ERR(idle)) | |
886 | cpu_idle_tasks[cpu] = idle; | |
887 | return idle; | |
888 | } | |
889 | #else | |
890 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
891 | #endif | |
1da177e4 | 892 | |
e1367daf | 893 | static int __devinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
894 | /* |
895 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
896 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
897 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
898 | */ | |
899 | { | |
900 | struct task_struct *idle; | |
901 | unsigned long boot_error; | |
e1367daf | 902 | int timeout; |
1da177e4 LT |
903 | unsigned long start_eip; |
904 | unsigned short nmi_high = 0, nmi_low = 0; | |
905 | ||
7c4cb60e ZA |
906 | if (!cpu_gdt_descr[cpu].address && |
907 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
908 | printk("Failed to allocate GDT for CPU %d\n", cpu); | |
909 | return 1; | |
910 | } | |
911 | ||
e1367daf LS |
912 | ++cpucount; |
913 | ||
1da177e4 LT |
914 | /* |
915 | * We can't use kernel_thread since we must avoid to | |
916 | * reschedule the child. | |
917 | */ | |
e1367daf | 918 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
919 | if (IS_ERR(idle)) |
920 | panic("failed fork for CPU %d", cpu); | |
921 | idle->thread.eip = (unsigned long) start_secondary; | |
922 | /* start_eip had better be page-aligned! */ | |
923 | start_eip = setup_trampoline(); | |
924 | ||
925 | /* So we see what's up */ | |
926 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
927 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
928 | stack_start.esp = (void *) idle->thread.esp; | |
929 | ||
930 | irq_ctx_init(cpu); | |
931 | ||
932 | /* | |
933 | * This grunge runs the startup process for | |
934 | * the targeted processor. | |
935 | */ | |
936 | ||
937 | atomic_set(&init_deasserted, 0); | |
938 | ||
939 | Dprintk("Setting warm reset code and vector.\n"); | |
940 | ||
941 | store_NMI_vector(&nmi_high, &nmi_low); | |
942 | ||
943 | smpboot_setup_warm_reset_vector(start_eip); | |
944 | ||
945 | /* | |
946 | * Starting actual IPI sequence... | |
947 | */ | |
948 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
949 | ||
950 | if (!boot_error) { | |
951 | /* | |
952 | * allow APs to start initializing. | |
953 | */ | |
954 | Dprintk("Before Callout %d.\n", cpu); | |
955 | cpu_set(cpu, cpu_callout_map); | |
956 | Dprintk("After Callout %d.\n", cpu); | |
957 | ||
958 | /* | |
959 | * Wait 5s total for a response | |
960 | */ | |
961 | for (timeout = 0; timeout < 50000; timeout++) { | |
962 | if (cpu_isset(cpu, cpu_callin_map)) | |
963 | break; /* It has booted */ | |
964 | udelay(100); | |
965 | } | |
966 | ||
967 | if (cpu_isset(cpu, cpu_callin_map)) { | |
968 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
969 | Dprintk("OK.\n"); | |
970 | printk("CPU%d: ", cpu); | |
971 | print_cpu_info(&cpu_data[cpu]); | |
972 | Dprintk("CPU has booted.\n"); | |
973 | } else { | |
974 | boot_error= 1; | |
975 | if (*((volatile unsigned char *)trampoline_base) | |
976 | == 0xA5) | |
977 | /* trampoline started but...? */ | |
978 | printk("Stuck ??\n"); | |
979 | else | |
980 | /* trampoline code not run */ | |
981 | printk("Not responding.\n"); | |
982 | inquire_remote_apic(apicid); | |
983 | } | |
984 | } | |
e1367daf | 985 | |
1da177e4 LT |
986 | if (boot_error) { |
987 | /* Try to put things back the way they were before ... */ | |
988 | unmap_cpu_to_logical_apicid(cpu); | |
989 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
990 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
991 | cpucount--; | |
e1367daf LS |
992 | } else { |
993 | x86_cpu_to_apicid[cpu] = apicid; | |
994 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
995 | } |
996 | ||
997 | /* mark "stuck" area as not stuck */ | |
998 | *((volatile unsigned long *)trampoline_base) = 0; | |
999 | ||
1000 | return boot_error; | |
1001 | } | |
1002 | ||
e1367daf LS |
1003 | #ifdef CONFIG_HOTPLUG_CPU |
1004 | void cpu_exit_clear(void) | |
1005 | { | |
1006 | int cpu = raw_smp_processor_id(); | |
1007 | ||
1008 | idle_task_exit(); | |
1009 | ||
1010 | cpucount --; | |
1011 | cpu_uninit(); | |
1012 | irq_ctx_exit(cpu); | |
1013 | ||
1014 | cpu_clear(cpu, cpu_callout_map); | |
1015 | cpu_clear(cpu, cpu_callin_map); | |
1016 | cpu_clear(cpu, cpu_present_map); | |
1017 | ||
1018 | cpu_clear(cpu, smp_commenced_mask); | |
1019 | unmap_cpu_to_logical_apicid(cpu); | |
1020 | } | |
1021 | ||
1022 | struct warm_boot_cpu_info { | |
1023 | struct completion *complete; | |
1024 | int apicid; | |
1025 | int cpu; | |
1026 | }; | |
1027 | ||
1028 | static void __devinit do_warm_boot_cpu(void *p) | |
1029 | { | |
1030 | struct warm_boot_cpu_info *info = p; | |
1031 | do_boot_cpu(info->apicid, info->cpu); | |
1032 | complete(info->complete); | |
1033 | } | |
1034 | ||
1035 | int __devinit smp_prepare_cpu(int cpu) | |
1036 | { | |
1037 | DECLARE_COMPLETION(done); | |
1038 | struct warm_boot_cpu_info info; | |
1039 | struct work_struct task; | |
1040 | int apicid, ret; | |
1041 | ||
1042 | lock_cpu_hotplug(); | |
1043 | apicid = x86_cpu_to_apicid[cpu]; | |
1044 | if (apicid == BAD_APICID) { | |
1045 | ret = -ENODEV; | |
1046 | goto exit; | |
1047 | } | |
1048 | ||
1049 | info.complete = &done; | |
1050 | info.apicid = apicid; | |
1051 | info.cpu = cpu; | |
1052 | INIT_WORK(&task, do_warm_boot_cpu, &info); | |
1053 | ||
1054 | tsc_sync_disabled = 1; | |
1055 | ||
1056 | /* init low mem mapping */ | |
d7271b14 ZA |
1057 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
1058 | KERNEL_PGD_PTRS); | |
e1367daf LS |
1059 | flush_tlb_all(); |
1060 | schedule_work(&task); | |
1061 | wait_for_completion(&done); | |
1062 | ||
1063 | tsc_sync_disabled = 0; | |
1064 | zap_low_mappings(); | |
1065 | ret = 0; | |
1066 | exit: | |
1067 | unlock_cpu_hotplug(); | |
1068 | return ret; | |
1069 | } | |
1070 | #endif | |
1071 | ||
1da177e4 LT |
1072 | static void smp_tune_scheduling (void) |
1073 | { | |
1074 | unsigned long cachesize; /* kB */ | |
1075 | unsigned long bandwidth = 350; /* MB/s */ | |
1076 | /* | |
1077 | * Rough estimation for SMP scheduling, this is the number of | |
1078 | * cycles it takes for a fully memory-limited process to flush | |
1079 | * the SMP-local cache. | |
1080 | * | |
1081 | * (For a P5 this pretty much means we will choose another idle | |
1082 | * CPU almost always at wakeup time (this is due to the small | |
1083 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
1084 | * the cache size) | |
1085 | */ | |
1086 | ||
1087 | if (!cpu_khz) { | |
1088 | /* | |
1089 | * this basically disables processor-affinity | |
1090 | * scheduling on SMP without a TSC. | |
1091 | */ | |
1092 | return; | |
1093 | } else { | |
1094 | cachesize = boot_cpu_data.x86_cache_size; | |
1095 | if (cachesize == -1) { | |
1096 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
1097 | bandwidth = 100; | |
1098 | } | |
198e2f18 | 1099 | max_cache_size = cachesize * 1024; |
1da177e4 LT |
1100 | } |
1101 | } | |
1102 | ||
1103 | /* | |
1104 | * Cycle through the processors sending APIC IPIs to boot each. | |
1105 | */ | |
1106 | ||
1107 | static int boot_cpu_logical_apicid; | |
1108 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1109 | void *xquad_portio; | |
129f6946 AD |
1110 | #ifdef CONFIG_X86_NUMAQ |
1111 | EXPORT_SYMBOL(xquad_portio); | |
1112 | #endif | |
1da177e4 | 1113 | |
1da177e4 LT |
1114 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1115 | { | |
1116 | int apicid, cpu, bit, kicked; | |
1117 | unsigned long bogosum = 0; | |
1118 | ||
1119 | /* | |
1120 | * Setup boot CPU information | |
1121 | */ | |
1122 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1123 | printk("CPU%d: ", 0); | |
1124 | print_cpu_info(&cpu_data[0]); | |
1125 | ||
1e4c85f9 | 1126 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1127 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1128 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1129 | ||
1130 | current_thread_info()->cpu = 0; | |
1131 | smp_tune_scheduling(); | |
1da177e4 | 1132 | |
94605eff | 1133 | set_cpu_sibling_map(0); |
3dd9d514 | 1134 | |
1da177e4 LT |
1135 | /* |
1136 | * If we couldn't find an SMP configuration at boot time, | |
1137 | * get out of here now! | |
1138 | */ | |
1139 | if (!smp_found_config && !acpi_lapic) { | |
1140 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1141 | smpboot_clear_io_apic_irqs(); |
1142 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1143 | if (APIC_init_uniprocessor()) | |
1144 | printk(KERN_NOTICE "Local APIC not detected." | |
1145 | " Using dummy APIC emulation.\n"); | |
1146 | map_cpu_to_logical_apicid(); | |
1147 | cpu_set(0, cpu_sibling_map[0]); | |
1148 | cpu_set(0, cpu_core_map[0]); | |
1149 | return; | |
1150 | } | |
1151 | ||
1152 | /* | |
1153 | * Should not be necessary because the MP table should list the boot | |
1154 | * CPU too, but we do it for the sake of robustness anyway. | |
1155 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1156 | */ | |
1157 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1158 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1159 | boot_cpu_physical_apicid); | |
1160 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1161 | } | |
1162 | ||
1163 | /* | |
1164 | * If we couldn't find a local APIC, then get out of here now! | |
1165 | */ | |
1166 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1167 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1168 | boot_cpu_physical_apicid); | |
1169 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1170 | smpboot_clear_io_apic_irqs(); | |
1171 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1172 | cpu_set(0, cpu_sibling_map[0]); | |
1173 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1174 | return; |
1175 | } | |
1176 | ||
1e4c85f9 LT |
1177 | verify_local_APIC(); |
1178 | ||
1da177e4 LT |
1179 | /* |
1180 | * If SMP should be disabled, then really disable it! | |
1181 | */ | |
1e4c85f9 LT |
1182 | if (!max_cpus) { |
1183 | smp_found_config = 0; | |
1184 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1185 | smpboot_clear_io_apic_irqs(); | |
1186 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1187 | cpu_set(0, cpu_sibling_map[0]); | |
1188 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1189 | return; |
1190 | } | |
1191 | ||
1e4c85f9 LT |
1192 | connect_bsp_APIC(); |
1193 | setup_local_APIC(); | |
1194 | map_cpu_to_logical_apicid(); | |
1195 | ||
1196 | ||
1da177e4 LT |
1197 | setup_portio_remap(); |
1198 | ||
1199 | /* | |
1200 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1201 | * | |
1202 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1203 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1204 | * clustered apic ID. | |
1205 | */ | |
1206 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1207 | ||
1208 | kicked = 1; | |
1209 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1210 | apicid = cpu_present_to_apicid(bit); | |
1211 | /* | |
1212 | * Don't even attempt to start the boot CPU! | |
1213 | */ | |
1214 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1215 | continue; | |
1216 | ||
1217 | if (!check_apicid_present(bit)) | |
1218 | continue; | |
1219 | if (max_cpus <= cpucount+1) | |
1220 | continue; | |
1221 | ||
e1367daf | 1222 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1223 | printk("CPU #%d not responding - cannot use it.\n", |
1224 | apicid); | |
1225 | else | |
1226 | ++kicked; | |
1227 | } | |
1228 | ||
1229 | /* | |
1230 | * Cleanup possible dangling ends... | |
1231 | */ | |
1232 | smpboot_restore_warm_reset_vector(); | |
1233 | ||
1234 | /* | |
1235 | * Allow the user to impress friends. | |
1236 | */ | |
1237 | Dprintk("Before bogomips.\n"); | |
1238 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1239 | if (cpu_isset(cpu, cpu_callout_map)) | |
1240 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1241 | printk(KERN_INFO | |
1242 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1243 | cpucount+1, | |
1244 | bogosum/(500000/HZ), | |
1245 | (bogosum/(5000/HZ))%100); | |
1246 | ||
1247 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1248 | ||
1249 | if (smp_b_stepping) | |
1250 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1251 | ||
1252 | /* | |
1253 | * Don't taint if we are running SMP kernel on a single non-MP | |
1254 | * approved Athlon | |
1255 | */ | |
1256 | if (tainted & TAINT_UNSAFE_SMP) { | |
1257 | if (cpucount) | |
1258 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1259 | else | |
1260 | tainted &= ~TAINT_UNSAFE_SMP; | |
1261 | } | |
1262 | ||
1263 | Dprintk("Boot done.\n"); | |
1264 | ||
1265 | /* | |
1266 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1267 | * efficiently. | |
1268 | */ | |
3dd9d514 | 1269 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1270 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1271 | cpus_clear(cpu_core_map[cpu]); |
1272 | } | |
1da177e4 | 1273 | |
d720803a LS |
1274 | cpu_set(0, cpu_sibling_map[0]); |
1275 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1276 | |
1e4c85f9 LT |
1277 | smpboot_setup_io_apic(); |
1278 | ||
1279 | setup_boot_APIC_clock(); | |
1280 | ||
1da177e4 LT |
1281 | /* |
1282 | * Synchronize the TSC with the AP | |
1283 | */ | |
1284 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1285 | synchronize_tsc_bp(); | |
1286 | } | |
1287 | ||
1288 | /* These are wrappers to interface to the new boot process. Someone | |
1289 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1290 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1291 | { | |
f3705136 ZM |
1292 | smp_commenced_mask = cpumask_of_cpu(0); |
1293 | cpu_callin_map = cpumask_of_cpu(0); | |
1294 | mb(); | |
1da177e4 LT |
1295 | smp_boot_cpus(max_cpus); |
1296 | } | |
1297 | ||
1298 | void __devinit smp_prepare_boot_cpu(void) | |
1299 | { | |
1300 | cpu_set(smp_processor_id(), cpu_online_map); | |
1301 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1302 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1303 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1304 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1305 | } |
1306 | ||
f3705136 | 1307 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1308 | static void |
1309 | remove_siblinginfo(int cpu) | |
1da177e4 | 1310 | { |
e1367daf | 1311 | int sibling; |
94605eff | 1312 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1313 | |
94605eff SS |
1314 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1315 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1316 | /* | |
1317 | * last thread sibling in this cpu core going down | |
1318 | */ | |
1319 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1320 | c[sibling].booted_cores--; | |
1321 | } | |
1322 | ||
e1367daf LS |
1323 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1324 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1325 | cpus_clear(cpu_sibling_map[cpu]); |
1326 | cpus_clear(cpu_core_map[cpu]); | |
1327 | phys_proc_id[cpu] = BAD_APICID; | |
1328 | cpu_core_id[cpu] = BAD_APICID; | |
94605eff | 1329 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1330 | } |
1331 | ||
1332 | int __cpu_disable(void) | |
1333 | { | |
1334 | cpumask_t map = cpu_online_map; | |
1335 | int cpu = smp_processor_id(); | |
1336 | ||
1337 | /* | |
1338 | * Perhaps use cpufreq to drop frequency, but that could go | |
1339 | * into generic code. | |
1340 | * | |
1341 | * We won't take down the boot processor on i386 due to some | |
1342 | * interrupts only being able to be serviced by the BSP. | |
1343 | * Especially so if we're not using an IOAPIC -zwane | |
1344 | */ | |
1345 | if (cpu == 0) | |
1346 | return -EBUSY; | |
1347 | ||
5e9ef02e | 1348 | clear_local_APIC(); |
f3705136 ZM |
1349 | /* Allow any queued timer interrupts to get serviced */ |
1350 | local_irq_enable(); | |
1351 | mdelay(1); | |
1352 | local_irq_disable(); | |
1353 | ||
e1367daf LS |
1354 | remove_siblinginfo(cpu); |
1355 | ||
f3705136 ZM |
1356 | cpu_clear(cpu, map); |
1357 | fixup_irqs(map); | |
1358 | /* It's now safe to remove this processor from the online map */ | |
1359 | cpu_clear(cpu, cpu_online_map); | |
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | void __cpu_die(unsigned int cpu) | |
1364 | { | |
1365 | /* We don't do anything here: idle task is faking death itself. */ | |
1366 | unsigned int i; | |
1367 | ||
1368 | for (i = 0; i < 10; i++) { | |
1369 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1370 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1371 | printk ("CPU %d is now offline\n", cpu); | |
f3705136 | 1372 | return; |
e1367daf | 1373 | } |
aeb8397b | 1374 | msleep(100); |
1da177e4 | 1375 | } |
f3705136 ZM |
1376 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1377 | } | |
1378 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1379 | int __cpu_disable(void) | |
1380 | { | |
1381 | return -ENOSYS; | |
1382 | } | |
1da177e4 | 1383 | |
f3705136 ZM |
1384 | void __cpu_die(unsigned int cpu) |
1385 | { | |
1386 | /* We said "no" in __cpu_disable */ | |
1387 | BUG(); | |
1388 | } | |
1389 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1390 | ||
1391 | int __devinit __cpu_up(unsigned int cpu) | |
1392 | { | |
1da177e4 LT |
1393 | /* In case one didn't come up */ |
1394 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1395 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1396 | local_irq_enable(); |
1397 | return -EIO; | |
1398 | } | |
1399 | ||
1400 | local_irq_enable(); | |
e1367daf | 1401 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1402 | /* Unleash the CPU! */ |
1403 | cpu_set(cpu, smp_commenced_mask); | |
1404 | while (!cpu_isset(cpu, cpu_online_map)) | |
1405 | mb(); | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | void __init smp_cpus_done(unsigned int max_cpus) | |
1410 | { | |
1411 | #ifdef CONFIG_X86_IO_APIC | |
1412 | setup_ioapic_dest(); | |
1413 | #endif | |
1414 | zap_low_mappings(); | |
e1367daf | 1415 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1416 | /* |
1417 | * Disable executability of the SMP trampoline: | |
1418 | */ | |
1419 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1420 | #endif |
1da177e4 LT |
1421 | } |
1422 | ||
1423 | void __init smp_intr_init(void) | |
1424 | { | |
1425 | /* | |
1426 | * IRQ0 must be given a fixed assignment and initialized, | |
1427 | * because it's used before the IO-APIC is set up. | |
1428 | */ | |
1429 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1430 | ||
1431 | /* | |
1432 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1433 | * IPI, driven by wakeup. | |
1434 | */ | |
1435 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1436 | ||
1437 | /* IPI for invalidation */ | |
1438 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1439 | ||
1440 | /* IPI for generic function call */ | |
1441 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1442 | } |