Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
43 | #include <linux/smp_lock.h> | |
1da177e4 | 44 | #include <linux/bootmem.h> |
f3705136 ZM |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpu.h> | |
47 | #include <linux/percpu.h> | |
1da177e4 LT |
48 | |
49 | #include <linux/delay.h> | |
50 | #include <linux/mc146818rtc.h> | |
51 | #include <asm/tlbflush.h> | |
52 | #include <asm/desc.h> | |
53 | #include <asm/arch_hooks.h> | |
3e4ff115 | 54 | #include <asm/nmi.h> |
1da177e4 LT |
55 | |
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
59 | ||
60 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 61 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
129f6946 AD |
65 | #ifdef CONFIG_X86_HT |
66 | EXPORT_SYMBOL(smp_num_siblings); | |
67 | #endif | |
d720803a | 68 | |
1e9f28fa SS |
69 | /* Last level cache ID of each logical CPU */ |
70 | int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
71 | ||
94605eff | 72 | /* representing HT siblings of each logical CPU */ |
6c036527 | 73 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
74 | EXPORT_SYMBOL(cpu_sibling_map); |
75 | ||
94605eff | 76 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 77 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
78 | EXPORT_SYMBOL(cpu_core_map); |
79 | ||
1da177e4 | 80 | /* bitmap of online cpus */ |
6c036527 | 81 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 82 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
83 | |
84 | cpumask_t cpu_callin_map; | |
85 | cpumask_t cpu_callout_map; | |
129f6946 | 86 | EXPORT_SYMBOL(cpu_callout_map); |
4ad8d383 ZM |
87 | cpumask_t cpu_possible_map; |
88 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
89 | static cpumask_t smp_commenced_mask; |
90 | ||
e1367daf LS |
91 | /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there |
92 | * is no way to resync one AP against BP. TBD: for prescott and above, we | |
93 | * should use IA64's algorithm | |
94 | */ | |
95 | static int __devinitdata tsc_sync_disabled; | |
96 | ||
1da177e4 LT |
97 | /* Per CPU bogomips and other parameters */ |
98 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 99 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 100 | |
6c036527 | 101 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
102 | { [0 ... NR_CPUS-1] = 0xff }; |
103 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
104 | ||
3b08606d | 105 | u8 apicid_2_node[MAX_APICID]; |
106 | ||
1da177e4 LT |
107 | /* |
108 | * Trampoline 80x86 program as an array. | |
109 | */ | |
110 | ||
111 | extern unsigned char trampoline_data []; | |
112 | extern unsigned char trampoline_end []; | |
113 | static unsigned char *trampoline_base; | |
114 | static int trampoline_exec; | |
115 | ||
116 | static void map_cpu_to_logical_apicid(void); | |
117 | ||
f3705136 ZM |
118 | /* State of each CPU. */ |
119 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
120 | ||
1da177e4 LT |
121 | /* |
122 | * Currently trivial. Write the real->protected mode | |
123 | * bootstrap into the page concerned. The caller | |
124 | * has made sure it's suitably aligned. | |
125 | */ | |
126 | ||
0bb3184d | 127 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
128 | { |
129 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
130 | return virt_to_phys(trampoline_base); | |
131 | } | |
132 | ||
133 | /* | |
134 | * We are called very early to get the low memory for the | |
135 | * SMP bootup trampoline page. | |
136 | */ | |
137 | void __init smp_alloc_memory(void) | |
138 | { | |
139 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
140 | /* | |
141 | * Has to be in very low memory so we can execute | |
142 | * real-mode AP code. | |
143 | */ | |
144 | if (__pa(trampoline_base) >= 0x9F000) | |
145 | BUG(); | |
146 | /* | |
147 | * Make the SMP trampoline executable: | |
148 | */ | |
149 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
150 | } | |
151 | ||
152 | /* | |
153 | * The bootstrap kernel entry code has set these up. Save them for | |
154 | * a given CPU | |
155 | */ | |
156 | ||
0bb3184d | 157 | static void __devinit smp_store_cpu_info(int id) |
1da177e4 LT |
158 | { |
159 | struct cpuinfo_x86 *c = cpu_data + id; | |
160 | ||
161 | *c = boot_cpu_data; | |
162 | if (id!=0) | |
163 | identify_cpu(c); | |
164 | /* | |
165 | * Mask B, Pentium, but not Pentium MMX | |
166 | */ | |
167 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
168 | c->x86 == 5 && | |
169 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
170 | c->x86_model <= 3) | |
171 | /* | |
172 | * Remember we have B step Pentia with bugs | |
173 | */ | |
174 | smp_b_stepping = 1; | |
175 | ||
176 | /* | |
177 | * Certain Athlons might work (for various values of 'work') in SMP | |
178 | * but they are not certified as MP capable. | |
179 | */ | |
180 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
181 | ||
3ca113ea DJ |
182 | if (num_possible_cpus() == 1) |
183 | goto valid_k7; | |
184 | ||
1da177e4 LT |
185 | /* Athlon 660/661 is valid. */ |
186 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
187 | goto valid_k7; | |
188 | ||
189 | /* Duron 670 is valid */ | |
190 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
191 | goto valid_k7; | |
192 | ||
193 | /* | |
194 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
195 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
196 | * have the MP bit set. | |
197 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
198 | */ | |
199 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
200 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
201 | (c->x86_model> 7)) | |
202 | if (cpu_has_mp) | |
203 | goto valid_k7; | |
204 | ||
205 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 206 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
207 | } |
208 | ||
209 | valid_k7: | |
210 | ; | |
211 | } | |
212 | ||
213 | /* | |
214 | * TSC synchronization. | |
215 | * | |
216 | * We first check whether all CPUs have their TSC's synchronized, | |
217 | * then we print a warning if not, and always resync. | |
218 | */ | |
219 | ||
c35a7261 AM |
220 | static struct { |
221 | atomic_t start_flag; | |
222 | atomic_t count_start; | |
223 | atomic_t count_stop; | |
224 | unsigned long long values[NR_CPUS]; | |
225 | } tsc __initdata = { | |
226 | .start_flag = ATOMIC_INIT(0), | |
227 | .count_start = ATOMIC_INIT(0), | |
228 | .count_stop = ATOMIC_INIT(0), | |
229 | }; | |
1da177e4 LT |
230 | |
231 | #define NR_LOOPS 5 | |
232 | ||
c35a7261 | 233 | static void __init synchronize_tsc_bp(void) |
1da177e4 LT |
234 | { |
235 | int i; | |
236 | unsigned long long t0; | |
237 | unsigned long long sum, avg; | |
238 | long long delta; | |
a3a255e7 | 239 | unsigned int one_usec; |
1da177e4 LT |
240 | int buggy = 0; |
241 | ||
242 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
243 | ||
244 | /* convert from kcyc/sec to cyc/usec */ | |
245 | one_usec = cpu_khz / 1000; | |
246 | ||
c35a7261 | 247 | atomic_set(&tsc.start_flag, 1); |
1da177e4 LT |
248 | wmb(); |
249 | ||
250 | /* | |
251 | * We loop a few times to get a primed instruction cache, | |
252 | * then the last pass is more or less synchronized and | |
253 | * the BP and APs set their cycle counters to zero all at | |
254 | * once. This reduces the chance of having random offsets | |
255 | * between the processors, and guarantees that the maximum | |
256 | * delay between the cycle counters is never bigger than | |
257 | * the latency of information-passing (cachelines) between | |
258 | * two CPUs. | |
259 | */ | |
260 | for (i = 0; i < NR_LOOPS; i++) { | |
261 | /* | |
262 | * all APs synchronize but they loop on '== num_cpus' | |
263 | */ | |
c35a7261 | 264 | while (atomic_read(&tsc.count_start) != num_booting_cpus()-1) |
18698917 | 265 | cpu_relax(); |
c35a7261 | 266 | atomic_set(&tsc.count_stop, 0); |
1da177e4 LT |
267 | wmb(); |
268 | /* | |
269 | * this lets the APs save their current TSC: | |
270 | */ | |
c35a7261 | 271 | atomic_inc(&tsc.count_start); |
1da177e4 | 272 | |
c35a7261 | 273 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
274 | /* |
275 | * We clear the TSC in the last loop: | |
276 | */ | |
277 | if (i == NR_LOOPS-1) | |
278 | write_tsc(0, 0); | |
279 | ||
280 | /* | |
281 | * Wait for all APs to leave the synchronization point: | |
282 | */ | |
c35a7261 | 283 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1) |
18698917 | 284 | cpu_relax(); |
c35a7261 | 285 | atomic_set(&tsc.count_start, 0); |
1da177e4 | 286 | wmb(); |
c35a7261 | 287 | atomic_inc(&tsc.count_stop); |
1da177e4 LT |
288 | } |
289 | ||
290 | sum = 0; | |
291 | for (i = 0; i < NR_CPUS; i++) { | |
292 | if (cpu_isset(i, cpu_callout_map)) { | |
c35a7261 | 293 | t0 = tsc.values[i]; |
1da177e4 LT |
294 | sum += t0; |
295 | } | |
296 | } | |
297 | avg = sum; | |
298 | do_div(avg, num_booting_cpus()); | |
299 | ||
1da177e4 LT |
300 | for (i = 0; i < NR_CPUS; i++) { |
301 | if (!cpu_isset(i, cpu_callout_map)) | |
302 | continue; | |
c35a7261 | 303 | delta = tsc.values[i] - avg; |
1da177e4 LT |
304 | if (delta < 0) |
305 | delta = -delta; | |
306 | /* | |
307 | * We report bigger than 2 microseconds clock differences. | |
308 | */ | |
309 | if (delta > 2*one_usec) { | |
c35a7261 AM |
310 | long long realdelta; |
311 | ||
1da177e4 LT |
312 | if (!buggy) { |
313 | buggy = 1; | |
314 | printk("\n"); | |
315 | } | |
316 | realdelta = delta; | |
317 | do_div(realdelta, one_usec); | |
c35a7261 | 318 | if (tsc.values[i] < avg) |
1da177e4 LT |
319 | realdelta = -realdelta; |
320 | ||
c35a7261 AM |
321 | if (realdelta) |
322 | printk(KERN_INFO "CPU#%d had %Ld usecs TSC " | |
7f5910ec | 323 | "skew, fixed it up.\n", i, realdelta); |
1da177e4 | 324 | } |
1da177e4 LT |
325 | } |
326 | if (!buggy) | |
327 | printk("passed.\n"); | |
328 | } | |
329 | ||
c35a7261 | 330 | static void __init synchronize_tsc_ap(void) |
1da177e4 LT |
331 | { |
332 | int i; | |
333 | ||
334 | /* | |
335 | * Not every cpu is online at the time | |
336 | * this gets called, so we first wait for the BP to | |
337 | * finish SMP initialization: | |
338 | */ | |
c35a7261 | 339 | while (!atomic_read(&tsc.start_flag)) |
18698917 | 340 | cpu_relax(); |
1da177e4 LT |
341 | |
342 | for (i = 0; i < NR_LOOPS; i++) { | |
c35a7261 AM |
343 | atomic_inc(&tsc.count_start); |
344 | while (atomic_read(&tsc.count_start) != num_booting_cpus()) | |
18698917 | 345 | cpu_relax(); |
1da177e4 | 346 | |
c35a7261 | 347 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
348 | if (i == NR_LOOPS-1) |
349 | write_tsc(0, 0); | |
350 | ||
c35a7261 AM |
351 | atomic_inc(&tsc.count_stop); |
352 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()) | |
18698917 | 353 | cpu_relax(); |
1da177e4 LT |
354 | } |
355 | } | |
356 | #undef NR_LOOPS | |
357 | ||
358 | extern void calibrate_delay(void); | |
359 | ||
360 | static atomic_t init_deasserted; | |
361 | ||
0bb3184d | 362 | static void __devinit smp_callin(void) |
1da177e4 LT |
363 | { |
364 | int cpuid, phys_id; | |
365 | unsigned long timeout; | |
366 | ||
367 | /* | |
368 | * If waken up by an INIT in an 82489DX configuration | |
369 | * we may get here before an INIT-deassert IPI reaches | |
370 | * our local APIC. We have to wait for the IPI or we'll | |
371 | * lock up on an APIC access. | |
372 | */ | |
373 | wait_for_init_deassert(&init_deasserted); | |
374 | ||
375 | /* | |
376 | * (This works even if the APIC is not enabled.) | |
377 | */ | |
378 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
379 | cpuid = smp_processor_id(); | |
380 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
381 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
382 | phys_id, cpuid); | |
383 | BUG(); | |
384 | } | |
385 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
386 | ||
387 | /* | |
388 | * STARTUP IPIs are fragile beasts as they might sometimes | |
389 | * trigger some glue motherboard logic. Complete APIC bus | |
390 | * silence for 1 second, this overestimates the time the | |
391 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
392 | * by a factor of two. This should be enough. | |
393 | */ | |
394 | ||
395 | /* | |
396 | * Waiting 2s total for startup (udelay is not yet working) | |
397 | */ | |
398 | timeout = jiffies + 2*HZ; | |
399 | while (time_before(jiffies, timeout)) { | |
400 | /* | |
401 | * Has the boot CPU finished it's STARTUP sequence? | |
402 | */ | |
403 | if (cpu_isset(cpuid, cpu_callout_map)) | |
404 | break; | |
405 | rep_nop(); | |
406 | } | |
407 | ||
408 | if (!time_before(jiffies, timeout)) { | |
409 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
410 | cpuid); | |
411 | BUG(); | |
412 | } | |
413 | ||
414 | /* | |
415 | * the boot CPU has finished the init stage and is spinning | |
416 | * on callin_map until we finish. We are free to set up this | |
417 | * CPU, first the APIC. (this is probably redundant on most | |
418 | * boards) | |
419 | */ | |
420 | ||
421 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
422 | smp_callin_clear_local_apic(); | |
423 | setup_local_APIC(); | |
424 | map_cpu_to_logical_apicid(); | |
425 | ||
426 | /* | |
427 | * Get our bogomips. | |
428 | */ | |
429 | calibrate_delay(); | |
430 | Dprintk("Stack at about %p\n",&cpuid); | |
431 | ||
432 | /* | |
433 | * Save our processor parameters | |
434 | */ | |
435 | smp_store_cpu_info(cpuid); | |
436 | ||
437 | disable_APIC_timer(); | |
438 | ||
439 | /* | |
440 | * Allow the master to continue. | |
441 | */ | |
442 | cpu_set(cpuid, cpu_callin_map); | |
443 | ||
444 | /* | |
445 | * Synchronize the TSC with the BP | |
446 | */ | |
e1367daf | 447 | if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) |
1da177e4 LT |
448 | synchronize_tsc_ap(); |
449 | } | |
450 | ||
451 | static int cpucount; | |
452 | ||
1e9f28fa SS |
453 | /* maps the cpu to the sched domain representing multi-core */ |
454 | cpumask_t cpu_coregroup_map(int cpu) | |
455 | { | |
456 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
457 | /* | |
458 | * For perf, we return last level cache shared map. | |
5c45bf27 | 459 | * And for power savings, we return cpu_core_map |
1e9f28fa | 460 | */ |
5c45bf27 SS |
461 | if (sched_mc_power_savings || sched_smt_power_savings) |
462 | return cpu_core_map[cpu]; | |
463 | else | |
464 | return c->llc_shared_map; | |
1e9f28fa SS |
465 | } |
466 | ||
94605eff SS |
467 | /* representing cpus for which sibling maps can be computed */ |
468 | static cpumask_t cpu_sibling_setup_map; | |
469 | ||
d720803a LS |
470 | static inline void |
471 | set_cpu_sibling_map(int cpu) | |
472 | { | |
473 | int i; | |
94605eff SS |
474 | struct cpuinfo_x86 *c = cpu_data; |
475 | ||
476 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
477 | |
478 | if (smp_num_siblings > 1) { | |
94605eff | 479 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
4b89aff9 RS |
480 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
481 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
d720803a LS |
482 | cpu_set(i, cpu_sibling_map[cpu]); |
483 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
484 | cpu_set(i, cpu_core_map[cpu]); |
485 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
486 | cpu_set(i, c[cpu].llc_shared_map); |
487 | cpu_set(cpu, c[i].llc_shared_map); | |
d720803a LS |
488 | } |
489 | } | |
490 | } else { | |
491 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
492 | } | |
493 | ||
1e9f28fa SS |
494 | cpu_set(cpu, c[cpu].llc_shared_map); |
495 | ||
94605eff | 496 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 497 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
498 | c[cpu].booted_cores = 1; |
499 | return; | |
500 | } | |
501 | ||
502 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
503 | if (cpu_llc_id[cpu] != BAD_APICID && |
504 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
505 | cpu_set(i, c[cpu].llc_shared_map); | |
506 | cpu_set(cpu, c[i].llc_shared_map); | |
507 | } | |
4b89aff9 | 508 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
509 | cpu_set(i, cpu_core_map[cpu]); |
510 | cpu_set(cpu, cpu_core_map[i]); | |
511 | /* | |
512 | * Does this new cpu bringup a new core? | |
513 | */ | |
514 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
515 | /* | |
516 | * for each core in package, increment | |
517 | * the booted_cores for this new cpu | |
518 | */ | |
519 | if (first_cpu(cpu_sibling_map[i]) == i) | |
520 | c[cpu].booted_cores++; | |
521 | /* | |
522 | * increment the core count for all | |
523 | * the other cpus in this package | |
524 | */ | |
525 | if (i != cpu) | |
526 | c[i].booted_cores++; | |
527 | } else if (i != cpu && !c[cpu].booted_cores) | |
528 | c[cpu].booted_cores = c[i].booted_cores; | |
529 | } | |
d720803a LS |
530 | } |
531 | } | |
532 | ||
1da177e4 LT |
533 | /* |
534 | * Activate a secondary processor. | |
535 | */ | |
0bb3184d | 536 | static void __devinit start_secondary(void *unused) |
1da177e4 LT |
537 | { |
538 | /* | |
539 | * Dont put anything before smp_callin(), SMP | |
540 | * booting is too fragile that we want to limit the | |
541 | * things done here to the most necessary things. | |
542 | */ | |
543 | cpu_init(); | |
5bfb5d69 | 544 | preempt_disable(); |
1da177e4 LT |
545 | smp_callin(); |
546 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
547 | rep_nop(); | |
548 | setup_secondary_APIC_clock(); | |
549 | if (nmi_watchdog == NMI_IO_APIC) { | |
550 | disable_8259A_irq(0); | |
551 | enable_NMI_through_LVT0(NULL); | |
552 | enable_8259A_irq(0); | |
553 | } | |
554 | enable_APIC_timer(); | |
555 | /* | |
556 | * low-memory mappings have been cleared, flush them from | |
557 | * the local TLBs too. | |
558 | */ | |
559 | local_flush_tlb(); | |
6fe940d6 | 560 | |
d720803a LS |
561 | /* This must be done before setting cpu_online_map */ |
562 | set_cpu_sibling_map(raw_smp_processor_id()); | |
563 | wmb(); | |
564 | ||
6fe940d6 LS |
565 | /* |
566 | * We need to hold call_lock, so there is no inconsistency | |
567 | * between the time smp_call_function() determines number of | |
568 | * IPI receipients, and the time when the determination is made | |
569 | * for which cpus receive the IPI. Holding this | |
570 | * lock helps us to not include this cpu in a currently in progress | |
571 | * smp_call_function(). | |
572 | */ | |
573 | lock_ipi_call_lock(); | |
1da177e4 | 574 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 575 | unlock_ipi_call_lock(); |
e1367daf | 576 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
577 | |
578 | /* We can take interrupts now: we're officially "up". */ | |
579 | local_irq_enable(); | |
580 | ||
581 | wmb(); | |
582 | cpu_idle(); | |
583 | } | |
584 | ||
585 | /* | |
586 | * Everything has been set up for the secondary | |
587 | * CPUs - they just need to reload everything | |
588 | * from the task structure | |
589 | * This function must not return. | |
590 | */ | |
0bb3184d | 591 | void __devinit initialize_secondary(void) |
1da177e4 LT |
592 | { |
593 | /* | |
594 | * We don't actually need to load the full TSS, | |
595 | * basically just the stack pointer and the eip. | |
596 | */ | |
597 | ||
598 | asm volatile( | |
599 | "movl %0,%%esp\n\t" | |
600 | "jmp *%1" | |
601 | : | |
602 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
603 | } | |
604 | ||
605 | extern struct { | |
606 | void * esp; | |
607 | unsigned short ss; | |
608 | } stack_start; | |
609 | ||
610 | #ifdef CONFIG_NUMA | |
611 | ||
612 | /* which logical CPUs are on which nodes */ | |
6c036527 | 613 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 | 614 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
a406c366 | 615 | EXPORT_SYMBOL(node_2_cpu_mask); |
1da177e4 | 616 | /* which node each logical CPU is on */ |
6c036527 | 617 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
618 | EXPORT_SYMBOL(cpu_2_node); |
619 | ||
620 | /* set up a mapping between cpu and node. */ | |
621 | static inline void map_cpu_to_node(int cpu, int node) | |
622 | { | |
623 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
624 | cpu_set(cpu, node_2_cpu_mask[node]); | |
625 | cpu_2_node[cpu] = node; | |
626 | } | |
627 | ||
628 | /* undo a mapping between cpu and node. */ | |
629 | static inline void unmap_cpu_to_node(int cpu) | |
630 | { | |
631 | int node; | |
632 | ||
633 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
634 | for (node = 0; node < MAX_NUMNODES; node ++) | |
635 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
636 | cpu_2_node[cpu] = 0; | |
637 | } | |
638 | #else /* !CONFIG_NUMA */ | |
639 | ||
640 | #define map_cpu_to_node(cpu, node) ({}) | |
641 | #define unmap_cpu_to_node(cpu) ({}) | |
642 | ||
643 | #endif /* CONFIG_NUMA */ | |
644 | ||
6c036527 | 645 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
646 | |
647 | static void map_cpu_to_logical_apicid(void) | |
648 | { | |
649 | int cpu = smp_processor_id(); | |
650 | int apicid = logical_smp_processor_id(); | |
78b656b8 | 651 | int node = apicid_to_node(apicid); |
bfa0e9a0 | 652 | |
653 | if (!node_online(node)) | |
654 | node = first_online_node; | |
1da177e4 LT |
655 | |
656 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 657 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
658 | } |
659 | ||
660 | static void unmap_cpu_to_logical_apicid(int cpu) | |
661 | { | |
662 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
663 | unmap_cpu_to_node(cpu); | |
664 | } | |
665 | ||
666 | #if APIC_DEBUG | |
667 | static inline void __inquire_remote_apic(int apicid) | |
668 | { | |
669 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
670 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
671 | int timeout, status; | |
672 | ||
673 | printk("Inquiring remote APIC #%d...\n", apicid); | |
674 | ||
38e548ee | 675 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
676 | printk("... APIC #%d %s: ", apicid, names[i]); |
677 | ||
678 | /* | |
679 | * Wait for idle. | |
680 | */ | |
681 | apic_wait_icr_idle(); | |
682 | ||
683 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
684 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
685 | ||
686 | timeout = 0; | |
687 | do { | |
688 | udelay(100); | |
689 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
690 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
691 | ||
692 | switch (status) { | |
693 | case APIC_ICR_RR_VALID: | |
694 | status = apic_read(APIC_RRR); | |
695 | printk("%08x\n", status); | |
696 | break; | |
697 | default: | |
698 | printk("failed\n"); | |
699 | } | |
700 | } | |
701 | } | |
702 | #endif | |
703 | ||
704 | #ifdef WAKE_SECONDARY_VIA_NMI | |
705 | /* | |
706 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
707 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
708 | * won't ... remember to clear down the APIC, etc later. | |
709 | */ | |
0bb3184d | 710 | static int __devinit |
1da177e4 LT |
711 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
712 | { | |
713 | unsigned long send_status = 0, accept_status = 0; | |
714 | int timeout, maxlvt; | |
715 | ||
716 | /* Target chip */ | |
717 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
718 | ||
719 | /* Boot on the stack */ | |
720 | /* Kick the second */ | |
721 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
722 | ||
723 | Dprintk("Waiting for send to finish...\n"); | |
724 | timeout = 0; | |
725 | do { | |
726 | Dprintk("+"); | |
727 | udelay(100); | |
728 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
729 | } while (send_status && (timeout++ < 1000)); | |
730 | ||
731 | /* | |
732 | * Give the other CPU some time to accept the IPI. | |
733 | */ | |
734 | udelay(200); | |
735 | /* | |
736 | * Due to the Pentium erratum 3AP. | |
737 | */ | |
738 | maxlvt = get_maxlvt(); | |
739 | if (maxlvt > 3) { | |
740 | apic_read_around(APIC_SPIV); | |
741 | apic_write(APIC_ESR, 0); | |
742 | } | |
743 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
744 | Dprintk("NMI sent.\n"); | |
745 | ||
746 | if (send_status) | |
747 | printk("APIC never delivered???\n"); | |
748 | if (accept_status) | |
749 | printk("APIC delivery error (%lx).\n", accept_status); | |
750 | ||
751 | return (send_status | accept_status); | |
752 | } | |
753 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
754 | ||
755 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 756 | static int __devinit |
1da177e4 LT |
757 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
758 | { | |
759 | unsigned long send_status = 0, accept_status = 0; | |
760 | int maxlvt, timeout, num_starts, j; | |
761 | ||
762 | /* | |
763 | * Be paranoid about clearing APIC errors. | |
764 | */ | |
765 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
766 | apic_read_around(APIC_SPIV); | |
767 | apic_write(APIC_ESR, 0); | |
768 | apic_read(APIC_ESR); | |
769 | } | |
770 | ||
771 | Dprintk("Asserting INIT.\n"); | |
772 | ||
773 | /* | |
774 | * Turn INIT on target chip | |
775 | */ | |
776 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
777 | ||
778 | /* | |
779 | * Send IPI | |
780 | */ | |
781 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
782 | | APIC_DM_INIT); | |
783 | ||
784 | Dprintk("Waiting for send to finish...\n"); | |
785 | timeout = 0; | |
786 | do { | |
787 | Dprintk("+"); | |
788 | udelay(100); | |
789 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
790 | } while (send_status && (timeout++ < 1000)); | |
791 | ||
792 | mdelay(10); | |
793 | ||
794 | Dprintk("Deasserting INIT.\n"); | |
795 | ||
796 | /* Target chip */ | |
797 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
798 | ||
799 | /* Send IPI */ | |
800 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
801 | ||
802 | Dprintk("Waiting for send to finish...\n"); | |
803 | timeout = 0; | |
804 | do { | |
805 | Dprintk("+"); | |
806 | udelay(100); | |
807 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
808 | } while (send_status && (timeout++ < 1000)); | |
809 | ||
810 | atomic_set(&init_deasserted, 1); | |
811 | ||
812 | /* | |
813 | * Should we send STARTUP IPIs ? | |
814 | * | |
815 | * Determine this based on the APIC version. | |
816 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
817 | */ | |
818 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
819 | num_starts = 2; | |
820 | else | |
821 | num_starts = 0; | |
822 | ||
823 | /* | |
824 | * Run STARTUP IPI loop. | |
825 | */ | |
826 | Dprintk("#startup loops: %d.\n", num_starts); | |
827 | ||
828 | maxlvt = get_maxlvt(); | |
829 | ||
830 | for (j = 1; j <= num_starts; j++) { | |
831 | Dprintk("Sending STARTUP #%d.\n",j); | |
832 | apic_read_around(APIC_SPIV); | |
833 | apic_write(APIC_ESR, 0); | |
834 | apic_read(APIC_ESR); | |
835 | Dprintk("After apic_write.\n"); | |
836 | ||
837 | /* | |
838 | * STARTUP IPI | |
839 | */ | |
840 | ||
841 | /* Target chip */ | |
842 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
843 | ||
844 | /* Boot on the stack */ | |
845 | /* Kick the second */ | |
846 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
847 | | (start_eip >> 12)); | |
848 | ||
849 | /* | |
850 | * Give the other CPU some time to accept the IPI. | |
851 | */ | |
852 | udelay(300); | |
853 | ||
854 | Dprintk("Startup point 1.\n"); | |
855 | ||
856 | Dprintk("Waiting for send to finish...\n"); | |
857 | timeout = 0; | |
858 | do { | |
859 | Dprintk("+"); | |
860 | udelay(100); | |
861 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
862 | } while (send_status && (timeout++ < 1000)); | |
863 | ||
864 | /* | |
865 | * Give the other CPU some time to accept the IPI. | |
866 | */ | |
867 | udelay(200); | |
868 | /* | |
869 | * Due to the Pentium erratum 3AP. | |
870 | */ | |
871 | if (maxlvt > 3) { | |
872 | apic_read_around(APIC_SPIV); | |
873 | apic_write(APIC_ESR, 0); | |
874 | } | |
875 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
876 | if (send_status || accept_status) | |
877 | break; | |
878 | } | |
879 | Dprintk("After Startup.\n"); | |
880 | ||
881 | if (send_status) | |
882 | printk("APIC never delivered???\n"); | |
883 | if (accept_status) | |
884 | printk("APIC delivery error (%lx).\n", accept_status); | |
885 | ||
886 | return (send_status | accept_status); | |
887 | } | |
888 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
889 | ||
890 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
891 | static inline int alloc_cpu_id(void) |
892 | { | |
893 | cpumask_t tmp_map; | |
894 | int cpu; | |
895 | cpus_complement(tmp_map, cpu_present_map); | |
896 | cpu = first_cpu(tmp_map); | |
897 | if (cpu >= NR_CPUS) | |
898 | return -ENODEV; | |
899 | return cpu; | |
900 | } | |
901 | ||
902 | #ifdef CONFIG_HOTPLUG_CPU | |
903 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
904 | static inline struct task_struct * alloc_idle_task(int cpu) | |
905 | { | |
906 | struct task_struct *idle; | |
907 | ||
908 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
909 | /* initialize thread_struct. we really want to avoid destroy | |
910 | * idle tread | |
911 | */ | |
07b047fc | 912 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
913 | init_idle(idle, cpu); |
914 | return idle; | |
915 | } | |
916 | idle = fork_idle(cpu); | |
917 | ||
918 | if (!IS_ERR(idle)) | |
919 | cpu_idle_tasks[cpu] = idle; | |
920 | return idle; | |
921 | } | |
922 | #else | |
923 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
924 | #endif | |
1da177e4 | 925 | |
e1367daf | 926 | static int __devinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
927 | /* |
928 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
929 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
930 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
931 | */ | |
932 | { | |
933 | struct task_struct *idle; | |
934 | unsigned long boot_error; | |
e1367daf | 935 | int timeout; |
1da177e4 LT |
936 | unsigned long start_eip; |
937 | unsigned short nmi_high = 0, nmi_low = 0; | |
938 | ||
e1367daf | 939 | ++cpucount; |
9a0b5817 | 940 | alternatives_smp_switch(1); |
e1367daf | 941 | |
1da177e4 LT |
942 | /* |
943 | * We can't use kernel_thread since we must avoid to | |
944 | * reschedule the child. | |
945 | */ | |
e1367daf | 946 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
947 | if (IS_ERR(idle)) |
948 | panic("failed fork for CPU %d", cpu); | |
949 | idle->thread.eip = (unsigned long) start_secondary; | |
950 | /* start_eip had better be page-aligned! */ | |
951 | start_eip = setup_trampoline(); | |
952 | ||
953 | /* So we see what's up */ | |
954 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
955 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
956 | stack_start.esp = (void *) idle->thread.esp; | |
957 | ||
958 | irq_ctx_init(cpu); | |
959 | ||
3b08606d | 960 | x86_cpu_to_apicid[cpu] = apicid; |
1da177e4 LT |
961 | /* |
962 | * This grunge runs the startup process for | |
963 | * the targeted processor. | |
964 | */ | |
965 | ||
966 | atomic_set(&init_deasserted, 0); | |
967 | ||
968 | Dprintk("Setting warm reset code and vector.\n"); | |
969 | ||
970 | store_NMI_vector(&nmi_high, &nmi_low); | |
971 | ||
972 | smpboot_setup_warm_reset_vector(start_eip); | |
973 | ||
974 | /* | |
975 | * Starting actual IPI sequence... | |
976 | */ | |
977 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
978 | ||
979 | if (!boot_error) { | |
980 | /* | |
981 | * allow APs to start initializing. | |
982 | */ | |
983 | Dprintk("Before Callout %d.\n", cpu); | |
984 | cpu_set(cpu, cpu_callout_map); | |
985 | Dprintk("After Callout %d.\n", cpu); | |
986 | ||
987 | /* | |
988 | * Wait 5s total for a response | |
989 | */ | |
990 | for (timeout = 0; timeout < 50000; timeout++) { | |
991 | if (cpu_isset(cpu, cpu_callin_map)) | |
992 | break; /* It has booted */ | |
993 | udelay(100); | |
994 | } | |
995 | ||
996 | if (cpu_isset(cpu, cpu_callin_map)) { | |
997 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
998 | Dprintk("OK.\n"); | |
999 | printk("CPU%d: ", cpu); | |
1000 | print_cpu_info(&cpu_data[cpu]); | |
1001 | Dprintk("CPU has booted.\n"); | |
1002 | } else { | |
1003 | boot_error= 1; | |
1004 | if (*((volatile unsigned char *)trampoline_base) | |
1005 | == 0xA5) | |
1006 | /* trampoline started but...? */ | |
1007 | printk("Stuck ??\n"); | |
1008 | else | |
1009 | /* trampoline code not run */ | |
1010 | printk("Not responding.\n"); | |
1011 | inquire_remote_apic(apicid); | |
1012 | } | |
1013 | } | |
e1367daf | 1014 | |
1da177e4 LT |
1015 | if (boot_error) { |
1016 | /* Try to put things back the way they were before ... */ | |
1017 | unmap_cpu_to_logical_apicid(cpu); | |
1018 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
1019 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
1020 | cpucount--; | |
e1367daf LS |
1021 | } else { |
1022 | x86_cpu_to_apicid[cpu] = apicid; | |
1023 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
1024 | } |
1025 | ||
1026 | /* mark "stuck" area as not stuck */ | |
1027 | *((volatile unsigned long *)trampoline_base) = 0; | |
1028 | ||
1029 | return boot_error; | |
1030 | } | |
1031 | ||
e1367daf LS |
1032 | #ifdef CONFIG_HOTPLUG_CPU |
1033 | void cpu_exit_clear(void) | |
1034 | { | |
1035 | int cpu = raw_smp_processor_id(); | |
1036 | ||
1037 | idle_task_exit(); | |
1038 | ||
1039 | cpucount --; | |
1040 | cpu_uninit(); | |
1041 | irq_ctx_exit(cpu); | |
1042 | ||
1043 | cpu_clear(cpu, cpu_callout_map); | |
1044 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
1045 | |
1046 | cpu_clear(cpu, smp_commenced_mask); | |
1047 | unmap_cpu_to_logical_apicid(cpu); | |
1048 | } | |
1049 | ||
1050 | struct warm_boot_cpu_info { | |
1051 | struct completion *complete; | |
c4028958 | 1052 | struct work_struct task; |
e1367daf LS |
1053 | int apicid; |
1054 | int cpu; | |
1055 | }; | |
1056 | ||
c4028958 | 1057 | static void __cpuinit do_warm_boot_cpu(struct work_struct *work) |
e1367daf | 1058 | { |
c4028958 DH |
1059 | struct warm_boot_cpu_info *info = |
1060 | container_of(work, struct warm_boot_cpu_info, task); | |
e1367daf LS |
1061 | do_boot_cpu(info->apicid, info->cpu); |
1062 | complete(info->complete); | |
1063 | } | |
1064 | ||
34f361ad | 1065 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf | 1066 | { |
6e9a4738 | 1067 | DECLARE_COMPLETION_ONSTACK(done); |
e1367daf | 1068 | struct warm_boot_cpu_info info; |
e1367daf | 1069 | int apicid, ret; |
bd9e0b74 | 1070 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
e1367daf | 1071 | |
e1367daf LS |
1072 | apicid = x86_cpu_to_apicid[cpu]; |
1073 | if (apicid == BAD_APICID) { | |
1074 | ret = -ENODEV; | |
1075 | goto exit; | |
1076 | } | |
1077 | ||
bd9e0b74 SL |
1078 | /* |
1079 | * the CPU isn't initialized at boot time, allocate gdt table here. | |
1080 | * cpu_init will initialize it | |
1081 | */ | |
1082 | if (!cpu_gdt_descr->address) { | |
1083 | cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL); | |
1084 | if (!cpu_gdt_descr->address) | |
1085 | printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu); | |
1086 | ret = -ENOMEM; | |
1087 | goto exit; | |
1088 | } | |
1089 | ||
e1367daf LS |
1090 | info.complete = &done; |
1091 | info.apicid = apicid; | |
1092 | info.cpu = cpu; | |
c4028958 | 1093 | INIT_WORK(&info.task, do_warm_boot_cpu); |
e1367daf LS |
1094 | |
1095 | tsc_sync_disabled = 1; | |
1096 | ||
1097 | /* init low mem mapping */ | |
d7271b14 ZA |
1098 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
1099 | KERNEL_PGD_PTRS); | |
e1367daf | 1100 | flush_tlb_all(); |
c4028958 | 1101 | schedule_work(&info.task); |
e1367daf LS |
1102 | wait_for_completion(&done); |
1103 | ||
1104 | tsc_sync_disabled = 0; | |
1105 | zap_low_mappings(); | |
1106 | ret = 0; | |
1107 | exit: | |
e1367daf LS |
1108 | return ret; |
1109 | } | |
1110 | #endif | |
1111 | ||
1da177e4 LT |
1112 | static void smp_tune_scheduling (void) |
1113 | { | |
1114 | unsigned long cachesize; /* kB */ | |
1115 | unsigned long bandwidth = 350; /* MB/s */ | |
1116 | /* | |
1117 | * Rough estimation for SMP scheduling, this is the number of | |
1118 | * cycles it takes for a fully memory-limited process to flush | |
1119 | * the SMP-local cache. | |
1120 | * | |
1121 | * (For a P5 this pretty much means we will choose another idle | |
1122 | * CPU almost always at wakeup time (this is due to the small | |
1123 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
1124 | * the cache size) | |
1125 | */ | |
1126 | ||
1127 | if (!cpu_khz) { | |
1128 | /* | |
1129 | * this basically disables processor-affinity | |
1130 | * scheduling on SMP without a TSC. | |
1131 | */ | |
1132 | return; | |
1133 | } else { | |
1134 | cachesize = boot_cpu_data.x86_cache_size; | |
1135 | if (cachesize == -1) { | |
1136 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
1137 | bandwidth = 100; | |
1138 | } | |
198e2f18 | 1139 | max_cache_size = cachesize * 1024; |
1da177e4 LT |
1140 | } |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Cycle through the processors sending APIC IPIs to boot each. | |
1145 | */ | |
1146 | ||
1147 | static int boot_cpu_logical_apicid; | |
1148 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1149 | void *xquad_portio; | |
129f6946 AD |
1150 | #ifdef CONFIG_X86_NUMAQ |
1151 | EXPORT_SYMBOL(xquad_portio); | |
1152 | #endif | |
1da177e4 | 1153 | |
1da177e4 LT |
1154 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1155 | { | |
1156 | int apicid, cpu, bit, kicked; | |
1157 | unsigned long bogosum = 0; | |
1158 | ||
1159 | /* | |
1160 | * Setup boot CPU information | |
1161 | */ | |
1162 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1163 | printk("CPU%d: ", 0); | |
1164 | print_cpu_info(&cpu_data[0]); | |
1165 | ||
1e4c85f9 | 1166 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1167 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1168 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1169 | ||
1170 | current_thread_info()->cpu = 0; | |
1171 | smp_tune_scheduling(); | |
1da177e4 | 1172 | |
94605eff | 1173 | set_cpu_sibling_map(0); |
3dd9d514 | 1174 | |
1da177e4 LT |
1175 | /* |
1176 | * If we couldn't find an SMP configuration at boot time, | |
1177 | * get out of here now! | |
1178 | */ | |
1179 | if (!smp_found_config && !acpi_lapic) { | |
1180 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1181 | smpboot_clear_io_apic_irqs(); |
1182 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1183 | if (APIC_init_uniprocessor()) | |
1184 | printk(KERN_NOTICE "Local APIC not detected." | |
1185 | " Using dummy APIC emulation.\n"); | |
1186 | map_cpu_to_logical_apicid(); | |
1187 | cpu_set(0, cpu_sibling_map[0]); | |
1188 | cpu_set(0, cpu_core_map[0]); | |
1189 | return; | |
1190 | } | |
1191 | ||
1192 | /* | |
1193 | * Should not be necessary because the MP table should list the boot | |
1194 | * CPU too, but we do it for the sake of robustness anyway. | |
1195 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1196 | */ | |
1197 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1198 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1199 | boot_cpu_physical_apicid); | |
1200 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1201 | } | |
1202 | ||
1203 | /* | |
1204 | * If we couldn't find a local APIC, then get out of here now! | |
1205 | */ | |
1206 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1207 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1208 | boot_cpu_physical_apicid); | |
1209 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1210 | smpboot_clear_io_apic_irqs(); | |
1211 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1212 | cpu_set(0, cpu_sibling_map[0]); | |
1213 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1214 | return; |
1215 | } | |
1216 | ||
1e4c85f9 LT |
1217 | verify_local_APIC(); |
1218 | ||
1da177e4 LT |
1219 | /* |
1220 | * If SMP should be disabled, then really disable it! | |
1221 | */ | |
1e4c85f9 LT |
1222 | if (!max_cpus) { |
1223 | smp_found_config = 0; | |
1224 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1225 | smpboot_clear_io_apic_irqs(); | |
1226 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1227 | cpu_set(0, cpu_sibling_map[0]); | |
1228 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1229 | return; |
1230 | } | |
1231 | ||
1e4c85f9 LT |
1232 | connect_bsp_APIC(); |
1233 | setup_local_APIC(); | |
1234 | map_cpu_to_logical_apicid(); | |
1235 | ||
1236 | ||
1da177e4 LT |
1237 | setup_portio_remap(); |
1238 | ||
1239 | /* | |
1240 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1241 | * | |
1242 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1243 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1244 | * clustered apic ID. | |
1245 | */ | |
1246 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1247 | ||
1248 | kicked = 1; | |
1249 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1250 | apicid = cpu_present_to_apicid(bit); | |
1251 | /* | |
1252 | * Don't even attempt to start the boot CPU! | |
1253 | */ | |
1254 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1255 | continue; | |
1256 | ||
1257 | if (!check_apicid_present(bit)) | |
1258 | continue; | |
1259 | if (max_cpus <= cpucount+1) | |
1260 | continue; | |
1261 | ||
e1367daf | 1262 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1263 | printk("CPU #%d not responding - cannot use it.\n", |
1264 | apicid); | |
1265 | else | |
1266 | ++kicked; | |
1267 | } | |
1268 | ||
1269 | /* | |
1270 | * Cleanup possible dangling ends... | |
1271 | */ | |
1272 | smpboot_restore_warm_reset_vector(); | |
1273 | ||
1274 | /* | |
1275 | * Allow the user to impress friends. | |
1276 | */ | |
1277 | Dprintk("Before bogomips.\n"); | |
1278 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1279 | if (cpu_isset(cpu, cpu_callout_map)) | |
1280 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1281 | printk(KERN_INFO | |
1282 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1283 | cpucount+1, | |
1284 | bogosum/(500000/HZ), | |
1285 | (bogosum/(5000/HZ))%100); | |
1286 | ||
1287 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1288 | ||
1289 | if (smp_b_stepping) | |
1290 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1291 | ||
1292 | /* | |
1293 | * Don't taint if we are running SMP kernel on a single non-MP | |
1294 | * approved Athlon | |
1295 | */ | |
1296 | if (tainted & TAINT_UNSAFE_SMP) { | |
1297 | if (cpucount) | |
1298 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1299 | else | |
1300 | tainted &= ~TAINT_UNSAFE_SMP; | |
1301 | } | |
1302 | ||
1303 | Dprintk("Boot done.\n"); | |
1304 | ||
1305 | /* | |
1306 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1307 | * efficiently. | |
1308 | */ | |
3dd9d514 | 1309 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1310 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1311 | cpus_clear(cpu_core_map[cpu]); |
1312 | } | |
1da177e4 | 1313 | |
d720803a LS |
1314 | cpu_set(0, cpu_sibling_map[0]); |
1315 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1316 | |
1e4c85f9 LT |
1317 | smpboot_setup_io_apic(); |
1318 | ||
1319 | setup_boot_APIC_clock(); | |
1320 | ||
1da177e4 LT |
1321 | /* |
1322 | * Synchronize the TSC with the AP | |
1323 | */ | |
1324 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1325 | synchronize_tsc_bp(); | |
1326 | } | |
1327 | ||
1328 | /* These are wrappers to interface to the new boot process. Someone | |
1329 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1330 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1331 | { | |
f3705136 ZM |
1332 | smp_commenced_mask = cpumask_of_cpu(0); |
1333 | cpu_callin_map = cpumask_of_cpu(0); | |
1334 | mb(); | |
1da177e4 LT |
1335 | smp_boot_cpus(max_cpus); |
1336 | } | |
1337 | ||
1338 | void __devinit smp_prepare_boot_cpu(void) | |
1339 | { | |
1340 | cpu_set(smp_processor_id(), cpu_online_map); | |
1341 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1342 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1343 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1344 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1345 | } |
1346 | ||
f3705136 | 1347 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1348 | static void |
1349 | remove_siblinginfo(int cpu) | |
1da177e4 | 1350 | { |
e1367daf | 1351 | int sibling; |
94605eff | 1352 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1353 | |
94605eff SS |
1354 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1355 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1356 | /* | |
1357 | * last thread sibling in this cpu core going down | |
1358 | */ | |
1359 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1360 | c[sibling].booted_cores--; | |
1361 | } | |
1362 | ||
e1367daf LS |
1363 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1364 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1365 | cpus_clear(cpu_sibling_map[cpu]); |
1366 | cpus_clear(cpu_core_map[cpu]); | |
4b89aff9 RS |
1367 | c[cpu].phys_proc_id = 0; |
1368 | c[cpu].cpu_core_id = 0; | |
94605eff | 1369 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1370 | } |
1371 | ||
1372 | int __cpu_disable(void) | |
1373 | { | |
1374 | cpumask_t map = cpu_online_map; | |
1375 | int cpu = smp_processor_id(); | |
1376 | ||
1377 | /* | |
1378 | * Perhaps use cpufreq to drop frequency, but that could go | |
1379 | * into generic code. | |
1380 | * | |
1381 | * We won't take down the boot processor on i386 due to some | |
1382 | * interrupts only being able to be serviced by the BSP. | |
1383 | * Especially so if we're not using an IOAPIC -zwane | |
1384 | */ | |
1385 | if (cpu == 0) | |
1386 | return -EBUSY; | |
4038f901 SL |
1387 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1388 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1389 | clear_local_APIC(); |
f3705136 ZM |
1390 | /* Allow any queued timer interrupts to get serviced */ |
1391 | local_irq_enable(); | |
1392 | mdelay(1); | |
1393 | local_irq_disable(); | |
1394 | ||
e1367daf LS |
1395 | remove_siblinginfo(cpu); |
1396 | ||
f3705136 ZM |
1397 | cpu_clear(cpu, map); |
1398 | fixup_irqs(map); | |
1399 | /* It's now safe to remove this processor from the online map */ | |
1400 | cpu_clear(cpu, cpu_online_map); | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | void __cpu_die(unsigned int cpu) | |
1405 | { | |
1406 | /* We don't do anything here: idle task is faking death itself. */ | |
1407 | unsigned int i; | |
1408 | ||
1409 | for (i = 0; i < 10; i++) { | |
1410 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1411 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1412 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1413 | if (1 == num_online_cpus()) |
1414 | alternatives_smp_switch(0); | |
f3705136 | 1415 | return; |
e1367daf | 1416 | } |
aeb8397b | 1417 | msleep(100); |
1da177e4 | 1418 | } |
f3705136 ZM |
1419 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1420 | } | |
1421 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1422 | int __cpu_disable(void) | |
1423 | { | |
1424 | return -ENOSYS; | |
1425 | } | |
1da177e4 | 1426 | |
f3705136 ZM |
1427 | void __cpu_die(unsigned int cpu) |
1428 | { | |
1429 | /* We said "no" in __cpu_disable */ | |
1430 | BUG(); | |
1431 | } | |
1432 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1433 | ||
1434 | int __devinit __cpu_up(unsigned int cpu) | |
1435 | { | |
34f361ad AR |
1436 | #ifdef CONFIG_HOTPLUG_CPU |
1437 | int ret=0; | |
1438 | ||
1439 | /* | |
1440 | * We do warm boot only on cpus that had booted earlier | |
1441 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1442 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1443 | * when a cpu is taken offline from cpu_exit_clear(). | |
1444 | */ | |
1445 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1446 | ret = __smp_prepare_cpu(cpu); | |
1447 | ||
1448 | if (ret) | |
1449 | return -EIO; | |
1450 | #endif | |
1451 | ||
1da177e4 LT |
1452 | /* In case one didn't come up */ |
1453 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1454 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1455 | local_irq_enable(); |
1456 | return -EIO; | |
1457 | } | |
1458 | ||
1459 | local_irq_enable(); | |
e1367daf | 1460 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1461 | /* Unleash the CPU! */ |
1462 | cpu_set(cpu, smp_commenced_mask); | |
1463 | while (!cpu_isset(cpu, cpu_online_map)) | |
18698917 | 1464 | cpu_relax(); |
1da177e4 LT |
1465 | return 0; |
1466 | } | |
1467 | ||
1468 | void __init smp_cpus_done(unsigned int max_cpus) | |
1469 | { | |
1470 | #ifdef CONFIG_X86_IO_APIC | |
1471 | setup_ioapic_dest(); | |
1472 | #endif | |
1473 | zap_low_mappings(); | |
e1367daf | 1474 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1475 | /* |
1476 | * Disable executability of the SMP trampoline: | |
1477 | */ | |
1478 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1479 | #endif |
1da177e4 LT |
1480 | } |
1481 | ||
1482 | void __init smp_intr_init(void) | |
1483 | { | |
1484 | /* | |
1485 | * IRQ0 must be given a fixed assignment and initialized, | |
1486 | * because it's used before the IO-APIC is set up. | |
1487 | */ | |
1488 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1489 | ||
1490 | /* | |
1491 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1492 | * IPI, driven by wakeup. | |
1493 | */ | |
1494 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1495 | ||
1496 | /* IPI for invalidation */ | |
1497 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1498 | ||
1499 | /* IPI for generic function call */ | |
1500 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1501 | } | |
1a3f239d RR |
1502 | |
1503 | /* | |
1504 | * If the BIOS enumerates physical processors before logical, | |
1505 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1506 | */ | |
1507 | static int __init parse_maxcpus(char *arg) | |
1508 | { | |
1509 | extern unsigned int maxcpus; | |
1510 | ||
1511 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1512 | return 0; | |
1513 | } | |
1514 | early_param("maxcpus", parse_maxcpus); |