Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
43 | #include <linux/smp_lock.h> | |
1da177e4 | 44 | #include <linux/bootmem.h> |
f3705136 ZM |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpu.h> | |
47 | #include <linux/percpu.h> | |
1da177e4 LT |
48 | |
49 | #include <linux/delay.h> | |
50 | #include <linux/mc146818rtc.h> | |
51 | #include <asm/tlbflush.h> | |
52 | #include <asm/desc.h> | |
53 | #include <asm/arch_hooks.h> | |
3e4ff115 | 54 | #include <asm/nmi.h> |
1da177e4 LT |
55 | |
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
59 | ||
60 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 61 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
129f6946 AD |
65 | #ifdef CONFIG_X86_HT |
66 | EXPORT_SYMBOL(smp_num_siblings); | |
67 | #endif | |
d720803a | 68 | |
1e9f28fa SS |
69 | /* Last level cache ID of each logical CPU */ |
70 | int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
71 | ||
94605eff | 72 | /* representing HT siblings of each logical CPU */ |
6c036527 | 73 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
74 | EXPORT_SYMBOL(cpu_sibling_map); |
75 | ||
94605eff | 76 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 77 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
78 | EXPORT_SYMBOL(cpu_core_map); |
79 | ||
1da177e4 | 80 | /* bitmap of online cpus */ |
6c036527 | 81 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 82 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
83 | |
84 | cpumask_t cpu_callin_map; | |
85 | cpumask_t cpu_callout_map; | |
129f6946 | 86 | EXPORT_SYMBOL(cpu_callout_map); |
4ad8d383 ZM |
87 | cpumask_t cpu_possible_map; |
88 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
89 | static cpumask_t smp_commenced_mask; |
90 | ||
e1367daf LS |
91 | /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there |
92 | * is no way to resync one AP against BP. TBD: for prescott and above, we | |
93 | * should use IA64's algorithm | |
94 | */ | |
95 | static int __devinitdata tsc_sync_disabled; | |
96 | ||
1da177e4 LT |
97 | /* Per CPU bogomips and other parameters */ |
98 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 99 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 100 | |
6c036527 | 101 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
102 | { [0 ... NR_CPUS-1] = 0xff }; |
103 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
104 | ||
105 | /* | |
106 | * Trampoline 80x86 program as an array. | |
107 | */ | |
108 | ||
109 | extern unsigned char trampoline_data []; | |
110 | extern unsigned char trampoline_end []; | |
111 | static unsigned char *trampoline_base; | |
112 | static int trampoline_exec; | |
113 | ||
114 | static void map_cpu_to_logical_apicid(void); | |
115 | ||
f3705136 ZM |
116 | /* State of each CPU. */ |
117 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
118 | ||
1da177e4 LT |
119 | /* |
120 | * Currently trivial. Write the real->protected mode | |
121 | * bootstrap into the page concerned. The caller | |
122 | * has made sure it's suitably aligned. | |
123 | */ | |
124 | ||
0bb3184d | 125 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
126 | { |
127 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
128 | return virt_to_phys(trampoline_base); | |
129 | } | |
130 | ||
131 | /* | |
132 | * We are called very early to get the low memory for the | |
133 | * SMP bootup trampoline page. | |
134 | */ | |
135 | void __init smp_alloc_memory(void) | |
136 | { | |
137 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
138 | /* | |
139 | * Has to be in very low memory so we can execute | |
140 | * real-mode AP code. | |
141 | */ | |
142 | if (__pa(trampoline_base) >= 0x9F000) | |
143 | BUG(); | |
144 | /* | |
145 | * Make the SMP trampoline executable: | |
146 | */ | |
147 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
148 | } | |
149 | ||
150 | /* | |
151 | * The bootstrap kernel entry code has set these up. Save them for | |
152 | * a given CPU | |
153 | */ | |
154 | ||
0bb3184d | 155 | static void __devinit smp_store_cpu_info(int id) |
1da177e4 LT |
156 | { |
157 | struct cpuinfo_x86 *c = cpu_data + id; | |
158 | ||
159 | *c = boot_cpu_data; | |
160 | if (id!=0) | |
161 | identify_cpu(c); | |
162 | /* | |
163 | * Mask B, Pentium, but not Pentium MMX | |
164 | */ | |
165 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
166 | c->x86 == 5 && | |
167 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
168 | c->x86_model <= 3) | |
169 | /* | |
170 | * Remember we have B step Pentia with bugs | |
171 | */ | |
172 | smp_b_stepping = 1; | |
173 | ||
174 | /* | |
175 | * Certain Athlons might work (for various values of 'work') in SMP | |
176 | * but they are not certified as MP capable. | |
177 | */ | |
178 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
179 | ||
180 | /* Athlon 660/661 is valid. */ | |
181 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
182 | goto valid_k7; | |
183 | ||
184 | /* Duron 670 is valid */ | |
185 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
186 | goto valid_k7; | |
187 | ||
188 | /* | |
189 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
190 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
191 | * have the MP bit set. | |
192 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
193 | */ | |
194 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
195 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
196 | (c->x86_model> 7)) | |
197 | if (cpu_has_mp) | |
198 | goto valid_k7; | |
199 | ||
200 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 201 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
202 | } |
203 | ||
204 | valid_k7: | |
205 | ; | |
206 | } | |
207 | ||
208 | /* | |
209 | * TSC synchronization. | |
210 | * | |
211 | * We first check whether all CPUs have their TSC's synchronized, | |
212 | * then we print a warning if not, and always resync. | |
213 | */ | |
214 | ||
c35a7261 AM |
215 | static struct { |
216 | atomic_t start_flag; | |
217 | atomic_t count_start; | |
218 | atomic_t count_stop; | |
219 | unsigned long long values[NR_CPUS]; | |
220 | } tsc __initdata = { | |
221 | .start_flag = ATOMIC_INIT(0), | |
222 | .count_start = ATOMIC_INIT(0), | |
223 | .count_stop = ATOMIC_INIT(0), | |
224 | }; | |
1da177e4 LT |
225 | |
226 | #define NR_LOOPS 5 | |
227 | ||
c35a7261 | 228 | static void __init synchronize_tsc_bp(void) |
1da177e4 LT |
229 | { |
230 | int i; | |
231 | unsigned long long t0; | |
232 | unsigned long long sum, avg; | |
233 | long long delta; | |
a3a255e7 | 234 | unsigned int one_usec; |
1da177e4 LT |
235 | int buggy = 0; |
236 | ||
237 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
238 | ||
239 | /* convert from kcyc/sec to cyc/usec */ | |
240 | one_usec = cpu_khz / 1000; | |
241 | ||
c35a7261 | 242 | atomic_set(&tsc.start_flag, 1); |
1da177e4 LT |
243 | wmb(); |
244 | ||
245 | /* | |
246 | * We loop a few times to get a primed instruction cache, | |
247 | * then the last pass is more or less synchronized and | |
248 | * the BP and APs set their cycle counters to zero all at | |
249 | * once. This reduces the chance of having random offsets | |
250 | * between the processors, and guarantees that the maximum | |
251 | * delay between the cycle counters is never bigger than | |
252 | * the latency of information-passing (cachelines) between | |
253 | * two CPUs. | |
254 | */ | |
255 | for (i = 0; i < NR_LOOPS; i++) { | |
256 | /* | |
257 | * all APs synchronize but they loop on '== num_cpus' | |
258 | */ | |
c35a7261 | 259 | while (atomic_read(&tsc.count_start) != num_booting_cpus()-1) |
18698917 | 260 | cpu_relax(); |
c35a7261 | 261 | atomic_set(&tsc.count_stop, 0); |
1da177e4 LT |
262 | wmb(); |
263 | /* | |
264 | * this lets the APs save their current TSC: | |
265 | */ | |
c35a7261 | 266 | atomic_inc(&tsc.count_start); |
1da177e4 | 267 | |
c35a7261 | 268 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
269 | /* |
270 | * We clear the TSC in the last loop: | |
271 | */ | |
272 | if (i == NR_LOOPS-1) | |
273 | write_tsc(0, 0); | |
274 | ||
275 | /* | |
276 | * Wait for all APs to leave the synchronization point: | |
277 | */ | |
c35a7261 | 278 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1) |
18698917 | 279 | cpu_relax(); |
c35a7261 | 280 | atomic_set(&tsc.count_start, 0); |
1da177e4 | 281 | wmb(); |
c35a7261 | 282 | atomic_inc(&tsc.count_stop); |
1da177e4 LT |
283 | } |
284 | ||
285 | sum = 0; | |
286 | for (i = 0; i < NR_CPUS; i++) { | |
287 | if (cpu_isset(i, cpu_callout_map)) { | |
c35a7261 | 288 | t0 = tsc.values[i]; |
1da177e4 LT |
289 | sum += t0; |
290 | } | |
291 | } | |
292 | avg = sum; | |
293 | do_div(avg, num_booting_cpus()); | |
294 | ||
1da177e4 LT |
295 | for (i = 0; i < NR_CPUS; i++) { |
296 | if (!cpu_isset(i, cpu_callout_map)) | |
297 | continue; | |
c35a7261 | 298 | delta = tsc.values[i] - avg; |
1da177e4 LT |
299 | if (delta < 0) |
300 | delta = -delta; | |
301 | /* | |
302 | * We report bigger than 2 microseconds clock differences. | |
303 | */ | |
304 | if (delta > 2*one_usec) { | |
c35a7261 AM |
305 | long long realdelta; |
306 | ||
1da177e4 LT |
307 | if (!buggy) { |
308 | buggy = 1; | |
309 | printk("\n"); | |
310 | } | |
311 | realdelta = delta; | |
312 | do_div(realdelta, one_usec); | |
c35a7261 | 313 | if (tsc.values[i] < avg) |
1da177e4 LT |
314 | realdelta = -realdelta; |
315 | ||
c35a7261 AM |
316 | if (realdelta) |
317 | printk(KERN_INFO "CPU#%d had %Ld usecs TSC " | |
7f5910ec | 318 | "skew, fixed it up.\n", i, realdelta); |
1da177e4 | 319 | } |
1da177e4 LT |
320 | } |
321 | if (!buggy) | |
322 | printk("passed.\n"); | |
323 | } | |
324 | ||
c35a7261 | 325 | static void __init synchronize_tsc_ap(void) |
1da177e4 LT |
326 | { |
327 | int i; | |
328 | ||
329 | /* | |
330 | * Not every cpu is online at the time | |
331 | * this gets called, so we first wait for the BP to | |
332 | * finish SMP initialization: | |
333 | */ | |
c35a7261 | 334 | while (!atomic_read(&tsc.start_flag)) |
18698917 | 335 | cpu_relax(); |
1da177e4 LT |
336 | |
337 | for (i = 0; i < NR_LOOPS; i++) { | |
c35a7261 AM |
338 | atomic_inc(&tsc.count_start); |
339 | while (atomic_read(&tsc.count_start) != num_booting_cpus()) | |
18698917 | 340 | cpu_relax(); |
1da177e4 | 341 | |
c35a7261 | 342 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
343 | if (i == NR_LOOPS-1) |
344 | write_tsc(0, 0); | |
345 | ||
c35a7261 AM |
346 | atomic_inc(&tsc.count_stop); |
347 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()) | |
18698917 | 348 | cpu_relax(); |
1da177e4 LT |
349 | } |
350 | } | |
351 | #undef NR_LOOPS | |
352 | ||
353 | extern void calibrate_delay(void); | |
354 | ||
355 | static atomic_t init_deasserted; | |
356 | ||
0bb3184d | 357 | static void __devinit smp_callin(void) |
1da177e4 LT |
358 | { |
359 | int cpuid, phys_id; | |
360 | unsigned long timeout; | |
361 | ||
362 | /* | |
363 | * If waken up by an INIT in an 82489DX configuration | |
364 | * we may get here before an INIT-deassert IPI reaches | |
365 | * our local APIC. We have to wait for the IPI or we'll | |
366 | * lock up on an APIC access. | |
367 | */ | |
368 | wait_for_init_deassert(&init_deasserted); | |
369 | ||
370 | /* | |
371 | * (This works even if the APIC is not enabled.) | |
372 | */ | |
373 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
374 | cpuid = smp_processor_id(); | |
375 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
376 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
377 | phys_id, cpuid); | |
378 | BUG(); | |
379 | } | |
380 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
381 | ||
382 | /* | |
383 | * STARTUP IPIs are fragile beasts as they might sometimes | |
384 | * trigger some glue motherboard logic. Complete APIC bus | |
385 | * silence for 1 second, this overestimates the time the | |
386 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
387 | * by a factor of two. This should be enough. | |
388 | */ | |
389 | ||
390 | /* | |
391 | * Waiting 2s total for startup (udelay is not yet working) | |
392 | */ | |
393 | timeout = jiffies + 2*HZ; | |
394 | while (time_before(jiffies, timeout)) { | |
395 | /* | |
396 | * Has the boot CPU finished it's STARTUP sequence? | |
397 | */ | |
398 | if (cpu_isset(cpuid, cpu_callout_map)) | |
399 | break; | |
400 | rep_nop(); | |
401 | } | |
402 | ||
403 | if (!time_before(jiffies, timeout)) { | |
404 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
405 | cpuid); | |
406 | BUG(); | |
407 | } | |
408 | ||
409 | /* | |
410 | * the boot CPU has finished the init stage and is spinning | |
411 | * on callin_map until we finish. We are free to set up this | |
412 | * CPU, first the APIC. (this is probably redundant on most | |
413 | * boards) | |
414 | */ | |
415 | ||
416 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
417 | smp_callin_clear_local_apic(); | |
418 | setup_local_APIC(); | |
419 | map_cpu_to_logical_apicid(); | |
420 | ||
421 | /* | |
422 | * Get our bogomips. | |
423 | */ | |
424 | calibrate_delay(); | |
425 | Dprintk("Stack at about %p\n",&cpuid); | |
426 | ||
427 | /* | |
428 | * Save our processor parameters | |
429 | */ | |
430 | smp_store_cpu_info(cpuid); | |
431 | ||
432 | disable_APIC_timer(); | |
433 | ||
434 | /* | |
435 | * Allow the master to continue. | |
436 | */ | |
437 | cpu_set(cpuid, cpu_callin_map); | |
438 | ||
439 | /* | |
440 | * Synchronize the TSC with the BP | |
441 | */ | |
e1367daf | 442 | if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) |
1da177e4 LT |
443 | synchronize_tsc_ap(); |
444 | } | |
445 | ||
446 | static int cpucount; | |
447 | ||
1e9f28fa SS |
448 | /* maps the cpu to the sched domain representing multi-core */ |
449 | cpumask_t cpu_coregroup_map(int cpu) | |
450 | { | |
451 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
452 | /* | |
453 | * For perf, we return last level cache shared map. | |
5c45bf27 | 454 | * And for power savings, we return cpu_core_map |
1e9f28fa | 455 | */ |
5c45bf27 SS |
456 | if (sched_mc_power_savings || sched_smt_power_savings) |
457 | return cpu_core_map[cpu]; | |
458 | else | |
459 | return c->llc_shared_map; | |
1e9f28fa SS |
460 | } |
461 | ||
94605eff SS |
462 | /* representing cpus for which sibling maps can be computed */ |
463 | static cpumask_t cpu_sibling_setup_map; | |
464 | ||
d720803a LS |
465 | static inline void |
466 | set_cpu_sibling_map(int cpu) | |
467 | { | |
468 | int i; | |
94605eff SS |
469 | struct cpuinfo_x86 *c = cpu_data; |
470 | ||
471 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
472 | |
473 | if (smp_num_siblings > 1) { | |
94605eff | 474 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
4b89aff9 RS |
475 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
476 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
d720803a LS |
477 | cpu_set(i, cpu_sibling_map[cpu]); |
478 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
479 | cpu_set(i, cpu_core_map[cpu]); |
480 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
481 | cpu_set(i, c[cpu].llc_shared_map); |
482 | cpu_set(cpu, c[i].llc_shared_map); | |
d720803a LS |
483 | } |
484 | } | |
485 | } else { | |
486 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
487 | } | |
488 | ||
1e9f28fa SS |
489 | cpu_set(cpu, c[cpu].llc_shared_map); |
490 | ||
94605eff | 491 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 492 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
493 | c[cpu].booted_cores = 1; |
494 | return; | |
495 | } | |
496 | ||
497 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
498 | if (cpu_llc_id[cpu] != BAD_APICID && |
499 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
500 | cpu_set(i, c[cpu].llc_shared_map); | |
501 | cpu_set(cpu, c[i].llc_shared_map); | |
502 | } | |
4b89aff9 | 503 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
504 | cpu_set(i, cpu_core_map[cpu]); |
505 | cpu_set(cpu, cpu_core_map[i]); | |
506 | /* | |
507 | * Does this new cpu bringup a new core? | |
508 | */ | |
509 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
510 | /* | |
511 | * for each core in package, increment | |
512 | * the booted_cores for this new cpu | |
513 | */ | |
514 | if (first_cpu(cpu_sibling_map[i]) == i) | |
515 | c[cpu].booted_cores++; | |
516 | /* | |
517 | * increment the core count for all | |
518 | * the other cpus in this package | |
519 | */ | |
520 | if (i != cpu) | |
521 | c[i].booted_cores++; | |
522 | } else if (i != cpu && !c[cpu].booted_cores) | |
523 | c[cpu].booted_cores = c[i].booted_cores; | |
524 | } | |
d720803a LS |
525 | } |
526 | } | |
527 | ||
1da177e4 LT |
528 | /* |
529 | * Activate a secondary processor. | |
530 | */ | |
0bb3184d | 531 | static void __devinit start_secondary(void *unused) |
1da177e4 LT |
532 | { |
533 | /* | |
534 | * Dont put anything before smp_callin(), SMP | |
535 | * booting is too fragile that we want to limit the | |
536 | * things done here to the most necessary things. | |
537 | */ | |
538 | cpu_init(); | |
5bfb5d69 | 539 | preempt_disable(); |
1da177e4 LT |
540 | smp_callin(); |
541 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
542 | rep_nop(); | |
543 | setup_secondary_APIC_clock(); | |
544 | if (nmi_watchdog == NMI_IO_APIC) { | |
545 | disable_8259A_irq(0); | |
546 | enable_NMI_through_LVT0(NULL); | |
547 | enable_8259A_irq(0); | |
548 | } | |
549 | enable_APIC_timer(); | |
550 | /* | |
551 | * low-memory mappings have been cleared, flush them from | |
552 | * the local TLBs too. | |
553 | */ | |
554 | local_flush_tlb(); | |
6fe940d6 | 555 | |
d720803a LS |
556 | /* This must be done before setting cpu_online_map */ |
557 | set_cpu_sibling_map(raw_smp_processor_id()); | |
558 | wmb(); | |
559 | ||
6fe940d6 LS |
560 | /* |
561 | * We need to hold call_lock, so there is no inconsistency | |
562 | * between the time smp_call_function() determines number of | |
563 | * IPI receipients, and the time when the determination is made | |
564 | * for which cpus receive the IPI. Holding this | |
565 | * lock helps us to not include this cpu in a currently in progress | |
566 | * smp_call_function(). | |
567 | */ | |
568 | lock_ipi_call_lock(); | |
1da177e4 | 569 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 570 | unlock_ipi_call_lock(); |
e1367daf | 571 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
572 | |
573 | /* We can take interrupts now: we're officially "up". */ | |
574 | local_irq_enable(); | |
575 | ||
576 | wmb(); | |
577 | cpu_idle(); | |
578 | } | |
579 | ||
580 | /* | |
581 | * Everything has been set up for the secondary | |
582 | * CPUs - they just need to reload everything | |
583 | * from the task structure | |
584 | * This function must not return. | |
585 | */ | |
0bb3184d | 586 | void __devinit initialize_secondary(void) |
1da177e4 LT |
587 | { |
588 | /* | |
589 | * We don't actually need to load the full TSS, | |
590 | * basically just the stack pointer and the eip. | |
591 | */ | |
592 | ||
593 | asm volatile( | |
594 | "movl %0,%%esp\n\t" | |
595 | "jmp *%1" | |
596 | : | |
597 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
598 | } | |
599 | ||
600 | extern struct { | |
601 | void * esp; | |
602 | unsigned short ss; | |
603 | } stack_start; | |
604 | ||
605 | #ifdef CONFIG_NUMA | |
606 | ||
607 | /* which logical CPUs are on which nodes */ | |
6c036527 | 608 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 LT |
609 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
610 | /* which node each logical CPU is on */ | |
6c036527 | 611 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
612 | EXPORT_SYMBOL(cpu_2_node); |
613 | ||
614 | /* set up a mapping between cpu and node. */ | |
615 | static inline void map_cpu_to_node(int cpu, int node) | |
616 | { | |
617 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
618 | cpu_set(cpu, node_2_cpu_mask[node]); | |
619 | cpu_2_node[cpu] = node; | |
620 | } | |
621 | ||
622 | /* undo a mapping between cpu and node. */ | |
623 | static inline void unmap_cpu_to_node(int cpu) | |
624 | { | |
625 | int node; | |
626 | ||
627 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
628 | for (node = 0; node < MAX_NUMNODES; node ++) | |
629 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
630 | cpu_2_node[cpu] = 0; | |
631 | } | |
632 | #else /* !CONFIG_NUMA */ | |
633 | ||
634 | #define map_cpu_to_node(cpu, node) ({}) | |
635 | #define unmap_cpu_to_node(cpu) ({}) | |
636 | ||
637 | #endif /* CONFIG_NUMA */ | |
638 | ||
6c036527 | 639 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
640 | |
641 | static void map_cpu_to_logical_apicid(void) | |
642 | { | |
643 | int cpu = smp_processor_id(); | |
644 | int apicid = logical_smp_processor_id(); | |
bfa0e9a0 | 645 | int node = apicid_to_node(apicid); |
646 | ||
647 | if (!node_online(node)) | |
648 | node = first_online_node; | |
1da177e4 LT |
649 | |
650 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 651 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
652 | } |
653 | ||
654 | static void unmap_cpu_to_logical_apicid(int cpu) | |
655 | { | |
656 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
657 | unmap_cpu_to_node(cpu); | |
658 | } | |
659 | ||
660 | #if APIC_DEBUG | |
661 | static inline void __inquire_remote_apic(int apicid) | |
662 | { | |
663 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
664 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
665 | int timeout, status; | |
666 | ||
667 | printk("Inquiring remote APIC #%d...\n", apicid); | |
668 | ||
38e548ee | 669 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
670 | printk("... APIC #%d %s: ", apicid, names[i]); |
671 | ||
672 | /* | |
673 | * Wait for idle. | |
674 | */ | |
675 | apic_wait_icr_idle(); | |
676 | ||
677 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
678 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
679 | ||
680 | timeout = 0; | |
681 | do { | |
682 | udelay(100); | |
683 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
684 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
685 | ||
686 | switch (status) { | |
687 | case APIC_ICR_RR_VALID: | |
688 | status = apic_read(APIC_RRR); | |
689 | printk("%08x\n", status); | |
690 | break; | |
691 | default: | |
692 | printk("failed\n"); | |
693 | } | |
694 | } | |
695 | } | |
696 | #endif | |
697 | ||
698 | #ifdef WAKE_SECONDARY_VIA_NMI | |
699 | /* | |
700 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
701 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
702 | * won't ... remember to clear down the APIC, etc later. | |
703 | */ | |
0bb3184d | 704 | static int __devinit |
1da177e4 LT |
705 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
706 | { | |
707 | unsigned long send_status = 0, accept_status = 0; | |
708 | int timeout, maxlvt; | |
709 | ||
710 | /* Target chip */ | |
711 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
712 | ||
713 | /* Boot on the stack */ | |
714 | /* Kick the second */ | |
715 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
716 | ||
717 | Dprintk("Waiting for send to finish...\n"); | |
718 | timeout = 0; | |
719 | do { | |
720 | Dprintk("+"); | |
721 | udelay(100); | |
722 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
723 | } while (send_status && (timeout++ < 1000)); | |
724 | ||
725 | /* | |
726 | * Give the other CPU some time to accept the IPI. | |
727 | */ | |
728 | udelay(200); | |
729 | /* | |
730 | * Due to the Pentium erratum 3AP. | |
731 | */ | |
732 | maxlvt = get_maxlvt(); | |
733 | if (maxlvt > 3) { | |
734 | apic_read_around(APIC_SPIV); | |
735 | apic_write(APIC_ESR, 0); | |
736 | } | |
737 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
738 | Dprintk("NMI sent.\n"); | |
739 | ||
740 | if (send_status) | |
741 | printk("APIC never delivered???\n"); | |
742 | if (accept_status) | |
743 | printk("APIC delivery error (%lx).\n", accept_status); | |
744 | ||
745 | return (send_status | accept_status); | |
746 | } | |
747 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
748 | ||
749 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 750 | static int __devinit |
1da177e4 LT |
751 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
752 | { | |
753 | unsigned long send_status = 0, accept_status = 0; | |
754 | int maxlvt, timeout, num_starts, j; | |
755 | ||
756 | /* | |
757 | * Be paranoid about clearing APIC errors. | |
758 | */ | |
759 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
760 | apic_read_around(APIC_SPIV); | |
761 | apic_write(APIC_ESR, 0); | |
762 | apic_read(APIC_ESR); | |
763 | } | |
764 | ||
765 | Dprintk("Asserting INIT.\n"); | |
766 | ||
767 | /* | |
768 | * Turn INIT on target chip | |
769 | */ | |
770 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
771 | ||
772 | /* | |
773 | * Send IPI | |
774 | */ | |
775 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
776 | | APIC_DM_INIT); | |
777 | ||
778 | Dprintk("Waiting for send to finish...\n"); | |
779 | timeout = 0; | |
780 | do { | |
781 | Dprintk("+"); | |
782 | udelay(100); | |
783 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
784 | } while (send_status && (timeout++ < 1000)); | |
785 | ||
786 | mdelay(10); | |
787 | ||
788 | Dprintk("Deasserting INIT.\n"); | |
789 | ||
790 | /* Target chip */ | |
791 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
792 | ||
793 | /* Send IPI */ | |
794 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
795 | ||
796 | Dprintk("Waiting for send to finish...\n"); | |
797 | timeout = 0; | |
798 | do { | |
799 | Dprintk("+"); | |
800 | udelay(100); | |
801 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
802 | } while (send_status && (timeout++ < 1000)); | |
803 | ||
804 | atomic_set(&init_deasserted, 1); | |
805 | ||
806 | /* | |
807 | * Should we send STARTUP IPIs ? | |
808 | * | |
809 | * Determine this based on the APIC version. | |
810 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
811 | */ | |
812 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
813 | num_starts = 2; | |
814 | else | |
815 | num_starts = 0; | |
816 | ||
817 | /* | |
818 | * Run STARTUP IPI loop. | |
819 | */ | |
820 | Dprintk("#startup loops: %d.\n", num_starts); | |
821 | ||
822 | maxlvt = get_maxlvt(); | |
823 | ||
824 | for (j = 1; j <= num_starts; j++) { | |
825 | Dprintk("Sending STARTUP #%d.\n",j); | |
826 | apic_read_around(APIC_SPIV); | |
827 | apic_write(APIC_ESR, 0); | |
828 | apic_read(APIC_ESR); | |
829 | Dprintk("After apic_write.\n"); | |
830 | ||
831 | /* | |
832 | * STARTUP IPI | |
833 | */ | |
834 | ||
835 | /* Target chip */ | |
836 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
837 | ||
838 | /* Boot on the stack */ | |
839 | /* Kick the second */ | |
840 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
841 | | (start_eip >> 12)); | |
842 | ||
843 | /* | |
844 | * Give the other CPU some time to accept the IPI. | |
845 | */ | |
846 | udelay(300); | |
847 | ||
848 | Dprintk("Startup point 1.\n"); | |
849 | ||
850 | Dprintk("Waiting for send to finish...\n"); | |
851 | timeout = 0; | |
852 | do { | |
853 | Dprintk("+"); | |
854 | udelay(100); | |
855 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
856 | } while (send_status && (timeout++ < 1000)); | |
857 | ||
858 | /* | |
859 | * Give the other CPU some time to accept the IPI. | |
860 | */ | |
861 | udelay(200); | |
862 | /* | |
863 | * Due to the Pentium erratum 3AP. | |
864 | */ | |
865 | if (maxlvt > 3) { | |
866 | apic_read_around(APIC_SPIV); | |
867 | apic_write(APIC_ESR, 0); | |
868 | } | |
869 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
870 | if (send_status || accept_status) | |
871 | break; | |
872 | } | |
873 | Dprintk("After Startup.\n"); | |
874 | ||
875 | if (send_status) | |
876 | printk("APIC never delivered???\n"); | |
877 | if (accept_status) | |
878 | printk("APIC delivery error (%lx).\n", accept_status); | |
879 | ||
880 | return (send_status | accept_status); | |
881 | } | |
882 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
883 | ||
884 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
885 | static inline int alloc_cpu_id(void) |
886 | { | |
887 | cpumask_t tmp_map; | |
888 | int cpu; | |
889 | cpus_complement(tmp_map, cpu_present_map); | |
890 | cpu = first_cpu(tmp_map); | |
891 | if (cpu >= NR_CPUS) | |
892 | return -ENODEV; | |
893 | return cpu; | |
894 | } | |
895 | ||
896 | #ifdef CONFIG_HOTPLUG_CPU | |
897 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
898 | static inline struct task_struct * alloc_idle_task(int cpu) | |
899 | { | |
900 | struct task_struct *idle; | |
901 | ||
902 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
903 | /* initialize thread_struct. we really want to avoid destroy | |
904 | * idle tread | |
905 | */ | |
07b047fc | 906 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
907 | init_idle(idle, cpu); |
908 | return idle; | |
909 | } | |
910 | idle = fork_idle(cpu); | |
911 | ||
912 | if (!IS_ERR(idle)) | |
913 | cpu_idle_tasks[cpu] = idle; | |
914 | return idle; | |
915 | } | |
916 | #else | |
917 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
918 | #endif | |
1da177e4 | 919 | |
e1367daf | 920 | static int __devinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
921 | /* |
922 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
923 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
924 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
925 | */ | |
926 | { | |
927 | struct task_struct *idle; | |
928 | unsigned long boot_error; | |
e1367daf | 929 | int timeout; |
1da177e4 LT |
930 | unsigned long start_eip; |
931 | unsigned short nmi_high = 0, nmi_low = 0; | |
932 | ||
e1367daf | 933 | ++cpucount; |
9a0b5817 | 934 | alternatives_smp_switch(1); |
e1367daf | 935 | |
1da177e4 LT |
936 | /* |
937 | * We can't use kernel_thread since we must avoid to | |
938 | * reschedule the child. | |
939 | */ | |
e1367daf | 940 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
941 | if (IS_ERR(idle)) |
942 | panic("failed fork for CPU %d", cpu); | |
943 | idle->thread.eip = (unsigned long) start_secondary; | |
944 | /* start_eip had better be page-aligned! */ | |
945 | start_eip = setup_trampoline(); | |
946 | ||
947 | /* So we see what's up */ | |
948 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
949 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
950 | stack_start.esp = (void *) idle->thread.esp; | |
951 | ||
952 | irq_ctx_init(cpu); | |
953 | ||
954 | /* | |
955 | * This grunge runs the startup process for | |
956 | * the targeted processor. | |
957 | */ | |
958 | ||
959 | atomic_set(&init_deasserted, 0); | |
960 | ||
961 | Dprintk("Setting warm reset code and vector.\n"); | |
962 | ||
963 | store_NMI_vector(&nmi_high, &nmi_low); | |
964 | ||
965 | smpboot_setup_warm_reset_vector(start_eip); | |
966 | ||
967 | /* | |
968 | * Starting actual IPI sequence... | |
969 | */ | |
970 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
971 | ||
972 | if (!boot_error) { | |
973 | /* | |
974 | * allow APs to start initializing. | |
975 | */ | |
976 | Dprintk("Before Callout %d.\n", cpu); | |
977 | cpu_set(cpu, cpu_callout_map); | |
978 | Dprintk("After Callout %d.\n", cpu); | |
979 | ||
980 | /* | |
981 | * Wait 5s total for a response | |
982 | */ | |
983 | for (timeout = 0; timeout < 50000; timeout++) { | |
984 | if (cpu_isset(cpu, cpu_callin_map)) | |
985 | break; /* It has booted */ | |
986 | udelay(100); | |
987 | } | |
988 | ||
989 | if (cpu_isset(cpu, cpu_callin_map)) { | |
990 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
991 | Dprintk("OK.\n"); | |
992 | printk("CPU%d: ", cpu); | |
993 | print_cpu_info(&cpu_data[cpu]); | |
994 | Dprintk("CPU has booted.\n"); | |
995 | } else { | |
996 | boot_error= 1; | |
997 | if (*((volatile unsigned char *)trampoline_base) | |
998 | == 0xA5) | |
999 | /* trampoline started but...? */ | |
1000 | printk("Stuck ??\n"); | |
1001 | else | |
1002 | /* trampoline code not run */ | |
1003 | printk("Not responding.\n"); | |
1004 | inquire_remote_apic(apicid); | |
1005 | } | |
1006 | } | |
e1367daf | 1007 | |
1da177e4 LT |
1008 | if (boot_error) { |
1009 | /* Try to put things back the way they were before ... */ | |
1010 | unmap_cpu_to_logical_apicid(cpu); | |
1011 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
1012 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
1013 | cpucount--; | |
e1367daf LS |
1014 | } else { |
1015 | x86_cpu_to_apicid[cpu] = apicid; | |
1016 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
1017 | } |
1018 | ||
1019 | /* mark "stuck" area as not stuck */ | |
1020 | *((volatile unsigned long *)trampoline_base) = 0; | |
1021 | ||
1022 | return boot_error; | |
1023 | } | |
1024 | ||
e1367daf LS |
1025 | #ifdef CONFIG_HOTPLUG_CPU |
1026 | void cpu_exit_clear(void) | |
1027 | { | |
1028 | int cpu = raw_smp_processor_id(); | |
1029 | ||
1030 | idle_task_exit(); | |
1031 | ||
1032 | cpucount --; | |
1033 | cpu_uninit(); | |
1034 | irq_ctx_exit(cpu); | |
1035 | ||
1036 | cpu_clear(cpu, cpu_callout_map); | |
1037 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
1038 | |
1039 | cpu_clear(cpu, smp_commenced_mask); | |
1040 | unmap_cpu_to_logical_apicid(cpu); | |
1041 | } | |
1042 | ||
1043 | struct warm_boot_cpu_info { | |
1044 | struct completion *complete; | |
1045 | int apicid; | |
1046 | int cpu; | |
1047 | }; | |
1048 | ||
34f361ad | 1049 | static void __cpuinit do_warm_boot_cpu(void *p) |
e1367daf LS |
1050 | { |
1051 | struct warm_boot_cpu_info *info = p; | |
1052 | do_boot_cpu(info->apicid, info->cpu); | |
1053 | complete(info->complete); | |
1054 | } | |
1055 | ||
34f361ad | 1056 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf LS |
1057 | { |
1058 | DECLARE_COMPLETION(done); | |
1059 | struct warm_boot_cpu_info info; | |
1060 | struct work_struct task; | |
1061 | int apicid, ret; | |
bd9e0b74 | 1062 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
e1367daf | 1063 | |
e1367daf LS |
1064 | apicid = x86_cpu_to_apicid[cpu]; |
1065 | if (apicid == BAD_APICID) { | |
1066 | ret = -ENODEV; | |
1067 | goto exit; | |
1068 | } | |
1069 | ||
bd9e0b74 SL |
1070 | /* |
1071 | * the CPU isn't initialized at boot time, allocate gdt table here. | |
1072 | * cpu_init will initialize it | |
1073 | */ | |
1074 | if (!cpu_gdt_descr->address) { | |
1075 | cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL); | |
1076 | if (!cpu_gdt_descr->address) | |
1077 | printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu); | |
1078 | ret = -ENOMEM; | |
1079 | goto exit; | |
1080 | } | |
1081 | ||
e1367daf LS |
1082 | info.complete = &done; |
1083 | info.apicid = apicid; | |
1084 | info.cpu = cpu; | |
1085 | INIT_WORK(&task, do_warm_boot_cpu, &info); | |
1086 | ||
1087 | tsc_sync_disabled = 1; | |
1088 | ||
1089 | /* init low mem mapping */ | |
d7271b14 ZA |
1090 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
1091 | KERNEL_PGD_PTRS); | |
e1367daf LS |
1092 | flush_tlb_all(); |
1093 | schedule_work(&task); | |
1094 | wait_for_completion(&done); | |
1095 | ||
1096 | tsc_sync_disabled = 0; | |
1097 | zap_low_mappings(); | |
1098 | ret = 0; | |
1099 | exit: | |
e1367daf LS |
1100 | return ret; |
1101 | } | |
1102 | #endif | |
1103 | ||
1da177e4 LT |
1104 | static void smp_tune_scheduling (void) |
1105 | { | |
1106 | unsigned long cachesize; /* kB */ | |
1107 | unsigned long bandwidth = 350; /* MB/s */ | |
1108 | /* | |
1109 | * Rough estimation for SMP scheduling, this is the number of | |
1110 | * cycles it takes for a fully memory-limited process to flush | |
1111 | * the SMP-local cache. | |
1112 | * | |
1113 | * (For a P5 this pretty much means we will choose another idle | |
1114 | * CPU almost always at wakeup time (this is due to the small | |
1115 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
1116 | * the cache size) | |
1117 | */ | |
1118 | ||
1119 | if (!cpu_khz) { | |
1120 | /* | |
1121 | * this basically disables processor-affinity | |
1122 | * scheduling on SMP without a TSC. | |
1123 | */ | |
1124 | return; | |
1125 | } else { | |
1126 | cachesize = boot_cpu_data.x86_cache_size; | |
1127 | if (cachesize == -1) { | |
1128 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
1129 | bandwidth = 100; | |
1130 | } | |
198e2f18 | 1131 | max_cache_size = cachesize * 1024; |
1da177e4 LT |
1132 | } |
1133 | } | |
1134 | ||
1135 | /* | |
1136 | * Cycle through the processors sending APIC IPIs to boot each. | |
1137 | */ | |
1138 | ||
1139 | static int boot_cpu_logical_apicid; | |
1140 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1141 | void *xquad_portio; | |
129f6946 AD |
1142 | #ifdef CONFIG_X86_NUMAQ |
1143 | EXPORT_SYMBOL(xquad_portio); | |
1144 | #endif | |
1da177e4 | 1145 | |
1da177e4 LT |
1146 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1147 | { | |
1148 | int apicid, cpu, bit, kicked; | |
1149 | unsigned long bogosum = 0; | |
1150 | ||
1151 | /* | |
1152 | * Setup boot CPU information | |
1153 | */ | |
1154 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1155 | printk("CPU%d: ", 0); | |
1156 | print_cpu_info(&cpu_data[0]); | |
1157 | ||
1e4c85f9 | 1158 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1159 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1160 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1161 | ||
1162 | current_thread_info()->cpu = 0; | |
1163 | smp_tune_scheduling(); | |
1da177e4 | 1164 | |
94605eff | 1165 | set_cpu_sibling_map(0); |
3dd9d514 | 1166 | |
1da177e4 LT |
1167 | /* |
1168 | * If we couldn't find an SMP configuration at boot time, | |
1169 | * get out of here now! | |
1170 | */ | |
1171 | if (!smp_found_config && !acpi_lapic) { | |
1172 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1173 | smpboot_clear_io_apic_irqs(); |
1174 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1175 | if (APIC_init_uniprocessor()) | |
1176 | printk(KERN_NOTICE "Local APIC not detected." | |
1177 | " Using dummy APIC emulation.\n"); | |
1178 | map_cpu_to_logical_apicid(); | |
1179 | cpu_set(0, cpu_sibling_map[0]); | |
1180 | cpu_set(0, cpu_core_map[0]); | |
1181 | return; | |
1182 | } | |
1183 | ||
1184 | /* | |
1185 | * Should not be necessary because the MP table should list the boot | |
1186 | * CPU too, but we do it for the sake of robustness anyway. | |
1187 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1188 | */ | |
1189 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1190 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1191 | boot_cpu_physical_apicid); | |
1192 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * If we couldn't find a local APIC, then get out of here now! | |
1197 | */ | |
1198 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1199 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1200 | boot_cpu_physical_apicid); | |
1201 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1202 | smpboot_clear_io_apic_irqs(); | |
1203 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1204 | cpu_set(0, cpu_sibling_map[0]); | |
1205 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1206 | return; |
1207 | } | |
1208 | ||
1e4c85f9 LT |
1209 | verify_local_APIC(); |
1210 | ||
1da177e4 LT |
1211 | /* |
1212 | * If SMP should be disabled, then really disable it! | |
1213 | */ | |
1e4c85f9 LT |
1214 | if (!max_cpus) { |
1215 | smp_found_config = 0; | |
1216 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1217 | smpboot_clear_io_apic_irqs(); | |
1218 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1219 | cpu_set(0, cpu_sibling_map[0]); | |
1220 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1221 | return; |
1222 | } | |
1223 | ||
1e4c85f9 LT |
1224 | connect_bsp_APIC(); |
1225 | setup_local_APIC(); | |
1226 | map_cpu_to_logical_apicid(); | |
1227 | ||
1228 | ||
1da177e4 LT |
1229 | setup_portio_remap(); |
1230 | ||
1231 | /* | |
1232 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1233 | * | |
1234 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1235 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1236 | * clustered apic ID. | |
1237 | */ | |
1238 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1239 | ||
1240 | kicked = 1; | |
1241 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1242 | apicid = cpu_present_to_apicid(bit); | |
1243 | /* | |
1244 | * Don't even attempt to start the boot CPU! | |
1245 | */ | |
1246 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1247 | continue; | |
1248 | ||
1249 | if (!check_apicid_present(bit)) | |
1250 | continue; | |
1251 | if (max_cpus <= cpucount+1) | |
1252 | continue; | |
1253 | ||
e1367daf | 1254 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1255 | printk("CPU #%d not responding - cannot use it.\n", |
1256 | apicid); | |
1257 | else | |
1258 | ++kicked; | |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * Cleanup possible dangling ends... | |
1263 | */ | |
1264 | smpboot_restore_warm_reset_vector(); | |
1265 | ||
1266 | /* | |
1267 | * Allow the user to impress friends. | |
1268 | */ | |
1269 | Dprintk("Before bogomips.\n"); | |
1270 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1271 | if (cpu_isset(cpu, cpu_callout_map)) | |
1272 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1273 | printk(KERN_INFO | |
1274 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1275 | cpucount+1, | |
1276 | bogosum/(500000/HZ), | |
1277 | (bogosum/(5000/HZ))%100); | |
1278 | ||
1279 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1280 | ||
1281 | if (smp_b_stepping) | |
1282 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1283 | ||
1284 | /* | |
1285 | * Don't taint if we are running SMP kernel on a single non-MP | |
1286 | * approved Athlon | |
1287 | */ | |
1288 | if (tainted & TAINT_UNSAFE_SMP) { | |
1289 | if (cpucount) | |
1290 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1291 | else | |
1292 | tainted &= ~TAINT_UNSAFE_SMP; | |
1293 | } | |
1294 | ||
1295 | Dprintk("Boot done.\n"); | |
1296 | ||
1297 | /* | |
1298 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1299 | * efficiently. | |
1300 | */ | |
3dd9d514 | 1301 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1302 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1303 | cpus_clear(cpu_core_map[cpu]); |
1304 | } | |
1da177e4 | 1305 | |
d720803a LS |
1306 | cpu_set(0, cpu_sibling_map[0]); |
1307 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1308 | |
1e4c85f9 LT |
1309 | smpboot_setup_io_apic(); |
1310 | ||
1311 | setup_boot_APIC_clock(); | |
1312 | ||
1da177e4 LT |
1313 | /* |
1314 | * Synchronize the TSC with the AP | |
1315 | */ | |
1316 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1317 | synchronize_tsc_bp(); | |
1318 | } | |
1319 | ||
1320 | /* These are wrappers to interface to the new boot process. Someone | |
1321 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1322 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1323 | { | |
f3705136 ZM |
1324 | smp_commenced_mask = cpumask_of_cpu(0); |
1325 | cpu_callin_map = cpumask_of_cpu(0); | |
1326 | mb(); | |
1da177e4 LT |
1327 | smp_boot_cpus(max_cpus); |
1328 | } | |
1329 | ||
1330 | void __devinit smp_prepare_boot_cpu(void) | |
1331 | { | |
1332 | cpu_set(smp_processor_id(), cpu_online_map); | |
1333 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1334 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1335 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1336 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1337 | } |
1338 | ||
f3705136 | 1339 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1340 | static void |
1341 | remove_siblinginfo(int cpu) | |
1da177e4 | 1342 | { |
e1367daf | 1343 | int sibling; |
94605eff | 1344 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1345 | |
94605eff SS |
1346 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1347 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1348 | /* | |
1349 | * last thread sibling in this cpu core going down | |
1350 | */ | |
1351 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1352 | c[sibling].booted_cores--; | |
1353 | } | |
1354 | ||
e1367daf LS |
1355 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1356 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1357 | cpus_clear(cpu_sibling_map[cpu]); |
1358 | cpus_clear(cpu_core_map[cpu]); | |
4b89aff9 RS |
1359 | c[cpu].phys_proc_id = 0; |
1360 | c[cpu].cpu_core_id = 0; | |
94605eff | 1361 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1362 | } |
1363 | ||
1364 | int __cpu_disable(void) | |
1365 | { | |
1366 | cpumask_t map = cpu_online_map; | |
1367 | int cpu = smp_processor_id(); | |
1368 | ||
1369 | /* | |
1370 | * Perhaps use cpufreq to drop frequency, but that could go | |
1371 | * into generic code. | |
1372 | * | |
1373 | * We won't take down the boot processor on i386 due to some | |
1374 | * interrupts only being able to be serviced by the BSP. | |
1375 | * Especially so if we're not using an IOAPIC -zwane | |
1376 | */ | |
1377 | if (cpu == 0) | |
1378 | return -EBUSY; | |
1379 | ||
5e9ef02e | 1380 | clear_local_APIC(); |
f3705136 ZM |
1381 | /* Allow any queued timer interrupts to get serviced */ |
1382 | local_irq_enable(); | |
1383 | mdelay(1); | |
1384 | local_irq_disable(); | |
1385 | ||
e1367daf LS |
1386 | remove_siblinginfo(cpu); |
1387 | ||
f3705136 ZM |
1388 | cpu_clear(cpu, map); |
1389 | fixup_irqs(map); | |
1390 | /* It's now safe to remove this processor from the online map */ | |
1391 | cpu_clear(cpu, cpu_online_map); | |
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | void __cpu_die(unsigned int cpu) | |
1396 | { | |
1397 | /* We don't do anything here: idle task is faking death itself. */ | |
1398 | unsigned int i; | |
1399 | ||
1400 | for (i = 0; i < 10; i++) { | |
1401 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1402 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1403 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1404 | if (1 == num_online_cpus()) |
1405 | alternatives_smp_switch(0); | |
f3705136 | 1406 | return; |
e1367daf | 1407 | } |
aeb8397b | 1408 | msleep(100); |
1da177e4 | 1409 | } |
f3705136 ZM |
1410 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1411 | } | |
1412 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1413 | int __cpu_disable(void) | |
1414 | { | |
1415 | return -ENOSYS; | |
1416 | } | |
1da177e4 | 1417 | |
f3705136 ZM |
1418 | void __cpu_die(unsigned int cpu) |
1419 | { | |
1420 | /* We said "no" in __cpu_disable */ | |
1421 | BUG(); | |
1422 | } | |
1423 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1424 | ||
1425 | int __devinit __cpu_up(unsigned int cpu) | |
1426 | { | |
34f361ad AR |
1427 | #ifdef CONFIG_HOTPLUG_CPU |
1428 | int ret=0; | |
1429 | ||
1430 | /* | |
1431 | * We do warm boot only on cpus that had booted earlier | |
1432 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1433 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1434 | * when a cpu is taken offline from cpu_exit_clear(). | |
1435 | */ | |
1436 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1437 | ret = __smp_prepare_cpu(cpu); | |
1438 | ||
1439 | if (ret) | |
1440 | return -EIO; | |
1441 | #endif | |
1442 | ||
1da177e4 LT |
1443 | /* In case one didn't come up */ |
1444 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1445 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1446 | local_irq_enable(); |
1447 | return -EIO; | |
1448 | } | |
1449 | ||
1450 | local_irq_enable(); | |
e1367daf | 1451 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1452 | /* Unleash the CPU! */ |
1453 | cpu_set(cpu, smp_commenced_mask); | |
1454 | while (!cpu_isset(cpu, cpu_online_map)) | |
18698917 | 1455 | cpu_relax(); |
1da177e4 LT |
1456 | return 0; |
1457 | } | |
1458 | ||
1459 | void __init smp_cpus_done(unsigned int max_cpus) | |
1460 | { | |
1461 | #ifdef CONFIG_X86_IO_APIC | |
1462 | setup_ioapic_dest(); | |
1463 | #endif | |
1464 | zap_low_mappings(); | |
e1367daf | 1465 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1466 | /* |
1467 | * Disable executability of the SMP trampoline: | |
1468 | */ | |
1469 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1470 | #endif |
1da177e4 LT |
1471 | } |
1472 | ||
1473 | void __init smp_intr_init(void) | |
1474 | { | |
1475 | /* | |
1476 | * IRQ0 must be given a fixed assignment and initialized, | |
1477 | * because it's used before the IO-APIC is set up. | |
1478 | */ | |
1479 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1480 | ||
1481 | /* | |
1482 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1483 | * IPI, driven by wakeup. | |
1484 | */ | |
1485 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1486 | ||
1487 | /* IPI for invalidation */ | |
1488 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1489 | ||
1490 | /* IPI for generic function call */ | |
1491 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1492 | } |