[deliverable/linux.git] / arch / i386 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>
 
#include "op_counter.h"
#include "op_x86_model.h"
 
static struct op_x86_model_spec const * model;
static struct op_msrs cpu_msrs[NR_CPUS];
static unsigned long saved_lvtpc[NR_CPUS];
 
static int nmi_start(void);
static void nmi_stop(void);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	if (nmi_enabled == 1)
		nmi_stop();
	return 0;
}


static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_start();
	return 0;
}


static struct sysdev_class oprofile_sysclass = {
	set_kset_name("oprofile"),
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};


static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};


static int __init init_driverfs(void)
{
	int error;
	if (!(error = sysdev_class_register(&oprofile_sysclass)))
		error = sysdev_register(&device_oprofile);
	return error;
}


static void exit_driverfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_driverfs() do { } while (0)
#define exit_driverfs() do { } while (0)
#endif /* CONFIG_PM */


static int nmi_callback(struct pt_regs * regs, int cpu)
{
	return model->check_ctrs(regs, &cpu_msrs[cpu]);
}
 
 
static void nmi_cpu_save_registers(struct op_msrs * msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls; 
	struct op_msr * counters = msrs->counters;
	struct op_msr * controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		rdmsr(counters[i].addr,
			counters[i].saved.low,
			counters[i].saved.high);
	}
 
	for (i = 0; i < nr_ctrls; ++i) {
		rdmsr(controls[i].addr,
			controls[i].saved.low,
			controls[i].saved.high);
	}
}


static void nmi_save_registers(void * dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs * msrs = &cpu_msrs[cpu];
	model->fill_in_addresses(msrs);
	nmi_cpu_save_registers(msrs);
}


static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(cpu_msrs[i].counters);
		cpu_msrs[i].counters = NULL;
		kfree(cpu_msrs[i].controls);
		cpu_msrs[i].controls = NULL;
	}
}


static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_online_cpu(i) {
		cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
		if (!cpu_msrs[i].counters) {
			success = 0;
			break;
		}
		cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
		if (!cpu_msrs[i].controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}


static void nmi_cpu_setup(void * dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs * msrs = &cpu_msrs[cpu];
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}


static int nmi_setup(void)
{
	if (!allocate_msrs())
		return -ENOMEM;

	/* We walk a thin line between law and rape here.
	 * We need to be careful to install our NMI handler
	 * without actually triggering any NMIs as this will
	 * break the core code horrifically.
	 */
	if (reserve_lapic_nmi() < 0) {
		free_msrs();
		return -EBUSY;
	}
	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */
	on_each_cpu(nmi_save_registers, NULL, 0, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
	set_nmi_callback(nmi_callback);
	nmi_enabled = 1;
	return 0;
}


static void nmi_restore_registers(struct op_msrs * msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls; 
	struct op_msr * counters = msrs->counters;
	struct op_msr * controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		wrmsr(controls[i].addr,
			controls[i].saved.low,
			controls[i].saved.high);
	}
 
	for (i = 0; i < nr_ctrs; ++i) {
		wrmsr(counters[i].addr,
			counters[i].saved.low,
			counters[i].saved.high);
	}
}
 

static void nmi_cpu_shutdown(void * dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs * msrs = &cpu_msrs[cpu];
 
	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

 
static void nmi_shutdown(void)
{
	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
	unset_nmi_callback();
	release_lapic_nmi();
	free_msrs();
}

 
static void nmi_cpu_start(void * dummy)
{
	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
	model->start(msrs);
}
 

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 0, 1);
	return 0;
}
 
 
static void nmi_cpu_stop(void * dummy)
{
	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
	model->stop(msrs);
}
 
 
static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
}


struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block * sb, struct dentry * root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry * dir;
		char buf[2];
 
		snprintf(buf, 2, "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); 
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); 
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); 
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); 
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); 
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); 
	}

	return 0;
}
 
 
static int __init p4_init(char ** cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 4)
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
		case 1:
			*cpu_type = "i386/p4";
			model = &op_p4_spec;
			return 1;

		case 2:
			*cpu_type = "i386/p4-ht";
			model = &op_p4_ht2_spec;
			return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}


static int __init ppro_init(char ** cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 0xd)
		return 0;

	if (cpu_model == 9) {
		*cpu_type = "i386/p6_mobile";
	} else if (cpu_model > 5) {
		*cpu_type = "i386/piii";
	} else if (cpu_model > 2) {
		*cpu_type = "i386/pii";
	} else {
		*cpu_type = "i386/ppro";
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get driverfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;

	if (!cpu_has_apic)
		return -ENODEV;
 
	switch (vendor) {
		case X86_VENDOR_AMD:
			/* Needs to be at least an Athlon (or hammer in 32bit mode) */

			switch (family) {
			default:
				return -ENODEV;
			case 6:
				model = &op_athlon_spec;
				cpu_type = "i386/athlon";
				break;
			case 0xf:
				model = &op_athlon_spec;
				/* Actually it could be i386/hammer too, but give
				   user space an consistent name. */
				cpu_type = "x86-64/hammer";
				break;
			}
			break;
 
		case X86_VENDOR_INTEL:
			switch (family) {
				/* Pentium IV */
				case 0xf:
					if (!p4_init(&cpu_type))
						return -ENODEV;
					break;

				/* A P6-class processor */
				case 6:
					if (!ppro_init(&cpu_type))
						return -ENODEV;
					break;

				default:
					return -ENODEV;
			}
			break;

		default:
			return -ENODEV;
	}

	init_driverfs();
	using_nmi = 1;
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}


void op_nmi_exit(void)
{
	if (using_nmi)
		exit_driverfs();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
	4	* @remark Copyright 2002 OProfile authors
	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/notifier.h>
	12	#include <linux/smp.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/sysdev.h>
	15	#include <linux/slab.h>
	16	#include <asm/nmi.h>
	17	#include <asm/msr.h>
	18	#include <asm/apic.h>
	19
	20	#include "op_counter.h"
	21	#include "op_x86_model.h"
	22
	23	static struct op_x86_model_spec const * model;
	24	static struct op_msrs cpu_msrs[NR_CPUS];
	25	static unsigned long saved_lvtpc[NR_CPUS];
	26
	27	static int nmi_start(void);
	28	static void nmi_stop(void);
	29
	30	/* 0 == registered but off, 1 == registered and on */
	31	static int nmi_enabled = 0;
	32
	33	#ifdef CONFIG_PM
	34
438510f6	35	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	36	{
	37	if (nmi_enabled == 1)
	38	nmi_stop();
	39	return 0;
	40	}
	41
	42
	43	static int nmi_resume(struct sys_device *dev)
	44	{
	45	if (nmi_enabled == 1)
	46	nmi_start();
	47	return 0;
	48	}
	49
	50
	51	static struct sysdev_class oprofile_sysclass = {
	52	set_kset_name("oprofile"),
	53	.resume = nmi_resume,
	54	.suspend = nmi_suspend,
	55	};
	56
	57
	58	static struct sys_device device_oprofile = {
	59	.id = 0,
	60	.cls = &oprofile_sysclass,
	61	};
	62
	63
	64	static int __init init_driverfs(void)
	65	{
	66	int error;
	67	if (!(error = sysdev_class_register(&oprofile_sysclass)))
	68	error = sysdev_register(&device_oprofile);
	69	return error;
	70	}
	71
	72
	73	static void exit_driverfs(void)
	74	{
	75	sysdev_unregister(&device_oprofile);
	76	sysdev_class_unregister(&oprofile_sysclass);
	77	}
	78
	79	#else
	80	#define init_driverfs() do { } while (0)
	81	#define exit_driverfs() do { } while (0)
	82	#endif /* CONFIG_PM */
	83
	84
	85	static int nmi_callback(struct pt_regs * regs, int cpu)
	86	{
	87	return model->check_ctrs(regs, &cpu_msrs[cpu]);
	88	}
	89
	90
	91	static void nmi_cpu_save_registers(struct op_msrs * msrs)
	92	{
	93	unsigned int const nr_ctrs = model->num_counters;
	94	unsigned int const nr_ctrls = model->num_controls;
	95	struct op_msr * counters = msrs->counters;
	96	struct op_msr * controls = msrs->controls;
	97	unsigned int i;
	98
	99	for (i = 0; i < nr_ctrs; ++i) {
100	rdmsr(counters[i].addr,
101	counters[i].saved.low,
102	counters[i].saved.high);
103	}
104
105	for (i = 0; i < nr_ctrls; ++i) {
106	rdmsr(controls[i].addr,
107	controls[i].saved.low,
108	controls[i].saved.high);
109	}
110	}
111
112
113	static void nmi_save_registers(void * dummy)
114	{
115	int cpu = smp_processor_id();
116	struct op_msrs * msrs = &cpu_msrs[cpu];
117	model->fill_in_addresses(msrs);
118	nmi_cpu_save_registers(msrs);
119	}
120
121
122	static void free_msrs(void)
123	{
124	int i;
c8912599	125	for_each_possible_cpu(i) {
1da177e4 LT	126	kfree(cpu_msrs[i].counters);
	127	cpu_msrs[i].counters = NULL;
	128	kfree(cpu_msrs[i].controls);
	129	cpu_msrs[i].controls = NULL;
	130	}
	131	}
	132
	133
	134	static int allocate_msrs(void)
	135	{
	136	int success = 1;
	137	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	138	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	139
	140	int i;
394e3902	141	for_each_online_cpu(i) {
1da177e4 LT	142	cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
	143	if (!cpu_msrs[i].counters) {
	144	success = 0;
	145	break;
	146	}
	147	cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
	148	if (!cpu_msrs[i].controls) {
	149	success = 0;
	150	break;
	151	}
	152	}
	153
	154	if (!success)
	155	free_msrs();
	156
	157	return success;
	158	}
	159
	160
	161	static void nmi_cpu_setup(void * dummy)
	162	{
	163	int cpu = smp_processor_id();
	164	struct op_msrs * msrs = &cpu_msrs[cpu];
	165	spin_lock(&oprofilefs_lock);
	166	model->setup_ctrs(msrs);
	167	spin_unlock(&oprofilefs_lock);
	168	saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
	169	apic_write(APIC_LVTPC, APIC_DM_NMI);
	170	}
	171
	172
	173	static int nmi_setup(void)
	174	{
	175	if (!allocate_msrs())
	176	return -ENOMEM;
	177
	178	/* We walk a thin line between law and rape here.
	179	* We need to be careful to install our NMI handler
	180	* without actually triggering any NMIs as this will
	181	* break the core code horrifically.
	182	*/
	183	if (reserve_lapic_nmi() < 0) {
	184	free_msrs();
	185	return -EBUSY;
	186	}
	187	/* We need to serialize save and setup for HT because the subset
	188	* of msrs are distinct for save and setup operations
	189	*/
	190	on_each_cpu(nmi_save_registers, NULL, 0, 1);
	191	on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
	192	set_nmi_callback(nmi_callback);
	193	nmi_enabled = 1;
	194	return 0;
	195	}
	196
	197
	198	static void nmi_restore_registers(struct op_msrs * msrs)
	199	{
	200	unsigned int const nr_ctrs = model->num_counters;
	201	unsigned int const nr_ctrls = model->num_controls;
	202	struct op_msr * counters = msrs->counters;
	203	struct op_msr * controls = msrs->controls;
	204	unsigned int i;
	205
206	for (i = 0; i < nr_ctrls; ++i) {
207	wrmsr(controls[i].addr,
208	controls[i].saved.low,
209	controls[i].saved.high);
210	}
211
212	for (i = 0; i < nr_ctrs; ++i) {
213	wrmsr(counters[i].addr,
214	counters[i].saved.low,
215	counters[i].saved.high);
216	}
217	}
218
219
220	static void nmi_cpu_shutdown(void * dummy)
221	{
222	unsigned int v;
223	int cpu = smp_processor_id();
224	struct op_msrs * msrs = &cpu_msrs[cpu];
225
226	/* restoring APIC_LVTPC can trigger an apic error because the delivery
227	* mode and vector nr combination can be illegal. That's by design: on
228	* power on apic lvt contain a zero vector nr which are legal only for
229	* NMI delivery mode. So inhibit apic err before restoring lvtpc
230	*/
231	v = apic_read(APIC_LVTERR);
232	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
233	apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
234	apic_write(APIC_LVTERR, v);
235	nmi_restore_registers(msrs);
236	}
237
238
239	static void nmi_shutdown(void)
240	{
241	nmi_enabled = 0;
242	on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
243	unset_nmi_callback();
244	release_lapic_nmi();
245	free_msrs();
246	}
247
248
249	static void nmi_cpu_start(void * dummy)
250	{
251	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
252	model->start(msrs);
253	}
254
255
256	static int nmi_start(void)
257	{
258	on_each_cpu(nmi_cpu_start, NULL, 0, 1);
259	return 0;
260	}
261
262
263	static void nmi_cpu_stop(void * dummy)
264	{
265	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
266	model->stop(msrs);
267	}
268
269
270	static void nmi_stop(void)
271	{
272	on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
273	}
274
275
276	struct op_counter_config counter_config[OP_MAX_COUNTER];
277
278	static int nmi_create_files(struct super_block * sb, struct dentry * root)
279	{
280	unsigned int i;
281
282	for (i = 0; i < model->num_counters; ++i) {
283	struct dentry * dir;
284	char buf[2];
285
286	snprintf(buf, 2, "%d", i);
287	dir = oprofilefs_mkdir(sb, root, buf);
288	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
289	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
290	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
291	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
292	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
293	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
294	}
295
296	return 0;
297	}
298
299
300	static int __init p4_init(char ** cpu_type)
301	{
302	__u8 cpu_model = boot_cpu_data.x86_model;
303
304	if (cpu_model > 4)
305	return 0;
306
307	#ifndef CONFIG_SMP
308	*cpu_type = "i386/p4";
309	model = &op_p4_spec;
310	return 1;
311	#else
312	switch (smp_num_siblings) {
313	case 1:
314	*cpu_type = "i386/p4";
315	model = &op_p4_spec;
316	return 1;
317
318	case 2:
319	*cpu_type = "i386/p4-ht";
320	model = &op_p4_ht2_spec;
321	return 1;
322	}
323	#endif
324
325	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
326	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
327	return 0;
328	}
329
330
331	static int __init ppro_init(char ** cpu_type)
332	{
333	__u8 cpu_model = boot_cpu_data.x86_model;
334
335	if (cpu_model > 0xd)
336	return 0;
337
338	if (cpu_model == 9) {
339	*cpu_type = "i386/p6_mobile";
340	} else if (cpu_model > 5) {
341	*cpu_type = "i386/piii";
342	} else if (cpu_model > 2) {
343	*cpu_type = "i386/pii";
344	} else {
345	*cpu_type = "i386/ppro";
346	}
347
348	model = &op_ppro_spec;
349	return 1;
350	}
351
352	/* in order to get driverfs right */
353	static int using_nmi;
354
96d0821c	355	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	356	{
	357	__u8 vendor = boot_cpu_data.x86_vendor;
	358	__u8 family = boot_cpu_data.x86;
	359	char *cpu_type;
	360
	361	if (!cpu_has_apic)
	362	return -ENODEV;
	363
	364	switch (vendor) {
	365	case X86_VENDOR_AMD:
	366	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
	367
	368	switch (family) {
	369	default:
	370	return -ENODEV;
	371	case 6:
	372	model = &op_athlon_spec;
	373	cpu_type = "i386/athlon";
	374	break;
	375	case 0xf:
	376	model = &op_athlon_spec;
	377	/* Actually it could be i386/hammer too, but give
	378	user space an consistent name. */
	379	cpu_type = "x86-64/hammer";
	380	break;
	381	}
	382	break;
	383
	384	case X86_VENDOR_INTEL:
	385	switch (family) {
	386	/* Pentium IV */
	387	case 0xf:
	388	if (!p4_init(&cpu_type))
	389	return -ENODEV;
	390	break;
	391
	392	/* A P6-class processor */
	393	case 6:
	394	if (!ppro_init(&cpu_type))
	395	return -ENODEV;
	396	break;
	397
	398	default:
	399	return -ENODEV;
	400	}
	401	break;
	402
	403	default:
	404	return -ENODEV;
	405	}
	406
	407	init_driverfs();
	408	using_nmi = 1;
	409	ops->create_files = nmi_create_files;
	410	ops->setup = nmi_setup;
	411	ops->shutdown = nmi_shutdown;
	412	ops->start = nmi_start;
	413	ops->stop = nmi_stop;
	414	ops->cpu_type = cpu_type;
	415	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	416	return 0;
	417	}
	418
	419
96d0821c	420	void op_nmi_exit(void)
1da177e4 LT	421	{
	422	if (using_nmi)
	423	exit_driverfs();
	424	}