[deliverable/linux.git] / arch / i386 / pci / direct.c

/*
 * direct.c - Low-level direct PCI config space access
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include "pci.h"

/*
 * Functions for accessing PCI configuration space with type 1 accesses
 */

#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
	(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))

int pci_conf1_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;

	if ((bus > 255) || (devfn > 255) || (reg > 255)) {
		*value = -1;
		return -EINVAL;
	}

	spin_lock_irqsave(&pci_config_lock, flags);

	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);

	switch (len) {
	case 1:
		*value = inb(0xCFC + (reg & 3));
		break;
	case 2:
		*value = inw(0xCFC + (reg & 2));
		break;
	case 4:
		*value = inl(0xCFC);
		break;
	}

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

int pci_conf1_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;

	if ((bus > 255) || (devfn > 255) || (reg > 255)) 
		return -EINVAL;

	spin_lock_irqsave(&pci_config_lock, flags);

	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);

	switch (len) {
	case 1:
		outb((u8)value, 0xCFC + (reg & 3));
		break;
	case 2:
		outw((u16)value, 0xCFC + (reg & 2));
		break;
	case 4:
		outl((u32)value, 0xCFC);
		break;
	}

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

#undef PCI_CONF1_ADDRESS

struct pci_raw_ops pci_direct_conf1 = {
	.read =		pci_conf1_read,
	.write =	pci_conf1_write,
};


/*
 * Functions for accessing PCI configuration space with type 2 accesses
 */

#define PCI_CONF2_ADDRESS(dev, reg)	(u16)(0xC000 | (dev << 8) | reg)

static int pci_conf2_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	int dev, fn;

	if ((bus > 255) || (devfn > 255) || (reg > 255)) {
		*value = -1;
		return -EINVAL;
	}

	dev = PCI_SLOT(devfn);
	fn = PCI_FUNC(devfn);

	if (dev & 0x10) 
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pci_config_lock, flags);

	outb((u8)(0xF0 | (fn << 1)), 0xCF8);
	outb((u8)bus, 0xCFA);

	switch (len) {
	case 1:
		*value = inb(PCI_CONF2_ADDRESS(dev, reg));
		break;
	case 2:
		*value = inw(PCI_CONF2_ADDRESS(dev, reg));
		break;
	case 4:
		*value = inl(PCI_CONF2_ADDRESS(dev, reg));
		break;
	}

	outb(0, 0xCF8);

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static int pci_conf2_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	int dev, fn;

	if ((bus > 255) || (devfn > 255) || (reg > 255)) 
		return -EINVAL;

	dev = PCI_SLOT(devfn);
	fn = PCI_FUNC(devfn);

	if (dev & 0x10) 
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pci_config_lock, flags);

	outb((u8)(0xF0 | (fn << 1)), 0xCF8);
	outb((u8)bus, 0xCFA);

	switch (len) {
	case 1:
		outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
		break;
	case 2:
		outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
		break;
	case 4:
		outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
		break;
	}

	outb(0, 0xCF8);    

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

#undef PCI_CONF2_ADDRESS

static struct pci_raw_ops pci_direct_conf2 = {
	.read =		pci_conf2_read,
	.write =	pci_conf2_write,
};


/*
 * Before we decide to use direct hardware access mechanisms, we try to do some
 * trivial checks to ensure it at least _seems_ to be working -- we just test
 * whether bus 00 contains a host bridge (this is similar to checking
 * techniques used in XFree86, but ours should be more reliable since we
 * attempt to make use of direct access hints provided by the PCI BIOS).
 *
 * This should be close to trivial, but it isn't, because there are buggy
 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
 */
static int __init pci_sanity_check(struct pci_raw_ops *o)
{
	u32 x = 0;
	int devfn;

	if (pci_probe & PCI_NO_CHECKS)
		return 1;
	/* Assume Type 1 works for newer systems.
	   This handles machines that don't have anything on PCI Bus 0. */
	if (dmi_get_year(DMI_BIOS_DATE) >= 2001)
		return 1;

	for (devfn = 0; devfn < 0x100; devfn++) {
		if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
			continue;
		if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
			return 1;

		if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
			continue;
		if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
			return 1;
	}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* direct.c - Low-level direct PCI config space access
	3	*/
	4
	5	#include <linux/pci.h>
	6	#include <linux/init.h>
ec0f08ee	7	#include <linux/dmi.h>
1da177e4 LT	8	#include "pci.h"
	9
	10	/*
	11	* Functions for accessing PCI configuration space with type 1 accesses
	12	*/
	13
	14	#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
	15	(0x80000000 \| (bus << 16) \| (devfn << 8) \| (reg & ~3))
	16
928cf8c6	17	int pci_conf1_read(unsigned int seg, unsigned int bus,
1da177e4 LT	18	unsigned int devfn, int reg, int len, u32 *value)
	19	{
	20	unsigned long flags;
	21
ecc16ba9	22	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 255)) {
49c93e84	23	*value = -1;
1da177e4	24	return -EINVAL;
49c93e84	25	}
1da177e4 LT	26
	27	spin_lock_irqsave(&pci_config_lock, flags);
	28
	29	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
	30
	31	switch (len) {
	32	case 1:
	33	*value = inb(0xCFC + (reg & 3));
	34	break;
	35	case 2:
	36	*value = inw(0xCFC + (reg & 2));
	37	break;
	38	case 4:
	39	*value = inl(0xCFC);
	40	break;
	41	}
	42
	43	spin_unlock_irqrestore(&pci_config_lock, flags);
	44
	45	return 0;
	46	}
	47
928cf8c6	48	int pci_conf1_write(unsigned int seg, unsigned int bus,
1da177e4 LT	49	unsigned int devfn, int reg, int len, u32 value)
	50	{
	51	unsigned long flags;
	52
	53	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 255))
	54	return -EINVAL;
	55
	56	spin_lock_irqsave(&pci_config_lock, flags);
	57
	58	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
	59
	60	switch (len) {
	61	case 1:
	62	outb((u8)value, 0xCFC + (reg & 3));
	63	break;
	64	case 2:
	65	outw((u16)value, 0xCFC + (reg & 2));
	66	break;
	67	case 4:
	68	outl((u32)value, 0xCFC);
	69	break;
	70	}
	71
	72	spin_unlock_irqrestore(&pci_config_lock, flags);
	73
	74	return 0;
	75	}
	76
	77	#undef PCI_CONF1_ADDRESS
	78
	79	struct pci_raw_ops pci_direct_conf1 = {
	80	.read = pci_conf1_read,
	81	.write = pci_conf1_write,
	82	};
	83
	84
	85	/*
	86	* Functions for accessing PCI configuration space with type 2 accesses
	87	*/
	88
	89	#define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 \| (dev << 8) \| reg)
	90
	91	static int pci_conf2_read(unsigned int seg, unsigned int bus,
	92	unsigned int devfn, int reg, int len, u32 *value)
	93	{
	94	unsigned long flags;
	95	int dev, fn;
	96
ecc16ba9 AK	97	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 255)) {
ecc16ba9 AK	98	*value = -1;
1da177e4	99	return -EINVAL;
ecc16ba9	100	}
1da177e4 LT	101
	102	dev = PCI_SLOT(devfn);
	103	fn = PCI_FUNC(devfn);
	104
	105	if (dev & 0x10)
	106	return PCIBIOS_DEVICE_NOT_FOUND;
	107
	108	spin_lock_irqsave(&pci_config_lock, flags);
	109
	110	outb((u8)(0xF0 \| (fn << 1)), 0xCF8);
	111	outb((u8)bus, 0xCFA);
	112
	113	switch (len) {
	114	case 1:
	115	*value = inb(PCI_CONF2_ADDRESS(dev, reg));
	116	break;
	117	case 2:
	118	*value = inw(PCI_CONF2_ADDRESS(dev, reg));
	119	break;
	120	case 4:
	121	*value = inl(PCI_CONF2_ADDRESS(dev, reg));
	122	break;
	123	}
	124
	125	outb(0, 0xCF8);
	126
	127	spin_unlock_irqrestore(&pci_config_lock, flags);
	128
	129	return 0;
	130	}
	131
	132	static int pci_conf2_write(unsigned int seg, unsigned int bus,
	133	unsigned int devfn, int reg, int len, u32 value)
	134	{
	135	unsigned long flags;
	136	int dev, fn;
	137
	138	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 255))
	139	return -EINVAL;
	140
	141	dev = PCI_SLOT(devfn);
	142	fn = PCI_FUNC(devfn);
	143
	144	if (dev & 0x10)
	145	return PCIBIOS_DEVICE_NOT_FOUND;
	146
	147	spin_lock_irqsave(&pci_config_lock, flags);
	148
	149	outb((u8)(0xF0 \| (fn << 1)), 0xCF8);
	150	outb((u8)bus, 0xCFA);
	151
	152	switch (len) {
	153	case 1:
	154	outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
	155	break;
	156	case 2:
	157	outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
	158	break;
	159	case 4:
	160	outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
	161	break;
	162	}
	163
	164	outb(0, 0xCF8);
165
166	spin_unlock_irqrestore(&pci_config_lock, flags);
167
168	return 0;
169	}
170
171	#undef PCI_CONF2_ADDRESS
172
173	static struct pci_raw_ops pci_direct_conf2 = {
174	.read = pci_conf2_read,
175	.write = pci_conf2_write,
176	};
177
178
179	/*
180	* Before we decide to use direct hardware access mechanisms, we try to do some
181	* trivial checks to ensure it at least _seems_ to be working -- we just test
182	* whether bus 00 contains a host bridge (this is similar to checking
183	* techniques used in XFree86, but ours should be more reliable since we
184	* attempt to make use of direct access hints provided by the PCI BIOS).
185	*
186	* This should be close to trivial, but it isn't, because there are buggy
187	* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
188	*/
189	static int __init pci_sanity_check(struct pci_raw_ops *o)
190	{
191	u32 x = 0;
192	int devfn;
193
194	if (pci_probe & PCI_NO_CHECKS)
195	return 1;
ec0f08ee AK	196	/* Assume Type 1 works for newer systems.
	197	This handles machines that don't have anything on PCI Bus 0. */
	198	if (dmi_get_year(DMI_BIOS_DATE) >= 2001)
	199	return 1;
1da177e4 LT	200
	201	for (devfn = 0; devfn < 0x100; devfn++) {
	202	if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
	203	continue;
	204	if (x == PCI_CLASS_BRIDGE_HOST \|\| x == PCI_CLASS_DISPLAY_VGA)
	205	return 1;
	206
	207	if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
	208	continue;
	209	if (x == PCI_VENDOR_ID_INTEL \|\| x == PCI_VENDOR_ID_COMPAQ)
	210	return 1;
	211	}
	212