Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * direct.c - Low-level direct PCI config space access | |
3 | */ | |
4 | ||
5 | #include <linux/pci.h> | |
6 | #include <linux/init.h> | |
7 | #include "pci.h" | |
8 | ||
9 | /* | |
10 | * Functions for accessing PCI configuration space with type 1 accesses | |
11 | */ | |
12 | ||
13 | #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ | |
14 | (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) | |
15 | ||
928cf8c6 | 16 | int pci_conf1_read(unsigned int seg, unsigned int bus, |
1da177e4 LT |
17 | unsigned int devfn, int reg, int len, u32 *value) |
18 | { | |
19 | unsigned long flags; | |
20 | ||
21 | if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) | |
22 | return -EINVAL; | |
23 | ||
24 | spin_lock_irqsave(&pci_config_lock, flags); | |
25 | ||
26 | outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); | |
27 | ||
28 | switch (len) { | |
29 | case 1: | |
30 | *value = inb(0xCFC + (reg & 3)); | |
31 | break; | |
32 | case 2: | |
33 | *value = inw(0xCFC + (reg & 2)); | |
34 | break; | |
35 | case 4: | |
36 | *value = inl(0xCFC); | |
37 | break; | |
38 | } | |
39 | ||
40 | spin_unlock_irqrestore(&pci_config_lock, flags); | |
41 | ||
42 | return 0; | |
43 | } | |
44 | ||
928cf8c6 | 45 | int pci_conf1_write(unsigned int seg, unsigned int bus, |
1da177e4 LT |
46 | unsigned int devfn, int reg, int len, u32 value) |
47 | { | |
48 | unsigned long flags; | |
49 | ||
50 | if ((bus > 255) || (devfn > 255) || (reg > 255)) | |
51 | return -EINVAL; | |
52 | ||
53 | spin_lock_irqsave(&pci_config_lock, flags); | |
54 | ||
55 | outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); | |
56 | ||
57 | switch (len) { | |
58 | case 1: | |
59 | outb((u8)value, 0xCFC + (reg & 3)); | |
60 | break; | |
61 | case 2: | |
62 | outw((u16)value, 0xCFC + (reg & 2)); | |
63 | break; | |
64 | case 4: | |
65 | outl((u32)value, 0xCFC); | |
66 | break; | |
67 | } | |
68 | ||
69 | spin_unlock_irqrestore(&pci_config_lock, flags); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
74 | #undef PCI_CONF1_ADDRESS | |
75 | ||
76 | struct pci_raw_ops pci_direct_conf1 = { | |
77 | .read = pci_conf1_read, | |
78 | .write = pci_conf1_write, | |
79 | }; | |
80 | ||
81 | ||
82 | /* | |
83 | * Functions for accessing PCI configuration space with type 2 accesses | |
84 | */ | |
85 | ||
86 | #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) | |
87 | ||
88 | static int pci_conf2_read(unsigned int seg, unsigned int bus, | |
89 | unsigned int devfn, int reg, int len, u32 *value) | |
90 | { | |
91 | unsigned long flags; | |
92 | int dev, fn; | |
93 | ||
94 | if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) | |
95 | return -EINVAL; | |
96 | ||
97 | dev = PCI_SLOT(devfn); | |
98 | fn = PCI_FUNC(devfn); | |
99 | ||
100 | if (dev & 0x10) | |
101 | return PCIBIOS_DEVICE_NOT_FOUND; | |
102 | ||
103 | spin_lock_irqsave(&pci_config_lock, flags); | |
104 | ||
105 | outb((u8)(0xF0 | (fn << 1)), 0xCF8); | |
106 | outb((u8)bus, 0xCFA); | |
107 | ||
108 | switch (len) { | |
109 | case 1: | |
110 | *value = inb(PCI_CONF2_ADDRESS(dev, reg)); | |
111 | break; | |
112 | case 2: | |
113 | *value = inw(PCI_CONF2_ADDRESS(dev, reg)); | |
114 | break; | |
115 | case 4: | |
116 | *value = inl(PCI_CONF2_ADDRESS(dev, reg)); | |
117 | break; | |
118 | } | |
119 | ||
120 | outb(0, 0xCF8); | |
121 | ||
122 | spin_unlock_irqrestore(&pci_config_lock, flags); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static int pci_conf2_write(unsigned int seg, unsigned int bus, | |
128 | unsigned int devfn, int reg, int len, u32 value) | |
129 | { | |
130 | unsigned long flags; | |
131 | int dev, fn; | |
132 | ||
133 | if ((bus > 255) || (devfn > 255) || (reg > 255)) | |
134 | return -EINVAL; | |
135 | ||
136 | dev = PCI_SLOT(devfn); | |
137 | fn = PCI_FUNC(devfn); | |
138 | ||
139 | if (dev & 0x10) | |
140 | return PCIBIOS_DEVICE_NOT_FOUND; | |
141 | ||
142 | spin_lock_irqsave(&pci_config_lock, flags); | |
143 | ||
144 | outb((u8)(0xF0 | (fn << 1)), 0xCF8); | |
145 | outb((u8)bus, 0xCFA); | |
146 | ||
147 | switch (len) { | |
148 | case 1: | |
149 | outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); | |
150 | break; | |
151 | case 2: | |
152 | outw((u16)value, PCI_CONF2_ADDRESS(dev, reg)); | |
153 | break; | |
154 | case 4: | |
155 | outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); | |
156 | break; | |
157 | } | |
158 | ||
159 | outb(0, 0xCF8); | |
160 | ||
161 | spin_unlock_irqrestore(&pci_config_lock, flags); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | #undef PCI_CONF2_ADDRESS | |
167 | ||
168 | static struct pci_raw_ops pci_direct_conf2 = { | |
169 | .read = pci_conf2_read, | |
170 | .write = pci_conf2_write, | |
171 | }; | |
172 | ||
173 | ||
174 | /* | |
175 | * Before we decide to use direct hardware access mechanisms, we try to do some | |
176 | * trivial checks to ensure it at least _seems_ to be working -- we just test | |
177 | * whether bus 00 contains a host bridge (this is similar to checking | |
178 | * techniques used in XFree86, but ours should be more reliable since we | |
179 | * attempt to make use of direct access hints provided by the PCI BIOS). | |
180 | * | |
181 | * This should be close to trivial, but it isn't, because there are buggy | |
182 | * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. | |
183 | */ | |
184 | static int __init pci_sanity_check(struct pci_raw_ops *o) | |
185 | { | |
186 | u32 x = 0; | |
187 | int devfn; | |
188 | ||
189 | if (pci_probe & PCI_NO_CHECKS) | |
190 | return 1; | |
191 | ||
192 | for (devfn = 0; devfn < 0x100; devfn++) { | |
193 | if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x)) | |
194 | continue; | |
195 | if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA) | |
196 | return 1; | |
197 | ||
198 | if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x)) | |
199 | continue; | |
200 | if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ) | |
201 | return 1; | |
202 | } | |
203 |