[deliverable/linux.git] / arch / i386 / pci / fixup.c

/*
 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
 */

#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/pci.h>
#include <linux/init.h>
#include "pci.h"


static void __devinit pci_fixup_i450nx(struct pci_dev *d)
{
	/*
	 * i450NX -- Find and scan all secondary buses on all PXB's.
	 */
	int pxb, reg;
	u8 busno, suba, subb;

	printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
	reg = 0xd0;
	for(pxb=0; pxb<2; pxb++) {
		pci_read_config_byte(d, reg++, &busno);
		pci_read_config_byte(d, reg++, &suba);
		pci_read_config_byte(d, reg++, &subb);
		DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
		if (busno)
			pci_scan_bus(busno, &pci_root_ops, NULL);	/* Bus A */
		if (suba < subb)
			pci_scan_bus(suba+1, &pci_root_ops, NULL);	/* Bus B */
	}
	pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);

static void __devinit pci_fixup_i450gx(struct pci_dev *d)
{
	/*
	 * i450GX and i450KX -- Find and scan all secondary buses.
	 * (called separately for each PCI bridge found)
	 */
	u8 busno;
	pci_read_config_byte(d, 0x4a, &busno);
	printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
	pci_scan_bus(busno, &pci_root_ops, NULL);
	pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);

static void __devinit  pci_fixup_umc_ide(struct pci_dev *d)
{
	/*
	 * UM8886BF IDE controller sets region type bits incorrectly,
	 * therefore they look like memory despite of them being I/O.
	 */
	int i;

	printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
	for(i=0; i<4; i++)
		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);

static void __devinit  pci_fixup_ncr53c810(struct pci_dev *d)
{
	/*
	 * NCR 53C810 returns class code 0 (at least on some systems).
	 * Fix class to be PCI_CLASS_STORAGE_SCSI
	 */
	if (!d->class) {
		printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
		d->class = PCI_CLASS_STORAGE_SCSI << 8;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);

static void __devinit  pci_fixup_latency(struct pci_dev *d)
{
	/*
	 *  SiS 5597 and 5598 chipsets require latency timer set to
	 *  at most 32 to avoid lockups.
	 */
	DBG("PCI: Setting max latency to 32\n");
	pcibios_max_latency = 32;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);

static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
{
	/*
	 * PIIX4 ACPI device: hardwired IRQ9
	 */
	d->irq = 9;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);

/*
 * Addresses issues with problems in the memory write queue timer in
 * certain VIA Northbridges.  This bugfix is per VIA's specifications,
 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
 * to trigger a bug in its integrated ProSavage video card, which
 * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
 * until VIA can provide us with definitive information on why screen
 * corruption occurs, and what exactly those bits do.
 *
 * VIA 8363,8622,8361 Northbridges:
 *  - bits  5, 6, 7 at offset 0x55 need to be turned off
 * VIA 8367 (KT266x) Northbridges:
 *  - bits  5, 6, 7 at offset 0x95 need to be turned off
 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
 *  - bits     6, 7 at offset 0x55 need to be turned off
 */

#define VIA_8363_KL133_REVISION_ID 0x81
#define VIA_8363_KM133_REVISION_ID 0x84

static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
{
	u8 v;
	u8 revision;
	int where = 0x55;
	int mask = 0x1f; /* clear bits 5, 6, 7 by default */

	pci_read_config_byte(d, PCI_REVISION_ID, &revision);

	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
		/* fix pci bus latency issues resulted by NB bios error
		   it appears on bug free^Wreduced kt266x's bios forces
		   NB latency to zero */
		pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);

		where = 0x95; /* the memory write queue timer register is 
				different for the KT266x's: 0x95 not 0x55 */
	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
			(revision == VIA_8363_KL133_REVISION_ID || 
			revision == VIA_8363_KM133_REVISION_ID)) {
			mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
					causes screen corruption on the KL133/KM133 */
	}

	pci_read_config_byte(d, where, &v);
	if (v & ~mask) {
		printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
			d->device, revision, where, v, mask, v & mask);
		v &= mask;
		pci_write_config_byte(d, where, v);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);

/*
 * For some reasons Intel decided that certain parts of their
 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
 * to Intel terminology. These devices do forward all addresses from
 * system to PCI bus no matter what are their window settings, so they are
 * "transparent" (or subtractive decoding) from programmers point of view.
 */
static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
{
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
	    (dev->device & 0xff00) == 0x2400)
		dev->transparent = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);

/*
 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
 *
 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
 *
 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
 * sequence.  Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
 * This allows the state-machine and timer to return to a proper state within
 * 80 ns of the CONNECT and probe appearing together.  Since the CPU will not
 * issue another HALT within 80 ns of the initial HALT, the failure condition
 * is avoided.
 */
static void __init pci_fixup_nforce2(struct pci_dev *dev)
{
	u32 val;

	/*
	 * Chip  Old value   New value
	 * C17   0x1F0FFF01  0x1F01FF01
	 * C18D  0x9F0FFF01  0x9F01FF01
	 *
	 * Northbridge chip version may be determined by
	 * reading the PCI revision ID (0xC1 or greater is C18D).
	 */
	pci_read_config_dword(dev, 0x6c, &val);

	/*
	 * Apply fixup if needed, but don't touch disconnect state
	 */
	if ((val & 0x00FF0000) != 0x00010000) {
		printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);

/* Max PCI Express root ports */
#define MAX_PCIEROOT	6
static int quirk_aspm_offset[MAX_PCIEROOT << 3];

#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))

static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
}

/*
 * Replace the original pci bus ops for write with a new one that will filter
 * the request to insure ASPM cannot be enabled.
 */
static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
	u8 offset;

	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];

	if ((offset) && (where == offset))
		value = value & 0xfffffffc;
	
	return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
}

static struct pci_ops quirk_pcie_aspm_ops = {
	.read = quirk_pcie_aspm_read,
	.write = quirk_pcie_aspm_write,
};

/*
 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
 *
 * Save the register offset, where the ASPM control bits are located,
 * for each PCI Express device that is in the device list of
 * the root port in an array for fast indexing. Replace the bus ops
 * with the modified one.
 */
static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
{
	int cap_base, i;
	struct pci_bus  *pbus;
	struct pci_dev *dev;

	if ((pbus = pdev->subordinate) == NULL)
		return;

	/*
	 * Check if the DID of pdev matches one of the six root ports. This
	 * check is needed in the case this function is called directly by the
	 * hot-plug driver.
	 */
	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
	    (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
		return;

	if (list_empty(&pbus->devices)) {
		/*
		 * If no device is attached to the root port at power-up or
		 * after hot-remove, the pbus->devices is empty and this code
		 * will set the offsets to zero and the bus ops to parent's bus
		 * ops, which is unmodified.
	 	 */
		for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
			quirk_aspm_offset[i] = 0;

		pbus->ops = pbus->parent->ops;
	} else {
		/*
		 * If devices are attached to the root port at power-up or
		 * after hot-add, the code loops through the device list of
		 * each root port to save the register offsets and replace the
		 * bus ops.
		 */
		list_for_each_entry(dev, &pbus->devices, bus_list) {
			/* There are 0 to 8 devices attached to this bus */
			cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
			quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10;
		}
		pbus->ops = &quirk_pcie_aspm_ops;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA,	pcie_rootport_aspm_quirk );
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA1,	pcie_rootport_aspm_quirk );
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB,	pcie_rootport_aspm_quirk );
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB1,	pcie_rootport_aspm_quirk );
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC,	pcie_rootport_aspm_quirk );
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC1,	pcie_rootport_aspm_quirk );

/*
 * Fixup to mark boot BIOS video selected by BIOS before it changes
 *
 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
 *
 * The standard boot ROM sequence for an x86 machine uses the BIOS
 * to select an initial video card for boot display. This boot video
 * card will have it's BIOS copied to C0000 in system RAM.
 * IORESOURCE_ROM_SHADOW is used to associate the boot video
 * card with this copy. On laptops this copy has to be used since
 * the main ROM may be compressed or combined with another image.
 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
 * is marked here since the boot video device will be the only enabled
 * video device at this point.
 */

static void __devinit pci_fixup_video(struct pci_dev *pdev)
{
	struct pci_dev *bridge;
	struct pci_bus *bus;
	u16 config;

	if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
		return;

	/* Is VGA routed to us? */
	bus = pdev->bus;
	while (bus) {
		bridge = bus->self;

		/*
		 * From information provided by
		 * "David Miller" <davem@davemloft.net>
		 * The bridge control register is valid for PCI header
		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
		 * PCI header type NORMAL.
		 */
		if (bridge
		    &&((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
		       ||(bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
						&config);
			if (!(config & PCI_BRIDGE_CTL_VGA))
				return;
		}
		bus = bus->parent;
	}
	pci_read_config_word(pdev, PCI_COMMAND, &config);
	if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
		pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
		printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);

/*
 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
 *
 * We pretend to bring them out of full D3 state, and restore the proper
 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
 * properly.  In some cases, the device will generate an interrupt on
 * the wrong IRQ line, causing any devices sharing the line it's
 * *supposed* to use to be disabled by the kernel's IRQ debug code.
 */
static u16 toshiba_line_size;

static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = {
	{
		.ident = "Toshiba PS5 based laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
			DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
		},
	},
	{
		.ident = "Toshiba PSM4 based laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
			DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
		},
	},
	{
		.ident = "Toshiba A40 based laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
			DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
		},
	},
	{ }
};

static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
{
	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
		return; /* only applies to certain Toshibas (so far) */

	dev->current_state = PCI_D3cold;
	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
			 pci_pre_fixup_toshiba_ohci1394);

static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
{
	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
		return; /* only applies to certain Toshibas (so far) */

	/* Restore config space on Toshiba laptops */
	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
			       pci_resource_start(dev, 0));
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
			       pci_resource_start(dev, 1));
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
			 pci_post_fixup_toshiba_ohci1394);


/*
 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
 * configuration space.
 */
static void __devinit pci_early_fixup_cyrix_5530(struct pci_dev *dev)
{
	u8 r;
	/* clear 'F4 Video Configuration Trap' bit */
	pci_read_config_byte(dev, 0x42, &r);
	r &= 0xfd;
	pci_write_config_byte(dev, 0x42, r);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
			pci_early_fixup_cyrix_5530);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Exceptions for specific devices. Usually work-arounds for fatal design flaws.
	3	*/
	4
f8977d0a JB	5	#include <linux/delay.h>
f8977d0a JB	6	#include <linux/dmi.h>
1da177e4 LT	7	#include <linux/pci.h>
	8	#include <linux/init.h>
	9	#include "pci.h"
	10
	11
	12	static void __devinit pci_fixup_i450nx(struct pci_dev *d)
	13	{
	14	/*
	15	* i450NX -- Find and scan all secondary buses on all PXB's.
	16	*/
	17	int pxb, reg;
	18	u8 busno, suba, subb;
	19
	20	printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
	21	reg = 0xd0;
	22	for(pxb=0; pxb<2; pxb++) {
	23	pci_read_config_byte(d, reg++, &busno);
	24	pci_read_config_byte(d, reg++, &suba);
	25	pci_read_config_byte(d, reg++, &subb);
	26	DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
	27	if (busno)
	28	pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */
	29	if (suba < subb)
	30	pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */
	31	}
	32	pcibios_last_bus = -1;
	33	}
	34	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
	35
	36	static void __devinit pci_fixup_i450gx(struct pci_dev *d)
	37	{
	38	/*
	39	* i450GX and i450KX -- Find and scan all secondary buses.
	40	* (called separately for each PCI bridge found)
	41	*/
	42	u8 busno;
	43	pci_read_config_byte(d, 0x4a, &busno);
	44	printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
	45	pci_scan_bus(busno, &pci_root_ops, NULL);
	46	pcibios_last_bus = -1;
	47	}
	48	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
	49
	50	static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
	51	{
	52	/*
	53	* UM8886BF IDE controller sets region type bits incorrectly,
	54	* therefore they look like memory despite of them being I/O.
	55	*/
	56	int i;
	57
	58	printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
	59	for(i=0; i<4; i++)
	60	d->resource[i].flags \|= PCI_BASE_ADDRESS_SPACE_IO;
	61	}
	62	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
	63
	64	static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
	65	{
	66	/*
	67	* NCR 53C810 returns class code 0 (at least on some systems).
	68	* Fix class to be PCI_CLASS_STORAGE_SCSI
	69	*/
	70	if (!d->class) {
71	printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
72	d->class = PCI_CLASS_STORAGE_SCSI << 8;
73	}
74	}
75	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
76
1da177e4 LT	77	static void __devinit pci_fixup_latency(struct pci_dev *d)
	78	{
	79	/*
	80	* SiS 5597 and 5598 chipsets require latency timer set to
	81	* at most 32 to avoid lockups.
	82	*/
	83	DBG("PCI: Setting max latency to 32\n");
	84	pcibios_max_latency = 32;
	85	}
	86	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
	87	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
	88
	89	static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
	90	{
	91	/*
	92	* PIIX4 ACPI device: hardwired IRQ9
	93	*/
	94	d->irq = 9;
	95	}
	96	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
	97
	98	/*
	99	* Addresses issues with problems in the memory write queue timer in
	100	* certain VIA Northbridges. This bugfix is per VIA's specifications,
	101	* except for the KL133/KM133: clearing bit 5 on those Northbridges seems
	102	* to trigger a bug in its integrated ProSavage video card, which
	103	* causes screen corruption. We only clear bits 6 and 7 for that chipset,
	104	* until VIA can provide us with definitive information on why screen
	105	* corruption occurs, and what exactly those bits do.
	106	*
	107	* VIA 8363,8622,8361 Northbridges:
	108	* - bits 5, 6, 7 at offset 0x55 need to be turned off
	109	* VIA 8367 (KT266x) Northbridges:
	110	* - bits 5, 6, 7 at offset 0x95 need to be turned off
	111	* VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
	112	* - bits 6, 7 at offset 0x55 need to be turned off
	113	*/
	114
	115	#define VIA_8363_KL133_REVISION_ID 0x81
	116	#define VIA_8363_KM133_REVISION_ID 0x84
	117
	118	static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
	119	{
	120	u8 v;
	121	u8 revision;
	122	int where = 0x55;
	123	int mask = 0x1f; /* clear bits 5, 6, 7 by default */
	124
	125	pci_read_config_byte(d, PCI_REVISION_ID, &revision);
	126
	127	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
	128	/* fix pci bus latency issues resulted by NB bios error
	129	it appears on bug free^Wreduced kt266x's bios forces
	130	NB latency to zero */
	131	pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
	132
	133	where = 0x95; /* the memory write queue timer register is
	134	different for the KT266x's: 0x95 not 0x55 */
	135	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
	136	(revision == VIA_8363_KL133_REVISION_ID \|\|
	137	revision == VIA_8363_KM133_REVISION_ID)) {
	138	mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
	139	causes screen corruption on the KL133/KM133 */
	140	}
141
142	pci_read_config_byte(d, where, &v);
143	if (v & ~mask) {
144	printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
145	d->device, revision, where, v, mask, v & mask);
146	v &= mask;
147	pci_write_config_byte(d, where, v);
148	}
149	}
150	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
151	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
152	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
153	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
154
155	/*
156	* For some reasons Intel decided that certain parts of their
157	* 815, 845 and some other chipsets must look like PCI-to-PCI bridges
158	* while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
159	* BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
160	* to Intel terminology. These devices do forward all addresses from
161	* system to PCI bus no matter what are their window settings, so they are
162	* "transparent" (or subtractive decoding) from programmers point of view.
163	*/
164	static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
165	{
166	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
167	(dev->device & 0xff00) == 0x2400)
168	dev->transparent = 1;
169	}
170	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
171
172	/*
173	* Fixup for C1 Halt Disconnect problem on nForce2 systems.
174	*
175	* From information provided by "Allen Martin" <AMartin@nvidia.com>:
176	*
177	* A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
178	* sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
179	* This allows the state-machine and timer to return to a proper state within
180	* 80 ns of the CONNECT and probe appearing together. Since the CPU will not
181	* issue another HALT within 80 ns of the initial HALT, the failure condition
182	* is avoided.
183	*/
184	static void __init pci_fixup_nforce2(struct pci_dev *dev)
185	{
186	u32 val;
187
188	/*
189	* Chip Old value New value
190	* C17 0x1F0FFF01 0x1F01FF01
191	* C18D 0x9F0FFF01 0x9F01FF01
192	*
193	* Northbridge chip version may be determined by
194	* reading the PCI revision ID (0xC1 or greater is C18D).
195	*/
196	pci_read_config_dword(dev, 0x6c, &val);
197
198	/*
199	* Apply fixup if needed, but don't touch disconnect state
200	*/
201	if ((val & 0x00FF0000) != 0x00010000) {
202	printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
203	pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) \| 0x00010000);
204	}
205	}
206	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
207
208	/* Max PCI Express root ports */
209	#define MAX_PCIEROOT 6
210	static int quirk_aspm_offset[MAX_PCIEROOT << 3];
211
ff0d2f90	212	#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
1da177e4 LT	213
	214	static int quirk_pcie_aspm_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
	215	{
	216	return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
	217	}
	218
	219	/*
	220	* Replace the original pci bus ops for write with a new one that will filter
	221	* the request to insure ASPM cannot be enabled.
	222	*/
	223	static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
	224	{
	225	u8 offset;
	226
	227	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
	228
	229	if ((offset) && (where == offset))
	230	value = value & 0xfffffffc;
	231
	232	return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
	233	}
	234
	235	static struct pci_ops quirk_pcie_aspm_ops = {
	236	.read = quirk_pcie_aspm_read,
	237	.write = quirk_pcie_aspm_write,
	238	};
	239
	240	/*
	241	* Prevents PCI Express ASPM (Active State Power Management) being enabled.
	242	*
	243	* Save the register offset, where the ASPM control bits are located,
	244	* for each PCI Express device that is in the device list of
	245	* the root port in an array for fast indexing. Replace the bus ops
	246	* with the modified one.
	247	*/
	248	static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
	249	{
	250	int cap_base, i;
	251	struct pci_bus *pbus;
	252	struct pci_dev *dev;
	253
	254	if ((pbus = pdev->subordinate) == NULL)
	255	return;
	256
	257	/*
	258	* Check if the DID of pdev matches one of the six root ports. This
	259	* check is needed in the case this function is called directly by the
	260	* hot-plug driver.
	261	*/
	262	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) \|\|
	263	(pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
	264	return;
	265
	266	if (list_empty(&pbus->devices)) {
	267	/*
	268	* If no device is attached to the root port at power-up or
	269	* after hot-remove, the pbus->devices is empty and this code
	270	* will set the offsets to zero and the bus ops to parent's bus
	271	* ops, which is unmodified.
	272	*/
	273	for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
	274	quirk_aspm_offset[i] = 0;
	275
	276	pbus->ops = pbus->parent->ops;
277	} else {
278	/*
279	* If devices are attached to the root port at power-up or
280	* after hot-add, the code loops through the device list of
281	* each root port to save the register offsets and replace the
282	* bus ops.
283	*/
284	list_for_each_entry(dev, &pbus->devices, bus_list) {
285	/* There are 0 to 8 devices attached to this bus */
286	cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
287	quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10;
288	}
289	pbus->ops = &quirk_pcie_aspm_ops;
290	}
291	}
292	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk );
293	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk );
294	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk );
295	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk );
296	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk );
297	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk );
298
6b5c76b8 EO	299	/*
	300	* Fixup to mark boot BIOS video selected by BIOS before it changes
	301	*
	302	* From information provided by "Jon Smirl" <jonsmirl@gmail.com>
	303	*
	304	* The standard boot ROM sequence for an x86 machine uses the BIOS
	305	* to select an initial video card for boot display. This boot video
	306	* card will have it's BIOS copied to C0000 in system RAM.
	307	* IORESOURCE_ROM_SHADOW is used to associate the boot video
	308	* card with this copy. On laptops this copy has to be used since
	309	* the main ROM may be compressed or combined with another image.
	310	* See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
	311	* is marked here since the boot video device will be the only enabled
	312	* video device at this point.
	313	*/
	314
	315	static void __devinit pci_fixup_video(struct pci_dev *pdev)
	316	{
	317	struct pci_dev *bridge;
	318	struct pci_bus *bus;
	319	u16 config;
	320
	321	if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
	322	return;
	323
	324	/* Is VGA routed to us? */
	325	bus = pdev->bus;
	326	while (bus) {
	327	bridge = bus->self;
	328
	329	/*
	330	* From information provided by
	331	* "David Miller" <davem@davemloft.net>
	332	* The bridge control register is valid for PCI header
	333	* type BRIDGE, or CARDBUS. Host to PCI controllers use
	334	* PCI header type NORMAL.
	335	*/
	336	if (bridge
	337	&&((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
	338	\|\|(bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
	339	pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
	340	&config);
	341	if (!(config & PCI_BRIDGE_CTL_VGA))
	342	return;
	343	}
	344	bus = bus->parent;
	345	}
	346	pci_read_config_word(pdev, PCI_COMMAND, &config);
	347	if (config & (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) {
	348	pdev->resource[PCI_ROM_RESOURCE].flags \|= IORESOURCE_ROM_SHADOW;
	349	printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
	350	}
	351	}
	352	DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
	353
f8977d0a JB	354	/*
	355	* Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
	356	*
	357	* We pretend to bring them out of full D3 state, and restore the proper
	358	* IRQ, PCI cache line size, and BARs, otherwise the device won't function
	359	* properly. In some cases, the device will generate an interrupt on
4b3f686d	360	* the wrong IRQ line, causing any devices sharing the line it's
f8977d0a JB	361	* supposed to use to be disabled by the kernel's IRQ debug code.
	362	*/
	363	static u16 toshiba_line_size;
	364
1d373741	365	static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = {
f8977d0a JB	366	{
	367	.ident = "Toshiba PS5 based laptop",
	368	.matches = {
	369	DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
	370	DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
	371	},
	372	},
	373	{
	374	.ident = "Toshiba PSM4 based laptop",
	375	.matches = {
	376	DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
	377	DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
	378	},
	379	},
19272684 JB	380	{
	381	.ident = "Toshiba A40 based laptop",
	382	.matches = {
	383	DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
	384	DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
	385	},
	386	},
f8977d0a JB	387	{ }
	388	};
	389
	390	static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
	391	{
	392	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
	393	return; /* only applies to certain Toshibas (so far) */
	394
	395	dev->current_state = PCI_D3cold;
	396	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
	397	}
	398	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
	399	pci_pre_fixup_toshiba_ohci1394);
	400
	401	static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
	402	{
	403	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
	404	return; /* only applies to certain Toshibas (so far) */
	405
	406	/* Restore config space on Toshiba laptops */
f8977d0a	407	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
6e6ece5d	408	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
f8977d0a JB	409	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
	410	pci_resource_start(dev, 0));
	411	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
	412	pci_resource_start(dev, 1));
	413	}
	414	DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
	415	pci_post_fixup_toshiba_ohci1394);
a80da738 DV	416
	417
	418	/*
	419	* Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
	420	* configuration space.
	421	*/
	422	static void __devinit pci_early_fixup_cyrix_5530(struct pci_dev *dev)
	423	{
	424	u8 r;
	425	/* clear 'F4 Video Configuration Trap' bit */
	426	pci_read_config_byte(dev, 0x42, &r);
	427	r &= 0xfd;
	428	pci_write_config_byte(dev, 0x42, r);
	429	}
	430	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
	431	pci_early_fixup_cyrix_5530);