Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
46cba3dc ST |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
13 | * APIC code. In particular, we now have separate | |
14 | * handlers for edge and level triggered | |
15 | * interrupts. | |
16 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
17 | * allocation PCI to vector mapping, shared PCI | |
18 | * interrupts. | |
19 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
20 | * understandable. Clean up much of the old | |
21 | * IOSAPIC cruft. | |
22 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
23 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 24 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
25 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
26 | * vectors in iosapic_set_affinity(), | |
27 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
28 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
29 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
30 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
31 | * IOSAPIC mapping error | |
1da177e4 | 32 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
33 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
34 | * interrupt, vector, etc.) | |
35 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
36 | * pci_irq code. | |
1da177e4 | 37 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
38 | * Remove iosapic_address & gsi_base from |
39 | * external interfaces. Rationalize | |
40 | * __init/__devinit attributes. | |
1da177e4 | 41 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
42 | * Updated to work with irq migration necessary |
43 | * for CPU Hotplug | |
1da177e4 LT |
44 | */ |
45 | /* | |
46cba3dc ST |
46 | * Here is what the interrupt logic between a PCI device and the kernel looks |
47 | * like: | |
1da177e4 | 48 | * |
46cba3dc ST |
49 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
50 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
51 | * (the function number does not matter here because all functions share | |
52 | * the same interrupt lines). | |
1da177e4 | 53 | * |
46cba3dc ST |
54 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
55 | * controller. Multiple interrupt lines may have to share the same | |
56 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
57 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
58 | * which can be calculated as the sum of the controller's base GSI number | |
59 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 60 | * |
46cba3dc ST |
61 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
62 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
63 | * sent to the CPU. | |
1da177e4 | 64 | * |
46cba3dc ST |
65 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
66 | * used as architecture-independent interrupt handling mechanism in Linux. | |
67 | * As an IRQ is a number, we have to have | |
68 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
69 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
70 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 LT |
71 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
72 | * Please see also include/asm-ia64/hw_irq.h for those APIs. | |
73 | * | |
74 | * To sum up, there are three levels of mappings involved: | |
75 | * | |
76 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
77 | * | |
46cba3dc ST |
78 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
79 | * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ | |
80 | * (isa_irq) is the only exception in this source code. | |
1da177e4 | 81 | */ |
1da177e4 LT |
82 | |
83 | #include <linux/acpi.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/irq.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/list.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/smp.h> | |
1da177e4 | 90 | #include <linux/string.h> |
24eeb568 | 91 | #include <linux/bootmem.h> |
1da177e4 LT |
92 | |
93 | #include <asm/delay.h> | |
94 | #include <asm/hw_irq.h> | |
95 | #include <asm/io.h> | |
96 | #include <asm/iosapic.h> | |
97 | #include <asm/machvec.h> | |
98 | #include <asm/processor.h> | |
99 | #include <asm/ptrace.h> | |
100 | #include <asm/system.h> | |
101 | ||
1da177e4 LT |
102 | #undef DEBUG_INTERRUPT_ROUTING |
103 | ||
104 | #ifdef DEBUG_INTERRUPT_ROUTING | |
105 | #define DBG(fmt...) printk(fmt) | |
106 | #else | |
107 | #define DBG(fmt...) | |
108 | #endif | |
109 | ||
46cba3dc ST |
110 | #define NR_PREALLOCATE_RTE_ENTRIES \ |
111 | (PAGE_SIZE / sizeof(struct iosapic_rte_info)) | |
24eeb568 KK |
112 | #define RTE_PREALLOCATED (1) |
113 | ||
1da177e4 LT |
114 | static DEFINE_SPINLOCK(iosapic_lock); |
115 | ||
46cba3dc ST |
116 | /* |
117 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
118 | * vector. | |
119 | */ | |
e1b30a39 YI |
120 | |
121 | #define NO_REF_RTE 0 | |
122 | ||
c5e3f9e5 YI |
123 | static struct iosapic { |
124 | char __iomem *addr; /* base address of IOSAPIC */ | |
125 | unsigned int gsi_base; /* GSI base */ | |
126 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
127 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ | |
128 | #ifdef CONFIG_NUMA | |
129 | unsigned short node; /* numa node association via pxm */ | |
130 | #endif | |
c1726d6f | 131 | spinlock_t lock; /* lock for indirect reg access */ |
c5e3f9e5 | 132 | } iosapic_lists[NR_IOSAPICS]; |
1da177e4 | 133 | |
24eeb568 | 134 | struct iosapic_rte_info { |
c5e3f9e5 | 135 | struct list_head rte_list; /* RTEs sharing the same vector */ |
24eeb568 KK |
136 | char rte_index; /* IOSAPIC RTE index */ |
137 | int refcnt; /* reference counter */ | |
138 | unsigned int flags; /* flags */ | |
c5e3f9e5 | 139 | struct iosapic *iosapic; |
24eeb568 KK |
140 | } ____cacheline_aligned; |
141 | ||
142 | static struct iosapic_intr_info { | |
46cba3dc ST |
143 | struct list_head rtes; /* RTEs using this vector (empty => |
144 | * not an IOSAPIC interrupt) */ | |
24eeb568 | 145 | int count; /* # of RTEs that shares this vector */ |
46cba3dc ST |
146 | u32 low32; /* current value of low word of |
147 | * Redirection table entry */ | |
24eeb568 | 148 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 149 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
150 | unsigned char polarity: 1; /* interrupt polarity |
151 | * (see iosapic.h) */ | |
1da177e4 | 152 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
4bbdec7a | 153 | } iosapic_intr_info[NR_IRQS]; |
1da177e4 | 154 | |
0e888adc | 155 | static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ |
1da177e4 | 156 | |
24eeb568 KK |
157 | static int iosapic_kmalloc_ok; |
158 | static LIST_HEAD(free_rte_list); | |
1da177e4 | 159 | |
c1726d6f YI |
160 | static inline void |
161 | iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) | |
162 | { | |
163 | unsigned long flags; | |
164 | ||
165 | spin_lock_irqsave(&iosapic->lock, flags); | |
166 | __iosapic_write(iosapic->addr, reg, val); | |
167 | spin_unlock_irqrestore(&iosapic->lock, flags); | |
168 | } | |
169 | ||
1da177e4 LT |
170 | /* |
171 | * Find an IOSAPIC associated with a GSI | |
172 | */ | |
173 | static inline int | |
174 | find_iosapic (unsigned int gsi) | |
175 | { | |
176 | int i; | |
177 | ||
0e888adc | 178 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
179 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
180 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
181 | return i; |
182 | } | |
183 | ||
184 | return -1; | |
185 | } | |
186 | ||
4bbdec7a | 187 | static inline int __gsi_to_irq(unsigned int gsi) |
1da177e4 | 188 | { |
4bbdec7a | 189 | int irq; |
1da177e4 | 190 | struct iosapic_intr_info *info; |
24eeb568 | 191 | struct iosapic_rte_info *rte; |
1da177e4 | 192 | |
4bbdec7a YI |
193 | for (irq = 0; irq < NR_IRQS; irq++) { |
194 | info = &iosapic_intr_info[irq]; | |
24eeb568 | 195 | list_for_each_entry(rte, &info->rtes, rte_list) |
c5e3f9e5 | 196 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
4bbdec7a YI |
197 | return irq; |
198 | } | |
1da177e4 LT |
199 | return -1; |
200 | } | |
201 | ||
202 | /* | |
203 | * Translate GSI number to the corresponding IA-64 interrupt vector. If no | |
204 | * entry exists, return -1. | |
205 | */ | |
206 | inline int | |
207 | gsi_to_vector (unsigned int gsi) | |
208 | { | |
4bbdec7a | 209 | int irq = __gsi_to_irq(gsi); |
e1b30a39 | 210 | if (check_irq_used(irq) < 0) |
4bbdec7a YI |
211 | return -1; |
212 | return irq_to_vector(irq); | |
1da177e4 LT |
213 | } |
214 | ||
215 | int | |
216 | gsi_to_irq (unsigned int gsi) | |
217 | { | |
24eeb568 KK |
218 | unsigned long flags; |
219 | int irq; | |
4bbdec7a | 220 | |
24eeb568 | 221 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 222 | irq = __gsi_to_irq(gsi); |
24eeb568 | 223 | spin_unlock_irqrestore(&iosapic_lock, flags); |
24eeb568 KK |
224 | return irq; |
225 | } | |
226 | ||
4bbdec7a | 227 | static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi) |
24eeb568 KK |
228 | { |
229 | struct iosapic_rte_info *rte; | |
230 | ||
4bbdec7a | 231 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 232 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 KK |
233 | return rte; |
234 | return NULL; | |
1da177e4 LT |
235 | } |
236 | ||
237 | static void | |
4bbdec7a | 238 | set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) |
1da177e4 LT |
239 | { |
240 | unsigned long pol, trigger, dmode; | |
241 | u32 low32, high32; | |
1da177e4 LT |
242 | int rte_index; |
243 | char redir; | |
24eeb568 | 244 | struct iosapic_rte_info *rte; |
4bbdec7a | 245 | ia64_vector vector = irq_to_vector(irq); |
1da177e4 LT |
246 | |
247 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
248 | ||
4bbdec7a | 249 | rte = find_rte(irq, gsi); |
24eeb568 | 250 | if (!rte) |
1da177e4 LT |
251 | return; /* not an IOSAPIC interrupt */ |
252 | ||
24eeb568 | 253 | rte_index = rte->rte_index; |
4bbdec7a YI |
254 | pol = iosapic_intr_info[irq].polarity; |
255 | trigger = iosapic_intr_info[irq].trigger; | |
256 | dmode = iosapic_intr_info[irq].dmode; | |
1da177e4 LT |
257 | |
258 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
259 | ||
260 | #ifdef CONFIG_SMP | |
4bbdec7a | 261 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); |
1da177e4 LT |
262 | #endif |
263 | ||
264 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
265 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
266 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
267 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
268 | vector); | |
269 | ||
270 | /* dest contains both id and eid */ | |
271 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
272 | ||
c1726d6f YI |
273 | iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
274 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
4bbdec7a YI |
275 | iosapic_intr_info[irq].low32 = low32; |
276 | iosapic_intr_info[irq].dest = dest; | |
1da177e4 LT |
277 | } |
278 | ||
279 | static void | |
46cba3dc | 280 | nop (unsigned int irq) |
1da177e4 LT |
281 | { |
282 | /* do nothing... */ | |
283 | } | |
284 | ||
a7956113 ZN |
285 | |
286 | #ifdef CONFIG_KEXEC | |
287 | void | |
288 | kexec_disable_iosapic(void) | |
289 | { | |
290 | struct iosapic_intr_info *info; | |
291 | struct iosapic_rte_info *rte; | |
4bbdec7a YI |
292 | ia64_vector vec; |
293 | int irq; | |
294 | ||
295 | for (irq = 0; irq < NR_IRQS; irq++) { | |
296 | info = &iosapic_intr_info[irq]; | |
297 | vec = irq_to_vector(irq); | |
a7956113 ZN |
298 | list_for_each_entry(rte, &info->rtes, |
299 | rte_list) { | |
c1726d6f | 300 | iosapic_write(rte->iosapic, |
a7956113 ZN |
301 | IOSAPIC_RTE_LOW(rte->rte_index), |
302 | IOSAPIC_MASK|vec); | |
c5e3f9e5 | 303 | iosapic_eoi(rte->iosapic->addr, vec); |
a7956113 ZN |
304 | } |
305 | } | |
306 | } | |
307 | #endif | |
308 | ||
1da177e4 LT |
309 | static void |
310 | mask_irq (unsigned int irq) | |
311 | { | |
1da177e4 LT |
312 | u32 low32; |
313 | int rte_index; | |
24eeb568 | 314 | struct iosapic_rte_info *rte; |
1da177e4 | 315 | |
4bbdec7a | 316 | if (list_empty(&iosapic_intr_info[irq].rtes)) |
1da177e4 LT |
317 | return; /* not an IOSAPIC interrupt! */ |
318 | ||
e3a8f7b8 | 319 | /* set only the mask bit */ |
4bbdec7a YI |
320 | low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
321 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 322 | rte_index = rte->rte_index; |
c1726d6f | 323 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 324 | } |
1da177e4 LT |
325 | } |
326 | ||
327 | static void | |
328 | unmask_irq (unsigned int irq) | |
329 | { | |
1da177e4 LT |
330 | u32 low32; |
331 | int rte_index; | |
24eeb568 | 332 | struct iosapic_rte_info *rte; |
1da177e4 | 333 | |
4bbdec7a | 334 | if (list_empty(&iosapic_intr_info[irq].rtes)) |
1da177e4 LT |
335 | return; /* not an IOSAPIC interrupt! */ |
336 | ||
4bbdec7a YI |
337 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; |
338 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 339 | rte_index = rte->rte_index; |
c1726d6f | 340 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 341 | } |
1da177e4 LT |
342 | } |
343 | ||
344 | ||
345 | static void | |
346 | iosapic_set_affinity (unsigned int irq, cpumask_t mask) | |
347 | { | |
348 | #ifdef CONFIG_SMP | |
1da177e4 LT |
349 | u32 high32, low32; |
350 | int dest, rte_index; | |
1da177e4 | 351 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
24eeb568 | 352 | struct iosapic_rte_info *rte; |
c1726d6f | 353 | struct iosapic *iosapic; |
1da177e4 LT |
354 | |
355 | irq &= (~IA64_IRQ_REDIRECTED); | |
1da177e4 LT |
356 | |
357 | if (cpus_empty(mask)) | |
358 | return; | |
359 | ||
360 | dest = cpu_physical_id(first_cpu(mask)); | |
361 | ||
4bbdec7a | 362 | if (list_empty(&iosapic_intr_info[irq].rtes)) |
1da177e4 LT |
363 | return; /* not an IOSAPIC interrupt */ |
364 | ||
365 | set_irq_affinity_info(irq, dest, redir); | |
366 | ||
367 | /* dest contains both id and eid */ | |
368 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
369 | ||
4bbdec7a | 370 | low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
e3a8f7b8 YI |
371 | if (redir) |
372 | /* change delivery mode to lowest priority */ | |
373 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
374 | else | |
375 | /* change delivery mode to fixed */ | |
376 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
377 | ||
4bbdec7a YI |
378 | iosapic_intr_info[irq].low32 = low32; |
379 | iosapic_intr_info[irq].dest = dest; | |
380 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
c1726d6f | 381 | iosapic = rte->iosapic; |
e3a8f7b8 | 382 | rte_index = rte->rte_index; |
c1726d6f YI |
383 | iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
384 | iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 385 | } |
1da177e4 LT |
386 | #endif |
387 | } | |
388 | ||
389 | /* | |
390 | * Handlers for level-triggered interrupts. | |
391 | */ | |
392 | ||
393 | static unsigned int | |
394 | iosapic_startup_level_irq (unsigned int irq) | |
395 | { | |
396 | unmask_irq(irq); | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static void | |
401 | iosapic_end_level_irq (unsigned int irq) | |
402 | { | |
403 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 404 | struct iosapic_rte_info *rte; |
1da177e4 | 405 | |
41503def | 406 | move_native_irq(irq); |
4bbdec7a | 407 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 408 | iosapic_eoi(rte->iosapic->addr, vec); |
1da177e4 LT |
409 | } |
410 | ||
411 | #define iosapic_shutdown_level_irq mask_irq | |
412 | #define iosapic_enable_level_irq unmask_irq | |
413 | #define iosapic_disable_level_irq mask_irq | |
414 | #define iosapic_ack_level_irq nop | |
415 | ||
e253eb0c | 416 | struct irq_chip irq_type_iosapic_level = { |
06344db3 | 417 | .name = "IO-SAPIC-level", |
1da177e4 LT |
418 | .startup = iosapic_startup_level_irq, |
419 | .shutdown = iosapic_shutdown_level_irq, | |
420 | .enable = iosapic_enable_level_irq, | |
421 | .disable = iosapic_disable_level_irq, | |
422 | .ack = iosapic_ack_level_irq, | |
423 | .end = iosapic_end_level_irq, | |
e253eb0c KH |
424 | .mask = mask_irq, |
425 | .unmask = unmask_irq, | |
1da177e4 LT |
426 | .set_affinity = iosapic_set_affinity |
427 | }; | |
428 | ||
429 | /* | |
430 | * Handlers for edge-triggered interrupts. | |
431 | */ | |
432 | ||
433 | static unsigned int | |
434 | iosapic_startup_edge_irq (unsigned int irq) | |
435 | { | |
436 | unmask_irq(irq); | |
437 | /* | |
438 | * IOSAPIC simply drops interrupts pended while the | |
439 | * corresponding pin was masked, so we can't know if an | |
440 | * interrupt is pending already. Let's hope not... | |
441 | */ | |
442 | return 0; | |
443 | } | |
444 | ||
445 | static void | |
446 | iosapic_ack_edge_irq (unsigned int irq) | |
447 | { | |
a8553acd | 448 | irq_desc_t *idesc = irq_desc + irq; |
1da177e4 | 449 | |
41503def | 450 | move_native_irq(irq); |
1da177e4 LT |
451 | /* |
452 | * Once we have recorded IRQ_PENDING already, we can mask the | |
453 | * interrupt for real. This prevents IRQ storms from unhandled | |
454 | * devices. | |
455 | */ | |
46cba3dc ST |
456 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == |
457 | (IRQ_PENDING|IRQ_DISABLED)) | |
1da177e4 LT |
458 | mask_irq(irq); |
459 | } | |
460 | ||
461 | #define iosapic_enable_edge_irq unmask_irq | |
462 | #define iosapic_disable_edge_irq nop | |
463 | #define iosapic_end_edge_irq nop | |
464 | ||
e253eb0c | 465 | struct irq_chip irq_type_iosapic_edge = { |
06344db3 | 466 | .name = "IO-SAPIC-edge", |
1da177e4 LT |
467 | .startup = iosapic_startup_edge_irq, |
468 | .shutdown = iosapic_disable_edge_irq, | |
469 | .enable = iosapic_enable_edge_irq, | |
470 | .disable = iosapic_disable_edge_irq, | |
471 | .ack = iosapic_ack_edge_irq, | |
472 | .end = iosapic_end_edge_irq, | |
e253eb0c KH |
473 | .mask = mask_irq, |
474 | .unmask = unmask_irq, | |
1da177e4 LT |
475 | .set_affinity = iosapic_set_affinity |
476 | }; | |
477 | ||
478 | unsigned int | |
479 | iosapic_version (char __iomem *addr) | |
480 | { | |
481 | /* | |
482 | * IOSAPIC Version Register return 32 bit structure like: | |
483 | * { | |
484 | * unsigned int version : 8; | |
485 | * unsigned int reserved1 : 8; | |
486 | * unsigned int max_redir : 8; | |
487 | * unsigned int reserved2 : 8; | |
488 | * } | |
489 | */ | |
c1726d6f | 490 | return __iosapic_read(addr, IOSAPIC_VERSION); |
1da177e4 LT |
491 | } |
492 | ||
4bbdec7a | 493 | static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol) |
24eeb568 | 494 | { |
4bbdec7a | 495 | int i, irq = -ENOSPC, min_count = -1; |
24eeb568 KK |
496 | struct iosapic_intr_info *info; |
497 | ||
498 | /* | |
499 | * shared vectors for edge-triggered interrupts are not | |
500 | * supported yet | |
501 | */ | |
502 | if (trigger == IOSAPIC_EDGE) | |
40598cbe | 503 | return -EINVAL; |
24eeb568 | 504 | |
4bbdec7a | 505 | for (i = 0; i <= NR_IRQS; i++) { |
24eeb568 KK |
506 | info = &iosapic_intr_info[i]; |
507 | if (info->trigger == trigger && info->polarity == pol && | |
f8c087f3 YI |
508 | (info->dmode == IOSAPIC_FIXED || |
509 | info->dmode == IOSAPIC_LOWEST_PRIORITY) && | |
510 | can_request_irq(i, IRQF_SHARED)) { | |
24eeb568 | 511 | if (min_count == -1 || info->count < min_count) { |
4bbdec7a | 512 | irq = i; |
24eeb568 KK |
513 | min_count = info->count; |
514 | } | |
515 | } | |
516 | } | |
4bbdec7a | 517 | return irq; |
24eeb568 KK |
518 | } |
519 | ||
1da177e4 LT |
520 | /* |
521 | * if the given vector is already owned by other, | |
522 | * assign a new vector for the other and make the vector available | |
523 | */ | |
524 | static void __init | |
4bbdec7a | 525 | iosapic_reassign_vector (int irq) |
1da177e4 | 526 | { |
4bbdec7a | 527 | int new_irq; |
1da177e4 | 528 | |
4bbdec7a YI |
529 | if (!list_empty(&iosapic_intr_info[irq].rtes)) { |
530 | new_irq = create_irq(); | |
531 | if (new_irq < 0) | |
3b5cc090 | 532 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
46cba3dc | 533 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
4bbdec7a YI |
534 | irq_to_vector(irq), irq_to_vector(new_irq)); |
535 | memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq], | |
1da177e4 | 536 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
537 | INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes); |
538 | list_move(iosapic_intr_info[irq].rtes.next, | |
539 | &iosapic_intr_info[new_irq].rtes); | |
540 | memset(&iosapic_intr_info[irq], 0, | |
46cba3dc | 541 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
542 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; |
543 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); | |
1da177e4 LT |
544 | } |
545 | } | |
546 | ||
24eeb568 KK |
547 | static struct iosapic_rte_info *iosapic_alloc_rte (void) |
548 | { | |
549 | int i; | |
550 | struct iosapic_rte_info *rte; | |
551 | int preallocated = 0; | |
552 | ||
553 | if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) { | |
46cba3dc ST |
554 | rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * |
555 | NR_PREALLOCATE_RTE_ENTRIES); | |
24eeb568 KK |
556 | if (!rte) |
557 | return NULL; | |
558 | for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++) | |
559 | list_add(&rte->rte_list, &free_rte_list); | |
560 | } | |
561 | ||
562 | if (!list_empty(&free_rte_list)) { | |
46cba3dc ST |
563 | rte = list_entry(free_rte_list.next, struct iosapic_rte_info, |
564 | rte_list); | |
24eeb568 KK |
565 | list_del(&rte->rte_list); |
566 | preallocated++; | |
567 | } else { | |
568 | rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC); | |
569 | if (!rte) | |
570 | return NULL; | |
571 | } | |
572 | ||
573 | memset(rte, 0, sizeof(struct iosapic_rte_info)); | |
574 | if (preallocated) | |
575 | rte->flags |= RTE_PREALLOCATED; | |
576 | ||
577 | return rte; | |
578 | } | |
579 | ||
580 | static void iosapic_free_rte (struct iosapic_rte_info *rte) | |
581 | { | |
582 | if (rte->flags & RTE_PREALLOCATED) | |
583 | list_add_tail(&rte->rte_list, &free_rte_list); | |
584 | else | |
585 | kfree(rte); | |
586 | } | |
587 | ||
4bbdec7a | 588 | static inline int irq_is_shared (int irq) |
24eeb568 | 589 | { |
4bbdec7a | 590 | return (iosapic_intr_info[irq].count > 1); |
24eeb568 KK |
591 | } |
592 | ||
14454a1b | 593 | static int |
4bbdec7a | 594 | register_intr (unsigned int gsi, int irq, unsigned char delivery, |
1da177e4 LT |
595 | unsigned long polarity, unsigned long trigger) |
596 | { | |
597 | irq_desc_t *idesc; | |
598 | struct hw_interrupt_type *irq_type; | |
1da177e4 | 599 | int index; |
24eeb568 | 600 | struct iosapic_rte_info *rte; |
1da177e4 LT |
601 | |
602 | index = find_iosapic(gsi); | |
603 | if (index < 0) { | |
46cba3dc ST |
604 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
605 | __FUNCTION__, gsi); | |
14454a1b | 606 | return -ENODEV; |
1da177e4 LT |
607 | } |
608 | ||
4bbdec7a | 609 | rte = find_rte(irq, gsi); |
24eeb568 KK |
610 | if (!rte) { |
611 | rte = iosapic_alloc_rte(); | |
612 | if (!rte) { | |
46cba3dc ST |
613 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
614 | __FUNCTION__); | |
14454a1b | 615 | return -ENOMEM; |
24eeb568 KK |
616 | } |
617 | ||
c5e3f9e5 YI |
618 | rte->iosapic = &iosapic_lists[index]; |
619 | rte->rte_index = gsi - rte->iosapic->gsi_base; | |
24eeb568 | 620 | rte->refcnt++; |
4bbdec7a YI |
621 | list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes); |
622 | iosapic_intr_info[irq].count++; | |
0e888adc | 623 | iosapic_lists[index].rtes_inuse++; |
24eeb568 | 624 | } |
e1b30a39 | 625 | else if (rte->refcnt == NO_REF_RTE) { |
4bbdec7a | 626 | struct iosapic_intr_info *info = &iosapic_intr_info[irq]; |
e1b30a39 YI |
627 | if (info->count > 0 && |
628 | (info->trigger != trigger || info->polarity != polarity)){ | |
46cba3dc ST |
629 | printk (KERN_WARNING |
630 | "%s: cannot override the interrupt\n", | |
631 | __FUNCTION__); | |
14454a1b | 632 | return -EINVAL; |
24eeb568 | 633 | } |
e1b30a39 YI |
634 | rte->refcnt++; |
635 | iosapic_intr_info[irq].count++; | |
636 | iosapic_lists[index].rtes_inuse++; | |
24eeb568 KK |
637 | } |
638 | ||
4bbdec7a YI |
639 | iosapic_intr_info[irq].polarity = polarity; |
640 | iosapic_intr_info[irq].dmode = delivery; | |
641 | iosapic_intr_info[irq].trigger = trigger; | |
1da177e4 LT |
642 | |
643 | if (trigger == IOSAPIC_EDGE) | |
644 | irq_type = &irq_type_iosapic_edge; | |
645 | else | |
646 | irq_type = &irq_type_iosapic_level; | |
647 | ||
4bbdec7a | 648 | idesc = irq_desc + irq; |
d1bef4ed IM |
649 | if (idesc->chip != irq_type) { |
650 | if (idesc->chip != &no_irq_type) | |
46cba3dc ST |
651 | printk(KERN_WARNING |
652 | "%s: changing vector %d from %s to %s\n", | |
4bbdec7a | 653 | __FUNCTION__, irq_to_vector(irq), |
351a5839 | 654 | idesc->chip->name, irq_type->name); |
d1bef4ed | 655 | idesc->chip = irq_type; |
1da177e4 | 656 | } |
14454a1b | 657 | return 0; |
1da177e4 LT |
658 | } |
659 | ||
660 | static unsigned int | |
4bbdec7a | 661 | get_target_cpu (unsigned int gsi, int irq) |
1da177e4 LT |
662 | { |
663 | #ifdef CONFIG_SMP | |
664 | static int cpu = -1; | |
ff741906 | 665 | extern int cpe_vector; |
1da177e4 | 666 | |
24eeb568 KK |
667 | /* |
668 | * In case of vector shared by multiple RTEs, all RTEs that | |
669 | * share the vector need to use the same destination CPU. | |
670 | */ | |
4bbdec7a YI |
671 | if (!list_empty(&iosapic_intr_info[irq].rtes)) |
672 | return iosapic_intr_info[irq].dest; | |
24eeb568 | 673 | |
1da177e4 LT |
674 | /* |
675 | * If the platform supports redirection via XTP, let it | |
676 | * distribute interrupts. | |
677 | */ | |
678 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
679 | return cpu_physical_id(smp_processor_id()); | |
680 | ||
681 | /* | |
682 | * Some interrupts (ACPI SCI, for instance) are registered | |
683 | * before the BSP is marked as online. | |
684 | */ | |
685 | if (!cpu_online(smp_processor_id())) | |
686 | return cpu_physical_id(smp_processor_id()); | |
687 | ||
ff741906 | 688 | #ifdef CONFIG_ACPI |
4bbdec7a | 689 | if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR) |
b88e9265 | 690 | return get_cpei_target_cpu(); |
ff741906 AR |
691 | #endif |
692 | ||
1da177e4 LT |
693 | #ifdef CONFIG_NUMA |
694 | { | |
695 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
696 | cpumask_t cpu_mask; | |
697 | ||
698 | iosapic_index = find_iosapic(gsi); | |
699 | if (iosapic_index < 0 || | |
700 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
701 | goto skip_numa_setup; | |
702 | ||
703 | cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node); | |
704 | ||
705 | for_each_cpu_mask(numa_cpu, cpu_mask) { | |
706 | if (!cpu_online(numa_cpu)) | |
707 | cpu_clear(numa_cpu, cpu_mask); | |
708 | } | |
709 | ||
710 | num_cpus = cpus_weight(cpu_mask); | |
711 | ||
712 | if (!num_cpus) | |
713 | goto skip_numa_setup; | |
714 | ||
4bbdec7a YI |
715 | /* Use irq assignment to distribute across cpus in node */ |
716 | cpu_index = irq % num_cpus; | |
1da177e4 LT |
717 | |
718 | for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++) | |
719 | numa_cpu = next_cpu(numa_cpu, cpu_mask); | |
720 | ||
721 | if (numa_cpu != NR_CPUS) | |
722 | return cpu_physical_id(numa_cpu); | |
723 | } | |
724 | skip_numa_setup: | |
725 | #endif | |
726 | /* | |
727 | * Otherwise, round-robin interrupt vectors across all the | |
728 | * processors. (It'd be nice if we could be smarter in the | |
729 | * case of NUMA.) | |
730 | */ | |
731 | do { | |
732 | if (++cpu >= NR_CPUS) | |
733 | cpu = 0; | |
734 | } while (!cpu_online(cpu)); | |
735 | ||
736 | return cpu_physical_id(cpu); | |
46cba3dc | 737 | #else /* CONFIG_SMP */ |
1da177e4 LT |
738 | return cpu_physical_id(smp_processor_id()); |
739 | #endif | |
740 | } | |
741 | ||
742 | /* | |
743 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
744 | * methods. This provides an interface to register those interrupts and | |
745 | * program the IOSAPIC RTE. | |
746 | */ | |
747 | int | |
748 | iosapic_register_intr (unsigned int gsi, | |
749 | unsigned long polarity, unsigned long trigger) | |
750 | { | |
4bbdec7a | 751 | int irq, mask = 1, err; |
1da177e4 LT |
752 | unsigned int dest; |
753 | unsigned long flags; | |
24eeb568 KK |
754 | struct iosapic_rte_info *rte; |
755 | u32 low32; | |
40598cbe | 756 | |
1da177e4 LT |
757 | /* |
758 | * If this GSI has already been registered (i.e., it's a | |
759 | * shared interrupt, or we lost a race to register it), | |
760 | * don't touch the RTE. | |
761 | */ | |
762 | spin_lock_irqsave(&iosapic_lock, flags); | |
4bbdec7a YI |
763 | irq = __gsi_to_irq(gsi); |
764 | if (irq > 0) { | |
765 | rte = find_rte(irq, gsi); | |
e1b30a39 YI |
766 | if(iosapic_intr_info[irq].count == 0) { |
767 | assign_irq_vector(irq); | |
768 | dynamic_irq_init(irq); | |
769 | } else if (rte->refcnt != NO_REF_RTE) { | |
770 | rte->refcnt++; | |
771 | goto unlock_iosapic_lock; | |
772 | } | |
773 | } else | |
774 | irq = create_irq(); | |
24eeb568 KK |
775 | |
776 | /* If vector is running out, we try to find a sharable vector */ | |
eb21ab24 | 777 | if (irq < 0) { |
4bbdec7a YI |
778 | irq = iosapic_find_sharable_irq(trigger, polarity); |
779 | if (irq < 0) | |
40598cbe | 780 | goto unlock_iosapic_lock; |
4bbdec7a | 781 | } |
1da177e4 | 782 | |
4bbdec7a YI |
783 | spin_lock(&irq_desc[irq].lock); |
784 | dest = get_target_cpu(gsi, irq); | |
785 | err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, | |
e3a8f7b8 YI |
786 | polarity, trigger); |
787 | if (err < 0) { | |
4bbdec7a | 788 | irq = err; |
40598cbe | 789 | goto unlock_all; |
1da177e4 | 790 | } |
e3a8f7b8 YI |
791 | |
792 | /* | |
793 | * If the vector is shared and already unmasked for other | |
794 | * interrupt sources, don't mask it. | |
795 | */ | |
4bbdec7a YI |
796 | low32 = iosapic_intr_info[irq].low32; |
797 | if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK)) | |
e3a8f7b8 | 798 | mask = 0; |
4bbdec7a | 799 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
800 | |
801 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
802 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
803 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 804 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
40598cbe | 805 | unlock_all: |
4bbdec7a | 806 | spin_unlock(&irq_desc[irq].lock); |
40598cbe YI |
807 | unlock_iosapic_lock: |
808 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
4bbdec7a | 809 | return irq; |
1da177e4 LT |
810 | } |
811 | ||
1da177e4 LT |
812 | void |
813 | iosapic_unregister_intr (unsigned int gsi) | |
814 | { | |
815 | unsigned long flags; | |
4bbdec7a | 816 | int irq, index; |
1da177e4 | 817 | irq_desc_t *idesc; |
24eeb568 | 818 | u32 low32; |
1da177e4 | 819 | unsigned long trigger, polarity; |
24eeb568 KK |
820 | unsigned int dest; |
821 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
822 | |
823 | /* | |
824 | * If the irq associated with the gsi is not found, | |
825 | * iosapic_unregister_intr() is unbalanced. We need to check | |
826 | * this again after getting locks. | |
827 | */ | |
828 | irq = gsi_to_irq(gsi); | |
829 | if (irq < 0) { | |
46cba3dc ST |
830 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
831 | gsi); | |
1da177e4 LT |
832 | WARN_ON(1); |
833 | return; | |
834 | } | |
1da177e4 | 835 | |
40598cbe | 836 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 837 | if ((rte = find_rte(irq, gsi)) == NULL) { |
e3a8f7b8 YI |
838 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
839 | gsi); | |
840 | WARN_ON(1); | |
841 | goto out; | |
842 | } | |
1da177e4 | 843 | |
e3a8f7b8 YI |
844 | if (--rte->refcnt > 0) |
845 | goto out; | |
1da177e4 | 846 | |
40598cbe | 847 | idesc = irq_desc + irq; |
e1b30a39 | 848 | rte->refcnt = NO_REF_RTE; |
40598cbe | 849 | |
e3a8f7b8 | 850 | /* Mask the interrupt */ |
4bbdec7a | 851 | low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK; |
c1726d6f | 852 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32); |
1da177e4 | 853 | |
4bbdec7a | 854 | iosapic_intr_info[irq].count--; |
e3a8f7b8 YI |
855 | index = find_iosapic(gsi); |
856 | iosapic_lists[index].rtes_inuse--; | |
857 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
24eeb568 | 858 | |
4bbdec7a YI |
859 | trigger = iosapic_intr_info[irq].trigger; |
860 | polarity = iosapic_intr_info[irq].polarity; | |
861 | dest = iosapic_intr_info[irq].dest; | |
e3a8f7b8 YI |
862 | printk(KERN_INFO |
863 | "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
864 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
865 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 866 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
24eeb568 | 867 | |
e1b30a39 | 868 | if (iosapic_intr_info[irq].count == 0) { |
451fe00c | 869 | #ifdef CONFIG_SMP |
e3a8f7b8 YI |
870 | /* Clear affinity */ |
871 | cpus_setall(idesc->affinity); | |
451fe00c | 872 | #endif |
e3a8f7b8 | 873 | /* Clear the interrupt information */ |
e1b30a39 YI |
874 | iosapic_intr_info[irq].dest = 0; |
875 | iosapic_intr_info[irq].dmode = 0; | |
876 | iosapic_intr_info[irq].polarity = 0; | |
877 | iosapic_intr_info[irq].trigger = 0; | |
4bbdec7a | 878 | iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
1da177e4 | 879 | |
e1b30a39 YI |
880 | /* Destroy and reserve IRQ */ |
881 | destroy_and_reserve_irq(irq); | |
1da177e4 | 882 | } |
24eeb568 | 883 | out: |
40598cbe | 884 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 | 885 | } |
1da177e4 LT |
886 | |
887 | /* | |
888 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
889 | */ |
890 | int __init | |
891 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
892 | int iosapic_vector, u16 eid, u16 id, | |
893 | unsigned long polarity, unsigned long trigger) | |
894 | { | |
895 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
896 | unsigned char delivery; | |
eb21ab24 | 897 | int irq, vector, mask = 0; |
1da177e4 LT |
898 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
899 | ||
900 | switch (int_type) { | |
901 | case ACPI_INTERRUPT_PMI: | |
e1b30a39 YI |
902 | irq = vector = iosapic_vector; |
903 | bind_irq_vector(irq, vector); | |
1da177e4 LT |
904 | /* |
905 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
906 | * we need to make sure the vector is available | |
907 | */ | |
4bbdec7a | 908 | iosapic_reassign_vector(irq); |
1da177e4 LT |
909 | delivery = IOSAPIC_PMI; |
910 | break; | |
911 | case ACPI_INTERRUPT_INIT: | |
eb21ab24 YI |
912 | irq = create_irq(); |
913 | if (irq < 0) | |
3b5cc090 | 914 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
eb21ab24 | 915 | vector = irq_to_vector(irq); |
1da177e4 LT |
916 | delivery = IOSAPIC_INIT; |
917 | break; | |
918 | case ACPI_INTERRUPT_CPEI: | |
e1b30a39 YI |
919 | irq = vector = IA64_CPE_VECTOR; |
920 | BUG_ON(bind_irq_vector(irq, vector)); | |
1da177e4 LT |
921 | delivery = IOSAPIC_LOWEST_PRIORITY; |
922 | mask = 1; | |
923 | break; | |
924 | default: | |
46cba3dc ST |
925 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__, |
926 | int_type); | |
1da177e4 LT |
927 | return -1; |
928 | } | |
929 | ||
4bbdec7a | 930 | register_intr(gsi, irq, delivery, polarity, trigger); |
1da177e4 | 931 | |
46cba3dc ST |
932 | printk(KERN_INFO |
933 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
934 | " vector %d\n", | |
1da177e4 LT |
935 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
936 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
937 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
938 | cpu_logical_id(dest), dest, vector); | |
939 | ||
4bbdec7a | 940 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
941 | return vector; |
942 | } | |
943 | ||
1da177e4 LT |
944 | /* |
945 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 | 946 | */ |
0f7ac29e | 947 | void __devinit |
1da177e4 LT |
948 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, |
949 | unsigned long polarity, | |
950 | unsigned long trigger) | |
951 | { | |
4bbdec7a | 952 | int vector, irq; |
1da177e4 LT |
953 | unsigned int dest = cpu_physical_id(smp_processor_id()); |
954 | ||
e1b30a39 YI |
955 | irq = vector = isa_irq_to_vector(isa_irq); |
956 | BUG_ON(bind_irq_vector(irq, vector)); | |
4bbdec7a | 957 | register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, polarity, trigger); |
1da177e4 LT |
958 | |
959 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
960 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
961 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
962 | cpu_logical_id(dest), dest, vector); | |
963 | ||
4bbdec7a | 964 | set_rte(gsi, irq, dest, 1); |
1da177e4 LT |
965 | } |
966 | ||
967 | void __init | |
968 | iosapic_system_init (int system_pcat_compat) | |
969 | { | |
4bbdec7a | 970 | int irq; |
1da177e4 | 971 | |
4bbdec7a YI |
972 | for (irq = 0; irq < NR_IRQS; ++irq) { |
973 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; | |
46cba3dc | 974 | /* mark as unused */ |
4bbdec7a | 975 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); |
e1b30a39 YI |
976 | |
977 | iosapic_intr_info[irq].count = 0; | |
24eeb568 | 978 | } |
1da177e4 LT |
979 | |
980 | pcat_compat = system_pcat_compat; | |
981 | if (pcat_compat) { | |
982 | /* | |
46cba3dc ST |
983 | * Disable the compatibility mode interrupts (8259 style), |
984 | * needs IN/OUT support enabled. | |
1da177e4 | 985 | */ |
46cba3dc ST |
986 | printk(KERN_INFO |
987 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
988 | __FUNCTION__); | |
1da177e4 LT |
989 | outb(0xff, 0xA1); |
990 | outb(0xff, 0x21); | |
991 | } | |
992 | } | |
993 | ||
0e888adc KK |
994 | static inline int |
995 | iosapic_alloc (void) | |
996 | { | |
997 | int index; | |
998 | ||
999 | for (index = 0; index < NR_IOSAPICS; index++) | |
1000 | if (!iosapic_lists[index].addr) | |
1001 | return index; | |
1002 | ||
1003 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__); | |
1004 | return -1; | |
1005 | } | |
1006 | ||
1007 | static inline void | |
1008 | iosapic_free (int index) | |
1009 | { | |
1010 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
1011 | } | |
1012 | ||
1013 | static inline int | |
1014 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
1015 | { | |
1016 | int index; | |
1017 | unsigned int gsi_end, base, end; | |
1018 | ||
1019 | /* check gsi range */ | |
1020 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
1021 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1022 | if (!iosapic_lists[index].addr) | |
1023 | continue; | |
1024 | ||
1025 | base = iosapic_lists[index].gsi_base; | |
1026 | end = base + iosapic_lists[index].num_rte - 1; | |
1027 | ||
e6d1ba5c | 1028 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1029 | continue; /* OK */ |
1030 | ||
1031 | return -EBUSY; | |
1032 | } | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | int __devinit | |
1da177e4 LT |
1037 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
1038 | { | |
0e888adc | 1039 | int num_rte, err, index; |
1da177e4 LT |
1040 | unsigned int isa_irq, ver; |
1041 | char __iomem *addr; | |
0e888adc KK |
1042 | unsigned long flags; |
1043 | ||
1044 | spin_lock_irqsave(&iosapic_lock, flags); | |
c1726d6f YI |
1045 | index = find_iosapic(gsi_base); |
1046 | if (index >= 0) { | |
1047 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1048 | return -EBUSY; | |
1049 | } | |
1050 | ||
e3a8f7b8 YI |
1051 | addr = ioremap(phys_addr, 0); |
1052 | ver = iosapic_version(addr); | |
e3a8f7b8 YI |
1053 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1054 | iounmap(addr); | |
1055 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1056 | return err; | |
1057 | } | |
1da177e4 | 1058 | |
e3a8f7b8 YI |
1059 | /* |
1060 | * The MAX_REDIR register holds the highest input pin number | |
1061 | * (starting from 0). We add 1 so that we can use it for | |
1062 | * number of pins (= RTEs) | |
1063 | */ | |
1064 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1065 | |
e3a8f7b8 YI |
1066 | index = iosapic_alloc(); |
1067 | iosapic_lists[index].addr = addr; | |
1068 | iosapic_lists[index].gsi_base = gsi_base; | |
1069 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1070 | #ifdef CONFIG_NUMA |
e3a8f7b8 | 1071 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1072 | #endif |
c1726d6f | 1073 | spin_lock_init(&iosapic_lists[index].lock); |
0e888adc | 1074 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 LT |
1075 | |
1076 | if ((gsi_base == 0) && pcat_compat) { | |
1077 | /* | |
46cba3dc ST |
1078 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1079 | * these may get reprogrammed later on with data from the ACPI | |
1080 | * Interrupt Source Override table. | |
1da177e4 LT |
1081 | */ |
1082 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1083 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1084 | IOSAPIC_POL_HIGH, | |
1085 | IOSAPIC_EDGE); | |
1da177e4 | 1086 | } |
0e888adc KK |
1087 | return 0; |
1088 | } | |
1089 | ||
1090 | #ifdef CONFIG_HOTPLUG | |
1091 | int | |
1092 | iosapic_remove (unsigned int gsi_base) | |
1093 | { | |
1094 | int index, err = 0; | |
1095 | unsigned long flags; | |
1096 | ||
1097 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
1098 | index = find_iosapic(gsi_base); |
1099 | if (index < 0) { | |
1100 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
1101 | __FUNCTION__, gsi_base); | |
1102 | goto out; | |
1103 | } | |
0e888adc | 1104 | |
e3a8f7b8 YI |
1105 | if (iosapic_lists[index].rtes_inuse) { |
1106 | err = -EBUSY; | |
1107 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
1108 | __FUNCTION__, gsi_base); | |
1109 | goto out; | |
0e888adc | 1110 | } |
e3a8f7b8 YI |
1111 | |
1112 | iounmap(iosapic_lists[index].addr); | |
1113 | iosapic_free(index); | |
0e888adc KK |
1114 | out: |
1115 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1116 | return err; | |
1da177e4 | 1117 | } |
0e888adc | 1118 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 LT |
1119 | |
1120 | #ifdef CONFIG_NUMA | |
0e888adc | 1121 | void __devinit |
1da177e4 LT |
1122 | map_iosapic_to_node(unsigned int gsi_base, int node) |
1123 | { | |
1124 | int index; | |
1125 | ||
1126 | index = find_iosapic(gsi_base); | |
1127 | if (index < 0) { | |
1128 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
1129 | __FUNCTION__, gsi_base); | |
1130 | return; | |
1131 | } | |
1132 | iosapic_lists[index].node = node; | |
1133 | return; | |
1134 | } | |
1135 | #endif | |
24eeb568 KK |
1136 | |
1137 | static int __init iosapic_enable_kmalloc (void) | |
1138 | { | |
1139 | iosapic_kmalloc_ok = 1; | |
1140 | return 0; | |
1141 | } | |
1142 | core_initcall (iosapic_enable_kmalloc); |