[deliverable/linux.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/ratelimit.h>
#include <linux/acpi.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
		return;

	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	for_each_cpu_mask(i, cleanup_mask)
		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __get_cpu_var(vector_irq)[vector];
		if (irq < 0)
			continue;

		desc = irq_desc + irq;
		cfg = irq_cfg + irq;
		raw_spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpu_isset(me, cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__get_cpu_var(vector_irq)[vector] = -1;
		cpu_clear(me, vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		raw_spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.flags =	IRQF_DISABLED,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	dynamic_irq_cleanup(irq);

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

			if (__ratelimit(&ratelimit)) {
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);
		struct irq_desc *desc = irq_to_desc(irq);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irqs_this_cpu(irq, desc);
		} else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);
		struct irq_desc *desc = irq_to_desc(irq);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irqs_this_cpu(irq, desc);
		} else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

/*
 * KVM uses this interrupt to force a cpu out of guest mode
 */
static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	struct irq_desc *desc;
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	desc = irq_desc + irq;
	desc->status |= IRQ_PER_CPU;
	desc->chip = &irq_type_ia64_lsapic;
	if (action)
		setup_irq(irq, action);
	set_irq_handler(irq, handle_percpu_irq);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
#ifdef CONFIG_ACPI
	acpi_boot_init();
#endif
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
	if (vector_domain_type != VECTOR_DOMAIN_NONE)
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
#endif
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
1da177e4 LT	25	#include <linux/ptrace.h>
	26	#include <linux/random.h> /* for rand_initialize_irq() */
	27	#include <linux/signal.h>
	28	#include <linux/smp.h>
1da177e4 LT	29	#include <linux/threads.h>
1da177e4 LT	30	#include <linux/bitops.h>
b6cf2583	31	#include <linux/irq.h>
7683a3f9	32	#include <linux/ratelimit.h>
4de0a759	33	#include <linux/acpi.h>
1da177e4 LT	34
	35	#include <asm/delay.h>
	36	#include <asm/intrinsics.h>
	37	#include <asm/io.h>
	38	#include <asm/hw_irq.h>
	39	#include <asm/machvec.h>
	40	#include <asm/pgtable.h>
	41	#include <asm/system.h>
3be44b9c	42	#include <asm/tlbflush.h>
1da177e4 LT	43
	44	#ifdef CONFIG_PERFMON
	45	# include <asm/perfmon.h>
	46	#endif
	47
	48	#define IRQ_DEBUG 0
	49
e1b30a39 YI	50	#define IRQ_VECTOR_UNASSIGNED (0)
	51
	52	#define IRQ_UNUSED (0)
	53	#define IRQ_USED (1)
	54	#define IRQ_RSVD (2)
	55
10083072 MM	56	/* These can be overridden in platform_irq_init */
	57	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	58	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	59
1da177e4 LT	60	/* default base addr of IPI table */
	61	void __iomem ipi_base_addr = ((void __iomem )
	62	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	63
4994be1b YI	64	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	65
1da177e4 LT	66	/*
	67	* Legacy IRQ to IA-64 vector translation table.
	68	*/
	69	__u8 isa_irq_to_vector_map[16] = {
	70	/* 8259 IRQ translation, first 16 entries */
	71	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	72	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	73	};
	74	EXPORT_SYMBOL(isa_irq_to_vector_map);
	75
e1b30a39 YI	76	DEFINE_SPINLOCK(vector_lock);
	77
	78	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	79	[0 ... NR_IRQS - 1] = {
	80	.vector = IRQ_VECTOR_UNASSIGNED,
	81	.domain = CPU_MASK_NONE
	82	}
e1b30a39 YI	83	};
	84
	85	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	86	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	87	};
e1b30a39 YI	88
6ffbc823 KK	89	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	90	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	91	};
4994be1b YI	92
e1b30a39 YI	93	static int irq_status[NR_IRQS] = {
	94	[0 ... NR_IRQS -1] = IRQ_UNUSED
	95	};
	96
	97	int check_irq_used(int irq)
	98	{
	99	if (irq_status[irq] == IRQ_USED)
	100	return 1;
	101
	102	return -1;
	103	}
	104
e1b30a39 YI	105	static inline int find_unassigned_irq(void)
	106	{
	107	int irq;
	108
	109	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	110	if (irq_status[irq] == IRQ_UNUSED)
	111	return irq;
	112	return -ENOSPC;
	113	}
	114
4994be1b	115	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	116	{
4994be1b	117	cpumask_t mask;
6ffbc823	118	int pos, vector;
4994be1b YI	119
	120	cpus_and(mask, domain, cpu_online_map);
	121	if (cpus_empty(mask))
	122	return -EINVAL;
e1b30a39	123
4994be1b	124	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	125	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	126	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	127	if (!cpus_empty(mask))
4994be1b YI	128	continue;
6ffbc823	129	return vector;
4994be1b	130	}
e1b30a39 YI	131	return -ENOSPC;
	132	}
	133
4994be1b	134	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	135	{
4994be1b	136	cpumask_t mask;
6ffbc823	137	int cpu;
4994be1b	138	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	139
6bde71ec KK	140	BUG_ON((unsigned)irq >= NR_IRQS);
	141	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	142
4994be1b YI	143	cpus_and(mask, domain, cpu_online_map);
	144	if (cpus_empty(mask))
	145	return -EINVAL;
	146	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	147	return 0;
4994be1b	148	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	149	return -EBUSY;
4994be1b	150	for_each_cpu_mask(cpu, mask)
e1b30a39	151	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	152	cfg->vector = vector;
4994be1b YI	153	cfg->domain = domain;
e1b30a39	154	irq_status[irq] = IRQ_USED;
6ffbc823	155	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	156	return 0;
	157	}
	158
4994be1b	159	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	160	{
	161	unsigned long flags;
	162	int ret;
	163
	164	spin_lock_irqsave(&vector_lock, flags);
4994be1b	165	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	166	spin_unlock_irqrestore(&vector_lock, flags);
	167	return ret;
	168	}
	169
cd378f18	170	static void __clear_irq_vector(int irq)
e1b30a39	171	{
6ffbc823	172	int vector, cpu;
4994be1b YI	173	cpumask_t mask;
	174	cpumask_t domain;
	175	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	176
e1b30a39	177	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	178	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	179	vector = cfg->vector;
	180	domain = cfg->domain;
	181	cpus_and(mask, cfg->domain, cpu_online_map);
	182	for_each_cpu_mask(cpu, mask)
17764d24	183	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	184	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	185	cfg->domain = CPU_MASK_NONE;
e1b30a39	186	irq_status[irq] = IRQ_UNUSED;
6ffbc823	187	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	188	}
	189
	190	static void clear_irq_vector(int irq)
	191	{
	192	unsigned long flags;
	193
	194	spin_lock_irqsave(&vector_lock, flags);
	195	__clear_irq_vector(irq);
e1b30a39 YI	196	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	197	}
1da177e4 LT	198
1da177e4 LT	199	int
85cbc503	200	ia64_native_assign_irq_vector (int irq)
1da177e4	201	{
e1b30a39	202	unsigned long flags;
4994be1b	203	int vector, cpu;
373167e8	204	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	205
4994be1b YI	206	vector = -ENOSPC;
e1b30a39	207
4994be1b	208	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	209	for_each_online_cpu(cpu) {
	210	domain = vector_allocation_domain(cpu);
	211	vector = find_unassigned_vector(domain);
	212	if (vector >= 0)
	213	break;
	214	}
e1b30a39 YI	215	if (vector < 0)
e1b30a39 YI	216	goto out;
8f5ad1a8 YI	217	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	218	irq = vector;
4994be1b	219	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	220	out:
4994be1b	221	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	222	return vector;
	223	}
	224
	225	void
85cbc503	226	ia64_native_free_irq_vector (int vector)
1da177e4	227	{
e1b30a39 YI	228	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	229	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	230	return;
e1b30a39	231	clear_irq_vector(vector);
1da177e4 LT	232	}
1da177e4 LT	233
10083072 MM	234	int
	235	reserve_irq_vector (int vector)
	236	{
10083072 MM	237	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	238	vector > IA64_LAST_DEVICE_VECTOR)
	239	return -EINVAL;
4994be1b	240	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	241	}
10083072	242
e1b30a39 YI	243	/*
	244	* Initialize vector_irq on a new cpu. This function must be called
	245	* with vector_lock held.
	246	*/
	247	void __setup_vector_irq(int cpu)
	248	{
	249	int irq, vector;
	250
	251	/* Clear vector_irq */
	252	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	253	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	254	/* Mark the inuse vectors */
e1b30a39 YI	255	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	256	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	257	continue;
	258	vector = irq_to_vector(irq);
	259	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	260	}
	261	}
	262
e5bd762b	263	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
a6cd6322	264
d080d397 YI	265	static enum vector_domain_type {
	266	VECTOR_DOMAIN_NONE,
	267	VECTOR_DOMAIN_PERCPU
	268	} vector_domain_type = VECTOR_DOMAIN_NONE;
	269
4994be1b YI	270	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	271	{
d080d397 YI	272	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	273	return cpumask_of_cpu(cpu);
4994be1b YI	274	return CPU_MASK_ALL;
	275	}
	276
a6cd6322 KK	277	static int __irq_prepare_move(int irq, int cpu)
	278	{
	279	struct irq_cfg *cfg = &irq_cfg[irq];
	280	int vector;
	281	cpumask_t domain;
	282
	283	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	284	return -EBUSY;
	285	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	286	return -EINVAL;
	287	if (cpu_isset(cpu, cfg->domain))
	288	return 0;
	289	domain = vector_allocation_domain(cpu);
	290	vector = find_unassigned_vector(domain);
	291	if (vector < 0)
	292	return -ENOSPC;
	293	cfg->move_in_progress = 1;
	294	cfg->old_domain = cfg->domain;
	295	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	296	cfg->domain = CPU_MASK_NONE;
	297	BUG_ON(__bind_irq_vector(irq, vector, domain));
	298	return 0;
	299	}
	300
	301	int irq_prepare_move(int irq, int cpu)
	302	{
	303	unsigned long flags;
	304	int ret;
	305
	306	spin_lock_irqsave(&vector_lock, flags);
	307	ret = __irq_prepare_move(irq, cpu);
	308	spin_unlock_irqrestore(&vector_lock, flags);
	309	return ret;
	310	}
	311
	312	void irq_complete_move(unsigned irq)
	313	{
	314	struct irq_cfg *cfg = &irq_cfg[irq];
	315	cpumask_t cleanup_mask;
	316	int i;
	317
	318	if (likely(!cfg->move_in_progress))
	319	return;
	320
	321	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
	322	return;
	323
	324	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	325	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	326	for_each_cpu_mask(i, cleanup_mask)
	327	platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	328	cfg->move_in_progress = 0;
	329	}
	330
	331	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	332	{
	333	int me = smp_processor_id();
	334	ia64_vector vector;
	335	unsigned long flags;
	336
	337	for (vector = IA64_FIRST_DEVICE_VECTOR;
	338	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	339	int irq;
	340	struct irq_desc *desc;
341	struct irq_cfg *cfg;
342	irq = __get_cpu_var(vector_irq)[vector];
343	if (irq < 0)
344	continue;
345
346	desc = irq_desc + irq;
347	cfg = irq_cfg + irq;
239007b8	348	raw_spin_lock(&desc->lock);
a6cd6322 KK	349	if (!cfg->move_cleanup_count)
	350	goto unlock;
	351
	352	if (!cpu_isset(me, cfg->old_domain))
	353	goto unlock;
	354
	355	spin_lock_irqsave(&vector_lock, flags);
	356	__get_cpu_var(vector_irq)[vector] = -1;
	357	cpu_clear(me, vector_table[vector]);
	358	spin_unlock_irqrestore(&vector_lock, flags);
	359	cfg->move_cleanup_count--;
	360	unlock:
239007b8	361	raw_spin_unlock(&desc->lock);
a6cd6322 KK	362	}
	363	return IRQ_HANDLED;
	364	}
	365
	366	static struct irqaction irq_move_irqaction = {
	367	.handler = smp_irq_move_cleanup_interrupt,
	368	.flags = IRQF_DISABLED,
	369	.name = "irq_move"
	370	};
	371
d080d397 YI	372	static int __init parse_vector_domain(char *arg)
	373	{
	374	if (!arg)
	375	return -EINVAL;
	376	if (!strcmp(arg, "percpu")) {
	377	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	378	no_int_routing = 1;
	379	}
074ff856	380	return 0;
d080d397 YI	381	}
	382	early_param("vector", parse_vector_domain);
	383	#else
	384	static cpumask_t vector_allocation_domain(int cpu)
	385	{
	386	return CPU_MASK_ALL;
	387	}
	388	#endif
	389
4994be1b	390
e1b30a39 YI	391	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	392	{
216fcd29 KK	393	unsigned long flags;
216fcd29 KK	394
e1b30a39 YI	395	dynamic_irq_cleanup(irq);
e1b30a39 YI	396
216fcd29 KK	397	spin_lock_irqsave(&vector_lock, flags);
	398	__clear_irq_vector(irq);
	399	irq_status[irq] = IRQ_RSVD;
	400	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	401	}
10083072 MM	402
b6cf2583 EB	403	/*
	404	* Dynamic irq allocate and deallocation for MSI
	405	*/
	406	int create_irq(void)
	407	{
e1b30a39	408	unsigned long flags;
4994be1b	409	int irq, vector, cpu;
373167e8	410	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	411
4994be1b	412	irq = vector = -ENOSPC;
e1b30a39	413	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	414	for_each_online_cpu(cpu) {
	415	domain = vector_allocation_domain(cpu);
	416	vector = find_unassigned_vector(domain);
	417	if (vector >= 0)
	418	break;
	419	}
e1b30a39 YI	420	if (vector < 0)
	421	goto out;
	422	irq = find_unassigned_irq();
	423	if (irq < 0)
	424	goto out;
4994be1b	425	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	426	out:
	427	spin_unlock_irqrestore(&vector_lock, flags);
	428	if (irq >= 0)
	429	dynamic_irq_init(irq);
	430	return irq;
b6cf2583 EB	431	}
	432
	433	void destroy_irq(unsigned int irq)
	434	{
	435	dynamic_irq_cleanup(irq);
e1b30a39	436	clear_irq_vector(irq);
b6cf2583 EB	437	}
b6cf2583 EB	438
1da177e4 LT	439	#ifdef CONFIG_SMP
1da177e4 LT	440	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	441	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	442	#else
1da177e4 LT	443	# define IS_RESCHEDULE(vec) (0)
3be44b9c	444	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	445	#endif
	446	/*
	447	* That's where the IVT branches when we get an external
	448	* interrupt. This branches to the correct hardware IRQ handler via
	449	* function ptr.
	450	*/
	451	void
	452	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	453	{
7d12e780	454	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	455	unsigned long saved_tpr;
	456
	457	#if IRQ_DEBUG
	458	{
	459	unsigned long bsp, sp;
	460
	461	/*
	462	* Note: if the interrupt happened while executing in
	463	* the context switch routine (ia64_switch_to), we may
	464	* get a spurious stack overflow here. This is
	465	* because the register and the memory stack are not
	466	* switched atomically.
	467	*/
	468	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	469	sp = ia64_getreg(_IA64_REG_SP);
	470
	471	if ((sp - bsp) < 1024) {
7683a3f9	472	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
1da177e4	473
7683a3f9	474	if (__ratelimit(&ratelimit)) {
1da177e4 LT	475	printk("ia64_handle_irq: DANGER: less than "
	476	"1KB of free stack space!!\n"
	477	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	478	}
	479	}
	480	}
	481	#endif /* IRQ_DEBUG */
	482
	483	/*
	484	* Always set TPR to limit maximum interrupt nesting depth to
	485	* 16 (without this, it would be ~240, which could easily lead
	486	* to kernel stack overflows).
	487	*/
	488	irq_enter();
	489	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	490	ia64_srlz_d();
	491	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	492	int irq = local_vector_to_irq(vector);
7c730ccd	493	struct irq_desc *desc = irq_to_desc(irq);
66f3e6af	494
3be44b9c JS	495	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	496	smp_local_flush_tlb();
66f3e6af	497	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	498	} else if (unlikely(IS_RESCHEDULE(vector))) {
66f3e6af	499	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	500	} else {
1da177e4 LT	501	ia64_setreg(_IA64_REG_CR_TPR, vector);
	502	ia64_srlz_d();
	503
17764d24 KK	504	if (unlikely(irq < 0)) {
	505	printk(KERN_ERR "%s: Unexpected interrupt "
	506	"vector %d on CPU %d is not mapped "
d4ed8084	507	"to any IRQ!\n", __func__, vector,
17764d24 KK	508	smp_processor_id());
	509	} else
	510	generic_handle_irq(irq);
1da177e4 LT	511
	512	/*
	513	* Disable interrupts and send EOI:
	514	*/
	515	local_irq_disable();
	516	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	517	}
	518	ia64_eoi();
	519	vector = ia64_get_ivr();
	520	}
	521	/*
	522	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	523	* handler needs to be able to wait for further keyboard interrupts, which can't
	524	* come through until ia64_eoi() has been done.
	525	*/
	526	irq_exit();
7d12e780	527	set_irq_regs(old_regs);
1da177e4 LT	528	}
	529
	530	#ifdef CONFIG_HOTPLUG_CPU
	531	/*
	532	* This function emulates a interrupt processing when a cpu is about to be
	533	* brought down.
	534	*/
	535	void ia64_process_pending_intr(void)
	536	{
	537	ia64_vector vector;
	538	unsigned long saved_tpr;
	539	extern unsigned int vectors_in_migration[NR_IRQS];
	540
	541	vector = ia64_get_ivr();
	542
66f3e6af JS	543	irq_enter();
	544	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	545	ia64_srlz_d();
1da177e4 LT	546
	547	/*
	548	* Perform normal interrupt style processing
	549	*/
	550	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	551	int irq = local_vector_to_irq(vector);
7c730ccd	552	struct irq_desc *desc = irq_to_desc(irq);
66f3e6af	553
3be44b9c JS	554	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	555	smp_local_flush_tlb();
66f3e6af	556	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	557	} else if (unlikely(IS_RESCHEDULE(vector))) {
66f3e6af	558	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	559	} else {
8c1addbc TL	560	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	561
1da177e4 LT	562	ia64_setreg(_IA64_REG_CR_TPR, vector);
	563	ia64_srlz_d();
	564
	565	/*
	566	* Now try calling normal ia64_handle_irq as it would have got called
	567	* from a real intr handler. Try passing null for pt_regs, hopefully
	568	* it will work. I hope it works!.
	569	* Probably could shared code.
	570	*/
17764d24 KK	571	if (unlikely(irq < 0)) {
	572	printk(KERN_ERR "%s: Unexpected interrupt "
	573	"vector %d on CPU %d not being mapped "
d4ed8084	574	"to any IRQ!!\n", __func__, vector,
17764d24 KK	575	smp_processor_id());
	576	} else {
	577	vectors_in_migration[irq]=0;
	578	generic_handle_irq(irq);
	579	}
8c1addbc	580	set_irq_regs(old_regs);
1da177e4 LT	581
	582	/*
	583	* Disable interrupts and send EOI
	584	*/
	585	local_irq_disable();
	586	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	587	}
	588	ia64_eoi();
	589	vector = ia64_get_ivr();
	590	}
	591	irq_exit();
	592	}
	593	#endif
	594
	595
	596	#ifdef CONFIG_SMP
1da177e4	597
9b3377f9 JS	598	static irqreturn_t dummy_handler (int irq, void *dev_id)
	599	{
	600	BUG();
	601	}
	602
1da177e4 LT	603	static struct irqaction ipi_irqaction = {
1da177e4 LT	604	.handler = handle_IPI,
121a4226	605	.flags = IRQF_DISABLED,
1da177e4 LT	606	.name = "IPI"
1da177e4 LT	607	};
9b3377f9	608
32f88400 MT	609	/*
	610	* KVM uses this interrupt to force a cpu out of guest mode
	611	*/
9b3377f9 JS	612	static struct irqaction resched_irqaction = {
9b3377f9 JS	613	.handler = dummy_handler,
38515e90	614	.flags = IRQF_DISABLED,
9b3377f9 JS	615	.name = "resched"
9b3377f9 JS	616	};
3be44b9c JS	617
	618	static struct irqaction tlb_irqaction = {
	619	.handler = dummy_handler,
5329571b	620	.flags = IRQF_DISABLED,
3be44b9c JS	621	.name = "tlb_flush"
	622	};
	623
1da177e4 LT	624	#endif
	625
	626	void
85cbc503	627	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4	628	{
86bc3dfe	629	struct irq_desc *desc;
1da177e4 LT	630	unsigned int irq;
1da177e4 LT	631
e1b30a39	632	irq = vec;
4994be1b	633	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
e1b30a39 YI	634	desc = irq_desc + irq;
	635	desc->status \|= IRQ_PER_CPU;
	636	desc->chip = &irq_type_ia64_lsapic;
	637	if (action)
	638	setup_irq(irq, action);
5d4bff94	639	set_irq_handler(irq, handle_percpu_irq);
1da177e4 LT	640	}
	641
	642	void __init
85cbc503	643	ia64_native_register_ipi(void)
1da177e4	644	{
1da177e4 LT	645	#ifdef CONFIG_SMP
1da177e4 LT	646	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	647	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	648	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	649	#endif
	650	}
	651
	652	void __init
	653	init_IRQ (void)
	654	{
4de0a759 TL	655	#ifdef CONFIG_ACPI
	656	acpi_boot_init();
	657	#endif
85cbc503 IY	658	ia64_register_ipi();
	659	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	660	#ifdef CONFIG_SMP
a6cd6322	661	#if defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG)
09b366b7	662	if (vector_domain_type != VECTOR_DOMAIN_NONE)
a6cd6322	663	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
a6cd6322	664	#endif
1da177e4 LT	665	#endif
	666	#ifdef CONFIG_PERFMON
	667	pfm_init_percpu();
	668	#endif
	669	platform_irq_init();
	670	}
	671
	672	void
	673	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	674	{
	675	void __iomem *ipi_addr;
	676	unsigned long ipi_data;
	677	unsigned long phys_cpu_id;
	678
1da177e4	679	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	680
	681	/*
	682	* cpu number is in 8bit ID and 8bit EID
	683	*/
	684
	685	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	686	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	687
	688	writeq(ipi_data, ipi_addr);
	689	}