[deliverable/linux.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/ratelimit.h>
#include <linux/acpi.h>
#include <linux/sched.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpumask_and(&mask, &domain, cpu_online_mask);
	if (cpumask_empty(&mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpumask_and(&mask, &domain, &vector_table[vector]);
		if (!cpumask_empty(&mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpumask_and(&mask, &domain, cpu_online_mask);
	if (cpumask_empty(&mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu(cpu, &mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpumask_or(&vector_table[vector], &vector_table[vector], &domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpumask_andnot(&vector_table[vector], &vector_table[vector], &domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpumask_test_cpu(cpu, &irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return *cpumask_of(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpumask_test_cpu(cpu, &cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpumask_test_cpu(smp_processor_id(), &cfg->old_domain)))
		return;

	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
	cfg->move_cleanup_count = cpumask_weight(&cleanup_mask);
	for_each_cpu(i, &cleanup_mask)
		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __this_cpu_read(vector_irq[vector]);
		if (irq < 0)
			continue;

		desc = irq_to_desc(irq);
		cfg = irq_cfg + irq;
		raw_spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpumask_test_cpu(me, &cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__this_cpu_write(vector_irq[vector], -1);
		cpumask_clear_cpu(me, &vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		raw_spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	irq_init_desc(irq);
	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		irq_init_desc(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	irq_init_desc(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

			if (__ratelimit(&ratelimit)) {
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irq_this_cpu(irq);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			scheduler_ipi();
			kstat_incr_irq_this_cpu(irq);
		} else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irq_this_cpu(irq);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irq_this_cpu(irq);
		} else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.name =		"IPI"
};

/*
 * KVM uses this interrupt to force a cpu out of guest mode
 */
static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	irq_set_status_flags(irq, IRQ_PER_CPU);
	irq_set_chip(irq, &irq_type_ia64_lsapic);
	if (action)
		setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
#ifdef CONFIG_ACPI
	acpi_boot_init();
#endif
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
	if (vector_domain_type != VECTOR_DOMAIN_NONE)
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
#endif
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
1da177e4	25	#include <linux/ptrace.h>
1da177e4 LT	26	#include <linux/signal.h>
1da177e4 LT	27	#include <linux/smp.h>
1da177e4 LT	28	#include <linux/threads.h>
1da177e4 LT	29	#include <linux/bitops.h>
b6cf2583	30	#include <linux/irq.h>
7683a3f9	31	#include <linux/ratelimit.h>
4de0a759	32	#include <linux/acpi.h>
184748cc	33	#include <linux/sched.h>
1da177e4 LT	34
	35	#include <asm/delay.h>
	36	#include <asm/intrinsics.h>
	37	#include <asm/io.h>
	38	#include <asm/hw_irq.h>
	39	#include <asm/machvec.h>
	40	#include <asm/pgtable.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	/* These can be overridden in platform_irq_init */
	56	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	57	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	58
1da177e4 LT	59	/* default base addr of IPI table */
	60	void __iomem ipi_base_addr = ((void __iomem )
	61	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	62
4994be1b YI	63	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	64
1da177e4 LT	65	/*
	66	* Legacy IRQ to IA-64 vector translation table.
	67	*/
	68	__u8 isa_irq_to_vector_map[16] = {
	69	/* 8259 IRQ translation, first 16 entries */
	70	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	71	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	72	};
	73	EXPORT_SYMBOL(isa_irq_to_vector_map);
	74
e1b30a39 YI	75	DEFINE_SPINLOCK(vector_lock);
	76
	77	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	78	[0 ... NR_IRQS - 1] = {
	79	.vector = IRQ_VECTOR_UNASSIGNED,
	80	.domain = CPU_MASK_NONE
	81	}
e1b30a39 YI	82	};
	83
	84	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	85	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	86	};
e1b30a39 YI	87
6ffbc823 KK	88	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	89	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	90	};
4994be1b YI	91
e1b30a39 YI	92	static int irq_status[NR_IRQS] = {
	93	[0 ... NR_IRQS -1] = IRQ_UNUSED
	94	};
	95
e1b30a39 YI	96	static inline int find_unassigned_irq(void)
	97	{
	98	int irq;
	99
	100	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	101	if (irq_status[irq] == IRQ_UNUSED)
	102	return irq;
	103	return -ENOSPC;
	104	}
	105
4994be1b	106	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	107	{
4994be1b	108	cpumask_t mask;
6ffbc823	109	int pos, vector;
4994be1b	110
7d7f9848	111	cpumask_and(&mask, &domain, cpu_online_mask);
5d2068da	112	if (cpumask_empty(&mask))
4994be1b	113	return -EINVAL;
e1b30a39	114
4994be1b	115	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823	116	vector = IA64_FIRST_DEVICE_VECTOR + pos;
5d2068da RR	117	cpumask_and(&mask, &domain, &vector_table[vector]);
5d2068da RR	118	if (!cpumask_empty(&mask))
4994be1b	119	continue;
6ffbc823	120	return vector;
4994be1b	121	}
e1b30a39 YI	122	return -ENOSPC;
	123	}
	124
4994be1b	125	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	126	{
4994be1b	127	cpumask_t mask;
6ffbc823	128	int cpu;
4994be1b	129	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	130
6bde71ec KK	131	BUG_ON((unsigned)irq >= NR_IRQS);
	132	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	133
7d7f9848	134	cpumask_and(&mask, &domain, cpu_online_mask);
5d2068da	135	if (cpumask_empty(&mask))
4994be1b	136	return -EINVAL;
5d2068da	137	if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain))
e1b30a39	138	return 0;
4994be1b	139	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	140	return -EBUSY;
5d2068da	141	for_each_cpu(cpu, &mask)
e1b30a39	142	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	143	cfg->vector = vector;
4994be1b YI	144	cfg->domain = domain;
e1b30a39	145	irq_status[irq] = IRQ_USED;
5d2068da	146	cpumask_or(&vector_table[vector], &vector_table[vector], &domain);
e1b30a39 YI	147	return 0;
	148	}
	149
4994be1b	150	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	151	{
	152	unsigned long flags;
	153	int ret;
	154
	155	spin_lock_irqsave(&vector_lock, flags);
4994be1b	156	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	157	spin_unlock_irqrestore(&vector_lock, flags);
	158	return ret;
	159	}
	160
cd378f18	161	static void __clear_irq_vector(int irq)
e1b30a39	162	{
6ffbc823	163	int vector, cpu;
4994be1b YI	164	cpumask_t domain;
4994be1b YI	165	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	166
e1b30a39	167	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	168	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	169	vector = cfg->vector;
	170	domain = cfg->domain;
51f7bd85	171	for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask)
17764d24	172	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	173	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	174	cfg->domain = CPU_MASK_NONE;
e1b30a39	175	irq_status[irq] = IRQ_UNUSED;
6a4bd8d1	176	cpumask_andnot(&vector_table[vector], &vector_table[vector], &domain);
cd378f18 YI	177	}
	178
	179	static void clear_irq_vector(int irq)
	180	{
	181	unsigned long flags;
	182
	183	spin_lock_irqsave(&vector_lock, flags);
	184	__clear_irq_vector(irq);
e1b30a39 YI	185	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	186	}
1da177e4 LT	187
1da177e4 LT	188	int
85cbc503	189	ia64_native_assign_irq_vector (int irq)
1da177e4	190	{
e1b30a39	191	unsigned long flags;
4994be1b	192	int vector, cpu;
373167e8	193	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	194
4994be1b YI	195	vector = -ENOSPC;
e1b30a39	196
4994be1b	197	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	198	for_each_online_cpu(cpu) {
	199	domain = vector_allocation_domain(cpu);
	200	vector = find_unassigned_vector(domain);
	201	if (vector >= 0)
	202	break;
	203	}
e1b30a39 YI	204	if (vector < 0)
e1b30a39 YI	205	goto out;
8f5ad1a8 YI	206	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	207	irq = vector;
4994be1b	208	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	209	out:
4994be1b	210	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	211	return vector;
	212	}
	213
	214	void
85cbc503	215	ia64_native_free_irq_vector (int vector)
1da177e4	216	{
e1b30a39 YI	217	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	218	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	219	return;
e1b30a39	220	clear_irq_vector(vector);
1da177e4 LT	221	}
1da177e4 LT	222
10083072 MM	223	int
	224	reserve_irq_vector (int vector)
	225	{
10083072 MM	226	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	227	vector > IA64_LAST_DEVICE_VECTOR)
	228	return -EINVAL;
4994be1b	229	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	230	}
10083072	231
e1b30a39 YI	232	/*
	233	* Initialize vector_irq on a new cpu. This function must be called
	234	* with vector_lock held.
	235	*/
	236	void __setup_vector_irq(int cpu)
	237	{
	238	int irq, vector;
	239
	240	/* Clear vector_irq */
	241	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	242	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	243	/* Mark the inuse vectors */
e1b30a39 YI	244	for (irq = 0; irq < NR_IRQS; ++irq) {
5d2068da	245	if (!cpumask_test_cpu(cpu, &irq_cfg[irq].domain))
4994be1b YI	246	continue;
	247	vector = irq_to_vector(irq);
	248	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	249	}
	250	}
	251
e5bd762b	252	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
a6cd6322	253
d080d397 YI	254	static enum vector_domain_type {
	255	VECTOR_DOMAIN_NONE,
	256	VECTOR_DOMAIN_PERCPU
	257	} vector_domain_type = VECTOR_DOMAIN_NONE;
	258
4994be1b YI	259	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	260	{
d080d397	261	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
6a4bd8d1	262	return *cpumask_of(cpu);
4994be1b YI	263	return CPU_MASK_ALL;
	264	}
	265
a6cd6322 KK	266	static int __irq_prepare_move(int irq, int cpu)
	267	{
	268	struct irq_cfg *cfg = &irq_cfg[irq];
	269	int vector;
	270	cpumask_t domain;
	271
	272	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	273	return -EBUSY;
	274	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	275	return -EINVAL;
5d2068da	276	if (cpumask_test_cpu(cpu, &cfg->domain))
a6cd6322 KK	277	return 0;
	278	domain = vector_allocation_domain(cpu);
	279	vector = find_unassigned_vector(domain);
	280	if (vector < 0)
	281	return -ENOSPC;
	282	cfg->move_in_progress = 1;
	283	cfg->old_domain = cfg->domain;
	284	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	285	cfg->domain = CPU_MASK_NONE;
	286	BUG_ON(__bind_irq_vector(irq, vector, domain));
	287	return 0;
	288	}
	289
	290	int irq_prepare_move(int irq, int cpu)
	291	{
	292	unsigned long flags;
	293	int ret;
	294
	295	spin_lock_irqsave(&vector_lock, flags);
	296	ret = __irq_prepare_move(irq, cpu);
	297	spin_unlock_irqrestore(&vector_lock, flags);
	298	return ret;
	299	}
	300
	301	void irq_complete_move(unsigned irq)
	302	{
	303	struct irq_cfg *cfg = &irq_cfg[irq];
	304	cpumask_t cleanup_mask;
	305	int i;
	306
	307	if (likely(!cfg->move_in_progress))
	308	return;
	309
5d2068da	310	if (unlikely(cpumask_test_cpu(smp_processor_id(), &cfg->old_domain)))
a6cd6322 KK	311	return;
a6cd6322 KK	312
7d7f9848	313	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
5d2068da RR	314	cfg->move_cleanup_count = cpumask_weight(&cleanup_mask);
5d2068da RR	315	for_each_cpu(i, &cleanup_mask)
a6cd6322 KK	316	platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	317	cfg->move_in_progress = 0;
	318	}
	319
	320	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	321	{
	322	int me = smp_processor_id();
	323	ia64_vector vector;
	324	unsigned long flags;
	325
	326	for (vector = IA64_FIRST_DEVICE_VECTOR;
	327	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	328	int irq;
	329	struct irq_desc *desc;
	330	struct irq_cfg *cfg;
6065a244	331	irq = __this_cpu_read(vector_irq[vector]);
a6cd6322 KK	332	if (irq < 0)
	333	continue;
	334
a2178334	335	desc = irq_to_desc(irq);
a6cd6322	336	cfg = irq_cfg + irq;
239007b8	337	raw_spin_lock(&desc->lock);
a6cd6322 KK	338	if (!cfg->move_cleanup_count)
	339	goto unlock;
	340
5d2068da	341	if (!cpumask_test_cpu(me, &cfg->old_domain))
a6cd6322 KK	342	goto unlock;
	343
	344	spin_lock_irqsave(&vector_lock, flags);
6065a244	345	__this_cpu_write(vector_irq[vector], -1);
5d2068da	346	cpumask_clear_cpu(me, &vector_table[vector]);
a6cd6322 KK	347	spin_unlock_irqrestore(&vector_lock, flags);
	348	cfg->move_cleanup_count--;
	349	unlock:
239007b8	350	raw_spin_unlock(&desc->lock);
a6cd6322 KK	351	}
	352	return IRQ_HANDLED;
	353	}
	354
	355	static struct irqaction irq_move_irqaction = {
	356	.handler = smp_irq_move_cleanup_interrupt,
a6cd6322 KK	357	.name = "irq_move"
	358	};
	359
d080d397 YI	360	static int __init parse_vector_domain(char *arg)
	361	{
	362	if (!arg)
	363	return -EINVAL;
	364	if (!strcmp(arg, "percpu")) {
	365	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	366	no_int_routing = 1;
	367	}
074ff856	368	return 0;
d080d397 YI	369	}
	370	early_param("vector", parse_vector_domain);
	371	#else
	372	static cpumask_t vector_allocation_domain(int cpu)
	373	{
	374	return CPU_MASK_ALL;
	375	}
	376	#endif
	377
4994be1b	378
e1b30a39 YI	379	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	380	{
216fcd29 KK	381	unsigned long flags;
216fcd29 KK	382
4debd723	383	irq_init_desc(irq);
216fcd29 KK	384	spin_lock_irqsave(&vector_lock, flags);
	385	__clear_irq_vector(irq);
	386	irq_status[irq] = IRQ_RSVD;
	387	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	388	}
10083072 MM	389
b6cf2583 EB	390	/*
	391	* Dynamic irq allocate and deallocation for MSI
	392	*/
	393	int create_irq(void)
	394	{
e1b30a39	395	unsigned long flags;
4994be1b	396	int irq, vector, cpu;
373167e8	397	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	398
4994be1b	399	irq = vector = -ENOSPC;
e1b30a39	400	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	401	for_each_online_cpu(cpu) {
	402	domain = vector_allocation_domain(cpu);
	403	vector = find_unassigned_vector(domain);
	404	if (vector >= 0)
	405	break;
	406	}
e1b30a39 YI	407	if (vector < 0)
	408	goto out;
	409	irq = find_unassigned_irq();
	410	if (irq < 0)
	411	goto out;
4994be1b	412	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	413	out:
	414	spin_unlock_irqrestore(&vector_lock, flags);
	415	if (irq >= 0)
4debd723	416	irq_init_desc(irq);
e1b30a39	417	return irq;
b6cf2583 EB	418	}
	419
	420	void destroy_irq(unsigned int irq)
	421	{
4debd723	422	irq_init_desc(irq);
e1b30a39	423	clear_irq_vector(irq);
b6cf2583 EB	424	}
b6cf2583 EB	425
1da177e4 LT	426	#ifdef CONFIG_SMP
1da177e4 LT	427	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	428	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	429	#else
1da177e4 LT	430	# define IS_RESCHEDULE(vec) (0)
3be44b9c	431	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	432	#endif
	433	/*
	434	* That's where the IVT branches when we get an external
	435	* interrupt. This branches to the correct hardware IRQ handler via
	436	* function ptr.
	437	*/
	438	void
	439	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	440	{
7d12e780	441	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	442	unsigned long saved_tpr;
	443
	444	#if IRQ_DEBUG
	445	{
	446	unsigned long bsp, sp;
	447
	448	/*
	449	* Note: if the interrupt happened while executing in
	450	* the context switch routine (ia64_switch_to), we may
	451	* get a spurious stack overflow here. This is
	452	* because the register and the memory stack are not
	453	* switched atomically.
	454	*/
	455	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	456	sp = ia64_getreg(_IA64_REG_SP);
	457
	458	if ((sp - bsp) < 1024) {
7683a3f9	459	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
1da177e4	460
7683a3f9	461	if (__ratelimit(&ratelimit)) {
1da177e4 LT	462	printk("ia64_handle_irq: DANGER: less than "
	463	"1KB of free stack space!!\n"
	464	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	465	}
	466	}
	467	}
	468	#endif /* IRQ_DEBUG */
	469
	470	/*
	471	* Always set TPR to limit maximum interrupt nesting depth to
	472	* 16 (without this, it would be ~240, which could easily lead
	473	* to kernel stack overflows).
	474	*/
	475	irq_enter();
	476	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	477	ia64_srlz_d();
	478	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af JS	479	int irq = local_vector_to_irq(vector);
66f3e6af JS	480
3be44b9c JS	481	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	482	smp_local_flush_tlb();
3611587a	483	kstat_incr_irq_this_cpu(irq);
7c730ccd	484	} else if (unlikely(IS_RESCHEDULE(vector))) {
184748cc	485	scheduler_ipi();
3611587a	486	kstat_incr_irq_this_cpu(irq);
7c730ccd	487	} else {
1da177e4 LT	488	ia64_setreg(_IA64_REG_CR_TPR, vector);
	489	ia64_srlz_d();
	490
17764d24 KK	491	if (unlikely(irq < 0)) {
	492	printk(KERN_ERR "%s: Unexpected interrupt "
	493	"vector %d on CPU %d is not mapped "
d4ed8084	494	"to any IRQ!\n", __func__, vector,
17764d24 KK	495	smp_processor_id());
	496	} else
	497	generic_handle_irq(irq);
1da177e4 LT	498
	499	/*
	500	* Disable interrupts and send EOI:
	501	*/
	502	local_irq_disable();
	503	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	504	}
	505	ia64_eoi();
	506	vector = ia64_get_ivr();
	507	}
	508	/*
	509	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	510	* handler needs to be able to wait for further keyboard interrupts, which can't
	511	* come through until ia64_eoi() has been done.
	512	*/
	513	irq_exit();
7d12e780	514	set_irq_regs(old_regs);
1da177e4 LT	515	}
	516
	517	#ifdef CONFIG_HOTPLUG_CPU
	518	/*
	519	* This function emulates a interrupt processing when a cpu is about to be
	520	* brought down.
	521	*/
	522	void ia64_process_pending_intr(void)
	523	{
	524	ia64_vector vector;
	525	unsigned long saved_tpr;
	526	extern unsigned int vectors_in_migration[NR_IRQS];
	527
	528	vector = ia64_get_ivr();
	529
66f3e6af JS	530	irq_enter();
	531	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	532	ia64_srlz_d();
1da177e4 LT	533
	534	/*
	535	* Perform normal interrupt style processing
	536	*/
	537	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	538	int irq = local_vector_to_irq(vector);
66f3e6af	539
3be44b9c JS	540	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	541	smp_local_flush_tlb();
3611587a	542	kstat_incr_irq_this_cpu(irq);
7c730ccd	543	} else if (unlikely(IS_RESCHEDULE(vector))) {
3611587a	544	kstat_incr_irq_this_cpu(irq);
7c730ccd	545	} else {
8c1addbc TL	546	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	547
1da177e4 LT	548	ia64_setreg(_IA64_REG_CR_TPR, vector);
	549	ia64_srlz_d();
	550
	551	/*
	552	* Now try calling normal ia64_handle_irq as it would have got called
	553	* from a real intr handler. Try passing null for pt_regs, hopefully
	554	* it will work. I hope it works!.
	555	* Probably could shared code.
	556	*/
17764d24 KK	557	if (unlikely(irq < 0)) {
	558	printk(KERN_ERR "%s: Unexpected interrupt "
	559	"vector %d on CPU %d not being mapped "
d4ed8084	560	"to any IRQ!!\n", __func__, vector,
17764d24 KK	561	smp_processor_id());
	562	} else {
	563	vectors_in_migration[irq]=0;
	564	generic_handle_irq(irq);
	565	}
8c1addbc	566	set_irq_regs(old_regs);
1da177e4 LT	567
	568	/*
	569	* Disable interrupts and send EOI
	570	*/
	571	local_irq_disable();
	572	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	573	}
	574	ia64_eoi();
	575	vector = ia64_get_ivr();
	576	}
	577	irq_exit();
	578	}
	579	#endif
	580
	581
	582	#ifdef CONFIG_SMP
1da177e4	583
9b3377f9 JS	584	static irqreturn_t dummy_handler (int irq, void *dev_id)
	585	{
	586	BUG();
	587	}
	588
1da177e4 LT	589	static struct irqaction ipi_irqaction = {
1da177e4 LT	590	.handler = handle_IPI,
1da177e4 LT	591	.name = "IPI"
1da177e4 LT	592	};
9b3377f9	593
32f88400 MT	594	/*
	595	* KVM uses this interrupt to force a cpu out of guest mode
	596	*/
9b3377f9 JS	597	static struct irqaction resched_irqaction = {
9b3377f9 JS	598	.handler = dummy_handler,
9b3377f9 JS	599	.name = "resched"
9b3377f9 JS	600	};
3be44b9c JS	601
	602	static struct irqaction tlb_irqaction = {
	603	.handler = dummy_handler,
3be44b9c JS	604	.name = "tlb_flush"
	605	};
	606
1da177e4 LT	607	#endif
	608
	609	void
85cbc503	610	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4	611	{
1da177e4 LT	612	unsigned int irq;
1da177e4 LT	613
e1b30a39	614	irq = vec;
4994be1b	615	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
a2178334	616	irq_set_status_flags(irq, IRQ_PER_CPU);
53c909c9	617	irq_set_chip(irq, &irq_type_ia64_lsapic);
e1b30a39 YI	618	if (action)
e1b30a39 YI	619	setup_irq(irq, action);
53c909c9	620	irq_set_handler(irq, handle_percpu_irq);
1da177e4 LT	621	}
	622
	623	void __init
85cbc503	624	ia64_native_register_ipi(void)
1da177e4	625	{
1da177e4 LT	626	#ifdef CONFIG_SMP
1da177e4 LT	627	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	628	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	629	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	630	#endif
	631	}
	632
	633	void __init
	634	init_IRQ (void)
	635	{
4de0a759 TL	636	#ifdef CONFIG_ACPI
	637	acpi_boot_init();
	638	#endif
85cbc503 IY	639	ia64_register_ipi();
	640	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	641	#ifdef CONFIG_SMP
a6cd6322	642	#if defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG)
09b366b7	643	if (vector_domain_type != VECTOR_DOMAIN_NONE)
a6cd6322	644	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
a6cd6322	645	#endif
1da177e4 LT	646	#endif
	647	#ifdef CONFIG_PERFMON
	648	pfm_init_percpu();
	649	#endif
	650	platform_irq_init();
	651	}
	652
	653	void
	654	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	655	{
	656	void __iomem *ipi_addr;
	657	unsigned long ipi_data;
	658	unsigned long phys_cpu_id;
	659
1da177e4	660	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	661
	662	/*
	663	* cpu number is in 8bit ID and 8bit EID
	664	*/
	665
	666	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	667	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	668
	669	writeq(ipi_data, ipi_addr);
	670	}