[deliverable/linux.git] / arch / ia64 / kernel / msi_ia64.c

/*
 * MSI hooks for standard x86 apic
 */

#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/msi.h>
#include <asm/smp.h>

/*
 * Shifts for APIC-based data
 */

#define MSI_DATA_VECTOR_SHIFT		0
#define	    MSI_DATA_VECTOR(v)		(((u8)v) << MSI_DATA_VECTOR_SHIFT)
#define MSI_DATA_VECTOR_MASK		0xffffff00

#define MSI_DATA_DELIVERY_SHIFT		8
#define     MSI_DATA_DELIVERY_FIXED	(0 << MSI_DATA_DELIVERY_SHIFT)
#define     MSI_DATA_DELIVERY_LOWPRI	(1 << MSI_DATA_DELIVERY_SHIFT)

#define MSI_DATA_LEVEL_SHIFT		14
#define     MSI_DATA_LEVEL_DEASSERT	(0 << MSI_DATA_LEVEL_SHIFT)
#define     MSI_DATA_LEVEL_ASSERT	(1 << MSI_DATA_LEVEL_SHIFT)

#define MSI_DATA_TRIGGER_SHIFT		15
#define     MSI_DATA_TRIGGER_EDGE	(0 << MSI_DATA_TRIGGER_SHIFT)
#define     MSI_DATA_TRIGGER_LEVEL	(1 << MSI_DATA_TRIGGER_SHIFT)

/*
 * Shift/mask fields for APIC-based bus address
 */

#define MSI_TARGET_CPU_SHIFT		4
#define MSI_ADDR_HEADER			0xfee00000

#define MSI_ADDR_DESTID_MASK		0xfff0000f
#define     MSI_ADDR_DESTID_CPU(cpu)	((cpu) << MSI_TARGET_CPU_SHIFT)

#define MSI_ADDR_DESTMODE_SHIFT		2
#define     MSI_ADDR_DESTMODE_PHYS	(0 << MSI_ADDR_DESTMODE_SHIFT)
#define	    MSI_ADDR_DESTMODE_LOGIC	(1 << MSI_ADDR_DESTMODE_SHIFT)

#define MSI_ADDR_REDIRECTION_SHIFT	3
#define     MSI_ADDR_REDIRECTION_CPU	(0 << MSI_ADDR_REDIRECTION_SHIFT)
#define     MSI_ADDR_REDIRECTION_LOWPRI	(1 << MSI_ADDR_REDIRECTION_SHIFT)

static struct irq_chip	ia64_msi_chip;

#ifdef CONFIG_SMP
static void ia64_set_msi_irq_affinity(unsigned int irq, cpumask_t cpu_mask)
{
	struct msi_msg msg;
	u32 addr, data;
	int cpu = first_cpu(cpu_mask);

	if (!cpu_online(cpu))
		return;

	if (irq_prepare_move(irq, cpu))
		return;

	read_msi_msg(irq, &msg);

	addr = msg.address_lo;
	addr &= MSI_ADDR_DESTID_MASK;
	addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(cpu));
	msg.address_lo = addr;

	data = msg.data;
	data &= MSI_DATA_VECTOR_MASK;
	data |= MSI_DATA_VECTOR(irq_to_vector(irq));
	msg.data = data;

	write_msi_msg(irq, &msg);
	irq_desc[irq].affinity = cpumask_of_cpu(cpu);
}
#endif /* CONFIG_SMP */

int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
	struct msi_msg	msg;
	unsigned long	dest_phys_id;
	int	irq, vector;
	cpumask_t mask;

	irq = create_irq();
	if (irq < 0)
		return irq;

	set_irq_msi(irq, desc);
	cpus_and(mask, irq_to_domain(irq), cpu_online_map);
	dest_phys_id = cpu_physical_id(first_cpu(mask));
	vector = irq_to_vector(irq);

	msg.address_hi = 0;
	msg.address_lo =
		MSI_ADDR_HEADER |
		MSI_ADDR_DESTMODE_PHYS |
		MSI_ADDR_REDIRECTION_CPU |
		MSI_ADDR_DESTID_CPU(dest_phys_id);

	msg.data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		MSI_DATA_DELIVERY_FIXED |
		MSI_DATA_VECTOR(vector);

	write_msi_msg(irq, &msg);
	set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);

	return 0;
}

void ia64_teardown_msi_irq(unsigned int irq)
{
	destroy_irq(irq);
}

static void ia64_ack_msi_irq(unsigned int irq)
{
	irq_complete_move(irq);
	move_native_irq(irq);
	ia64_eoi();
}

static int ia64_msi_retrigger_irq(unsigned int irq)
{
	unsigned int vector = irq_to_vector(irq);
	ia64_resend_irq(vector);

	return 1;
}

/*
 * Generic ops used on most IA64 platforms.
 */
static struct irq_chip ia64_msi_chip = {
	.name		= "PCI-MSI",
	.mask		= mask_msi_irq,
	.unmask		= unmask_msi_irq,
	.ack		= ia64_ack_msi_irq,
#ifdef CONFIG_SMP
	.set_affinity	= ia64_set_msi_irq_affinity,
#endif
	.retrigger	= ia64_msi_retrigger_irq,
};


int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
	if (platform_setup_msi_irq)
		return platform_setup_msi_irq(pdev, desc);

	return ia64_setup_msi_irq(pdev, desc);
}

void arch_teardown_msi_irq(unsigned int irq)
{
	if (platform_teardown_msi_irq)
		return platform_teardown_msi_irq(irq);

	return ia64_teardown_msi_irq(irq);
}
Commit	Line	Data
fd58e55f MM	1	/*
	2	* MSI hooks for standard x86 apic
	3	*/
	4
	5	#include <linux/pci.h>
	6	#include <linux/irq.h>
3b7d1921	7	#include <linux/msi.h>
a4cffb64	8	#include <asm/smp.h>
fd58e55f	9
fd58e55f MM	10	/*
	11	* Shifts for APIC-based data
	12	*/
	13
	14	#define MSI_DATA_VECTOR_SHIFT 0
	15	#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
cd378f18	16	#define MSI_DATA_VECTOR_MASK 0xffffff00
fd58e55f MM	17
	18	#define MSI_DATA_DELIVERY_SHIFT 8
	19	#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT)
	20	#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT)
	21
	22	#define MSI_DATA_LEVEL_SHIFT 14
	23	#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
	24	#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
	25
	26	#define MSI_DATA_TRIGGER_SHIFT 15
	27	#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
	28	#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
	29
	30	/*
	31	* Shift/mask fields for APIC-based bus address
	32	*/
	33
3b7d1921	34	#define MSI_TARGET_CPU_SHIFT 4
fd58e55f MM	35	#define MSI_ADDR_HEADER 0xfee00000
	36
	37	#define MSI_ADDR_DESTID_MASK 0xfff0000f
	38	#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT)
	39
	40	#define MSI_ADDR_DESTMODE_SHIFT 2
	41	#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
	42	#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
	43
	44	#define MSI_ADDR_REDIRECTION_SHIFT 3
	45	#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
	46	#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
	47
3b7d1921	48	static struct irq_chip ia64_msi_chip;
fd58e55f	49
3b7d1921 EB	50	#ifdef CONFIG_SMP
3b7d1921 EB	51	static void ia64_set_msi_irq_affinity(unsigned int irq, cpumask_t cpu_mask)
fd58e55f	52	{
3b7d1921	53	struct msi_msg msg;
cd378f18 YI	54	u32 addr, data;
cd378f18 YI	55	int cpu = first_cpu(cpu_mask);
3b7d1921	56
cd378f18 YI	57	if (!cpu_online(cpu))
	58	return;
	59
a6cd6322	60	if (irq_prepare_move(irq, cpu))
4994be1b YI	61	return;
4994be1b YI	62
3b7d1921	63	read_msi_msg(irq, &msg);
fd58e55f	64
3b7d1921	65	addr = msg.address_lo;
fd58e55f	66	addr &= MSI_ADDR_DESTID_MASK;
cd378f18	67	addr \|= MSI_ADDR_DESTID_CPU(cpu_physical_id(cpu));
3b7d1921	68	msg.address_lo = addr;
fd58e55f	69
cd378f18 YI	70	data = msg.data;
	71	data &= MSI_DATA_VECTOR_MASK;
	72	data \|= MSI_DATA_VECTOR(irq_to_vector(irq));
	73	msg.data = data;
	74
3b7d1921	75	write_msi_msg(irq, &msg);
cd378f18	76	irq_desc[irq].affinity = cpumask_of_cpu(cpu);
fd58e55f	77	}
3b7d1921	78	#endif /* CONFIG_SMP */
fd58e55f	79
f7feaca7	80	int ia64_setup_msi_irq(struct pci_dev pdev, struct msi_desc desc)
fd58e55f	81	{
3b7d1921	82	struct msi_msg msg;
fd58e55f	83	unsigned long dest_phys_id;
8a3a0ee7	84	int irq, vector;
4994be1b	85	cpumask_t mask;
fd58e55f	86
f7feaca7 EB	87	irq = create_irq();
	88	if (irq < 0)
	89	return irq;
	90
	91	set_irq_msi(irq, desc);
4994be1b YI	92	cpus_and(mask, irq_to_domain(irq), cpu_online_map);
4994be1b YI	93	dest_phys_id = cpu_physical_id(first_cpu(mask));
9438a121	94	vector = irq_to_vector(irq);
fd58e55f	95
3b7d1921 EB	96	msg.address_hi = 0;
3b7d1921 EB	97	msg.address_lo =
38bc0361 EB	98	MSI_ADDR_HEADER \|
	99	MSI_ADDR_DESTMODE_PHYS \|
	100	MSI_ADDR_REDIRECTION_CPU \|
	101	MSI_ADDR_DESTID_CPU(dest_phys_id);
fd58e55f	102
3b7d1921	103	msg.data =
38bc0361	104	MSI_DATA_TRIGGER_EDGE \|
fd58e55f MM	105	MSI_DATA_LEVEL_ASSERT \|
	106	MSI_DATA_DELIVERY_FIXED \|
	107	MSI_DATA_VECTOR(vector);
	108
3b7d1921 EB	109	write_msi_msg(irq, &msg);
	110	set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
	111
3aff0373	112	return 0;
fd58e55f MM	113	}
fd58e55f MM	114
3b7d1921	115	void ia64_teardown_msi_irq(unsigned int irq)
fd58e55f	116	{
f7feaca7	117	destroy_irq(irq);
fd58e55f MM	118	}
fd58e55f MM	119
3b7d1921 EB	120	static void ia64_ack_msi_irq(unsigned int irq)
3b7d1921 EB	121	{
a6cd6322	122	irq_complete_move(irq);
3b7d1921 EB	123	move_native_irq(irq);
	124	ia64_eoi();
	125	}
	126
	127	static int ia64_msi_retrigger_irq(unsigned int irq)
	128	{
9438a121	129	unsigned int vector = irq_to_vector(irq);
3b7d1921 EB	130	ia64_resend_irq(vector);
	131
	132	return 1;
	133	}
	134
fd58e55f	135	/*
3b7d1921	136	* Generic ops used on most IA64 platforms.
fd58e55f	137	*/
3b7d1921 EB	138	static struct irq_chip ia64_msi_chip = {
	139	.name = "PCI-MSI",
	140	.mask = mask_msi_irq,
	141	.unmask = unmask_msi_irq,
	142	.ack = ia64_ack_msi_irq,
	143	#ifdef CONFIG_SMP
	144	.set_affinity = ia64_set_msi_irq_affinity,
	145	#endif
	146	.retrigger = ia64_msi_retrigger_irq,
fd58e55f	147	};
3b7d1921 EB	148
3b7d1921 EB	149
f7feaca7	150	int arch_setup_msi_irq(struct pci_dev pdev, struct msi_desc desc)
3b7d1921 EB	151	{
3b7d1921 EB	152	if (platform_setup_msi_irq)
f7feaca7	153	return platform_setup_msi_irq(pdev, desc);
3b7d1921	154
f7feaca7	155	return ia64_setup_msi_irq(pdev, desc);
3b7d1921 EB	156	}
	157
	158	void arch_teardown_msi_irq(unsigned int irq)
	159	{
	160	if (platform_teardown_msi_irq)
	161	return platform_teardown_msi_irq(irq);
	162
	163	return ia64_teardown_msi_irq(irq);
	164	}