Commit | Line | Data |
---|---|---|
fd58e55f MM |
1 | /* |
2 | * MSI hooks for standard x86 apic | |
3 | */ | |
4 | ||
5 | #include <linux/pci.h> | |
6 | #include <linux/irq.h> | |
3b7d1921 | 7 | #include <linux/msi.h> |
62fdd767 | 8 | #include <linux/dmar.h> |
a4cffb64 | 9 | #include <asm/smp.h> |
fd58e55f | 10 | |
fd58e55f MM |
11 | /* |
12 | * Shifts for APIC-based data | |
13 | */ | |
14 | ||
15 | #define MSI_DATA_VECTOR_SHIFT 0 | |
16 | #define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT) | |
cd378f18 | 17 | #define MSI_DATA_VECTOR_MASK 0xffffff00 |
fd58e55f MM |
18 | |
19 | #define MSI_DATA_DELIVERY_SHIFT 8 | |
20 | #define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT) | |
21 | #define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT) | |
22 | ||
23 | #define MSI_DATA_LEVEL_SHIFT 14 | |
24 | #define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) | |
25 | #define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) | |
26 | ||
27 | #define MSI_DATA_TRIGGER_SHIFT 15 | |
28 | #define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) | |
29 | #define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) | |
30 | ||
31 | /* | |
32 | * Shift/mask fields for APIC-based bus address | |
33 | */ | |
34 | ||
3b7d1921 | 35 | #define MSI_TARGET_CPU_SHIFT 4 |
fd58e55f MM |
36 | #define MSI_ADDR_HEADER 0xfee00000 |
37 | ||
38 | #define MSI_ADDR_DESTID_MASK 0xfff0000f | |
39 | #define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT) | |
40 | ||
41 | #define MSI_ADDR_DESTMODE_SHIFT 2 | |
42 | #define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT) | |
43 | #define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT) | |
44 | ||
45 | #define MSI_ADDR_REDIRECTION_SHIFT 3 | |
46 | #define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) | |
47 | #define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) | |
48 | ||
3b7d1921 | 49 | static struct irq_chip ia64_msi_chip; |
fd58e55f | 50 | |
3b7d1921 | 51 | #ifdef CONFIG_SMP |
0de26520 RR |
52 | static void ia64_set_msi_irq_affinity(unsigned int irq, |
53 | const cpumask_t *cpu_mask) | |
fd58e55f | 54 | { |
3b7d1921 | 55 | struct msi_msg msg; |
cd378f18 | 56 | u32 addr, data; |
0de26520 | 57 | int cpu = first_cpu(*cpu_mask); |
3b7d1921 | 58 | |
cd378f18 YI |
59 | if (!cpu_online(cpu)) |
60 | return; | |
61 | ||
a6cd6322 | 62 | if (irq_prepare_move(irq, cpu)) |
4994be1b YI |
63 | return; |
64 | ||
3b7d1921 | 65 | read_msi_msg(irq, &msg); |
fd58e55f | 66 | |
3b7d1921 | 67 | addr = msg.address_lo; |
fd58e55f | 68 | addr &= MSI_ADDR_DESTID_MASK; |
cd378f18 | 69 | addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(cpu)); |
3b7d1921 | 70 | msg.address_lo = addr; |
fd58e55f | 71 | |
cd378f18 YI |
72 | data = msg.data; |
73 | data &= MSI_DATA_VECTOR_MASK; | |
74 | data |= MSI_DATA_VECTOR(irq_to_vector(irq)); | |
75 | msg.data = data; | |
76 | ||
3b7d1921 | 77 | write_msi_msg(irq, &msg); |
e65e49d0 | 78 | cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); |
fd58e55f | 79 | } |
3b7d1921 | 80 | #endif /* CONFIG_SMP */ |
fd58e55f | 81 | |
f7feaca7 | 82 | int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
fd58e55f | 83 | { |
3b7d1921 | 84 | struct msi_msg msg; |
fd58e55f | 85 | unsigned long dest_phys_id; |
8a3a0ee7 | 86 | int irq, vector; |
4994be1b | 87 | cpumask_t mask; |
fd58e55f | 88 | |
f7feaca7 EB |
89 | irq = create_irq(); |
90 | if (irq < 0) | |
91 | return irq; | |
92 | ||
93 | set_irq_msi(irq, desc); | |
4994be1b YI |
94 | cpus_and(mask, irq_to_domain(irq), cpu_online_map); |
95 | dest_phys_id = cpu_physical_id(first_cpu(mask)); | |
9438a121 | 96 | vector = irq_to_vector(irq); |
fd58e55f | 97 | |
3b7d1921 EB |
98 | msg.address_hi = 0; |
99 | msg.address_lo = | |
38bc0361 EB |
100 | MSI_ADDR_HEADER | |
101 | MSI_ADDR_DESTMODE_PHYS | | |
102 | MSI_ADDR_REDIRECTION_CPU | | |
103 | MSI_ADDR_DESTID_CPU(dest_phys_id); | |
fd58e55f | 104 | |
3b7d1921 | 105 | msg.data = |
38bc0361 | 106 | MSI_DATA_TRIGGER_EDGE | |
fd58e55f MM |
107 | MSI_DATA_LEVEL_ASSERT | |
108 | MSI_DATA_DELIVERY_FIXED | | |
109 | MSI_DATA_VECTOR(vector); | |
110 | ||
3b7d1921 EB |
111 | write_msi_msg(irq, &msg); |
112 | set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); | |
113 | ||
3aff0373 | 114 | return 0; |
fd58e55f MM |
115 | } |
116 | ||
3b7d1921 | 117 | void ia64_teardown_msi_irq(unsigned int irq) |
fd58e55f | 118 | { |
f7feaca7 | 119 | destroy_irq(irq); |
fd58e55f MM |
120 | } |
121 | ||
3b7d1921 EB |
122 | static void ia64_ack_msi_irq(unsigned int irq) |
123 | { | |
a6cd6322 | 124 | irq_complete_move(irq); |
3b7d1921 EB |
125 | move_native_irq(irq); |
126 | ia64_eoi(); | |
127 | } | |
128 | ||
129 | static int ia64_msi_retrigger_irq(unsigned int irq) | |
130 | { | |
9438a121 | 131 | unsigned int vector = irq_to_vector(irq); |
3b7d1921 EB |
132 | ia64_resend_irq(vector); |
133 | ||
134 | return 1; | |
135 | } | |
136 | ||
fd58e55f | 137 | /* |
3b7d1921 | 138 | * Generic ops used on most IA64 platforms. |
fd58e55f | 139 | */ |
3b7d1921 EB |
140 | static struct irq_chip ia64_msi_chip = { |
141 | .name = "PCI-MSI", | |
142 | .mask = mask_msi_irq, | |
143 | .unmask = unmask_msi_irq, | |
144 | .ack = ia64_ack_msi_irq, | |
145 | #ifdef CONFIG_SMP | |
146 | .set_affinity = ia64_set_msi_irq_affinity, | |
147 | #endif | |
148 | .retrigger = ia64_msi_retrigger_irq, | |
fd58e55f | 149 | }; |
3b7d1921 EB |
150 | |
151 | ||
f7feaca7 | 152 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
3b7d1921 EB |
153 | { |
154 | if (platform_setup_msi_irq) | |
f7feaca7 | 155 | return platform_setup_msi_irq(pdev, desc); |
3b7d1921 | 156 | |
f7feaca7 | 157 | return ia64_setup_msi_irq(pdev, desc); |
3b7d1921 EB |
158 | } |
159 | ||
160 | void arch_teardown_msi_irq(unsigned int irq) | |
161 | { | |
162 | if (platform_teardown_msi_irq) | |
163 | return platform_teardown_msi_irq(irq); | |
164 | ||
165 | return ia64_teardown_msi_irq(irq); | |
166 | } | |
62fdd767 FY |
167 | |
168 | #ifdef CONFIG_DMAR | |
169 | #ifdef CONFIG_SMP | |
0de26520 | 170 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
62fdd767 FY |
171 | { |
172 | struct irq_cfg *cfg = irq_cfg + irq; | |
173 | struct msi_msg msg; | |
0de26520 | 174 | int cpu = cpumask_first(mask); |
62fdd767 FY |
175 | |
176 | if (!cpu_online(cpu)) | |
177 | return; | |
178 | ||
179 | if (irq_prepare_move(irq, cpu)) | |
180 | return; | |
181 | ||
182 | dmar_msi_read(irq, &msg); | |
183 | ||
184 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
185 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
186 | msg.address_lo &= ~MSI_ADDR_DESTID_MASK; | |
187 | msg.address_lo |= MSI_ADDR_DESTID_CPU(cpu_physical_id(cpu)); | |
188 | ||
189 | dmar_msi_write(irq, &msg); | |
e65e49d0 | 190 | cpumask_copy(irq_desc[irq].affinity, mask); |
62fdd767 FY |
191 | } |
192 | #endif /* CONFIG_SMP */ | |
193 | ||
194 | struct irq_chip dmar_msi_type = { | |
195 | .name = "DMAR_MSI", | |
196 | .unmask = dmar_msi_unmask, | |
197 | .mask = dmar_msi_mask, | |
198 | .ack = ia64_ack_msi_irq, | |
199 | #ifdef CONFIG_SMP | |
200 | .set_affinity = dmar_msi_set_affinity, | |
201 | #endif | |
202 | .retrigger = ia64_msi_retrigger_irq, | |
203 | }; | |
204 | ||
205 | static int | |
206 | msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) | |
207 | { | |
208 | struct irq_cfg *cfg = irq_cfg + irq; | |
209 | unsigned dest; | |
210 | cpumask_t mask; | |
211 | ||
212 | cpus_and(mask, irq_to_domain(irq), cpu_online_map); | |
213 | dest = cpu_physical_id(first_cpu(mask)); | |
214 | ||
215 | msg->address_hi = 0; | |
216 | msg->address_lo = | |
217 | MSI_ADDR_HEADER | | |
218 | MSI_ADDR_DESTMODE_PHYS | | |
219 | MSI_ADDR_REDIRECTION_CPU | | |
220 | MSI_ADDR_DESTID_CPU(dest); | |
221 | ||
222 | msg->data = | |
223 | MSI_DATA_TRIGGER_EDGE | | |
224 | MSI_DATA_LEVEL_ASSERT | | |
225 | MSI_DATA_DELIVERY_FIXED | | |
226 | MSI_DATA_VECTOR(cfg->vector); | |
227 | return 0; | |
228 | } | |
229 | ||
230 | int arch_setup_dmar_msi(unsigned int irq) | |
231 | { | |
232 | int ret; | |
233 | struct msi_msg msg; | |
234 | ||
235 | ret = msi_compose_msg(NULL, irq, &msg); | |
236 | if (ret < 0) | |
237 | return ret; | |
238 | dmar_msi_write(irq, &msg); | |
239 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
240 | "edge"); | |
241 | return 0; | |
242 | } | |
243 | #endif /* CONFIG_DMAR */ | |
244 |