projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a4f50038 XZ |
1 | /* |
| 2 | * vti.h: prototype for generial vt related interface | |
| 3 | * Copyright (c) 2004, Intel Corporation. | |
| 4 | * | |
| 5 | * Xuefei Xu (Anthony Xu) (anthony.xu@intel.com) | |
| 6 | * Fred Yang (fred.yang@intel.com) | |
| 7 | * Kun Tian (Kevin Tian) (kevin.tian@intel.com) | |
| 8 | * | |
| 9 | * Copyright (c) 2007, Intel Corporation. | |
| 10 | * Zhang xiantao <xiantao.zhang@intel.com> | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify it | |
| 13 | * under the terms and conditions of the GNU General Public License, | |
| 14 | * version 2, as published by the Free Software Foundation. | |
| 15 | * | |
| 16 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 19 | * more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License along with | |
| 22 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
| 23 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
| 24 | */ | |
| 25 | #ifndef _KVM_VT_I_H | |
| 26 | #define _KVM_VT_I_H | |
| 27 | ||
| 28 | #ifndef __ASSEMBLY__ | |
| 29 | #include <asm/page.h> | |
| 30 | ||
| 31 | #include <linux/kvm_host.h> | |
| 32 | ||
| 33 | /* define itr.i and itr.d in ia64_itr function */ | |
| 34 | #define ITR 0x01 | |
| 35 | #define DTR 0x02 | |
| 36 | #define IaDTR 0x03 | |
| 37 | ||
| 38 | #define IA64_TR_VMM 6 /*itr6, dtr6 : maps vmm code, vmbuffer*/ | |
| 39 | #define IA64_TR_VM_DATA 7 /*dtr7 : maps current vm data*/ | |
| 40 | ||
| 41 | #define RR6 (6UL<<61) | |
| 42 | #define RR7 (7UL<<61) | |
| 43 | ||
| 44 | ||
| 45 | /* config_options in pal_vp_init_env */ | |
| 46 | #define VP_INITIALIZE 1UL | |
| 47 | #define VP_FR_PMC 1UL<<1 | |
| 48 | #define VP_OPCODE 1UL<<8 | |
| 49 | #define VP_CAUSE 1UL<<9 | |
| 50 | #define VP_FW_ACC 1UL<<63 | |
| 51 | ||
| 52 | /* init vp env with initializing vm_buffer */ | |
| 53 | #define VP_INIT_ENV_INITALIZE (VP_INITIALIZE | VP_FR_PMC |\ | |
| 54 | VP_OPCODE | VP_CAUSE | VP_FW_ACC) | |
| 55 | /* init vp env without initializing vm_buffer */ | |
| 56 | #define VP_INIT_ENV VP_FR_PMC | VP_OPCODE | VP_CAUSE | VP_FW_ACC | |
| 57 | ||
| 58 | #define PAL_VP_CREATE 265 | |
| 59 | /* Stacked Virt. Initializes a new VPD for the operation of | |
| 60 | * a new virtual processor in the virtual environment. | |
| 61 | */ | |
| 62 | #define PAL_VP_ENV_INFO 266 | |
| 63 | /*Stacked Virt. Returns the parameters needed to enter a virtual environment.*/ | |
| 64 | #define PAL_VP_EXIT_ENV 267 | |
| 65 | /*Stacked Virt. Allows a logical processor to exit a virtual environment.*/ | |
| 66 | #define PAL_VP_INIT_ENV 268 | |
| 67 | /*Stacked Virt. Allows a logical processor to enter a virtual environment.*/ | |
| 68 | #define PAL_VP_REGISTER 269 | |
| 69 | /*Stacked Virt. Register a different host IVT for the virtual processor.*/ | |
| 70 | #define PAL_VP_RESUME 270 | |
| 71 | /* Renamed from PAL_VP_RESUME */ | |
| 72 | #define PAL_VP_RESTORE 270 | |
| 73 | /*Stacked Virt. Resumes virtual processor operation on the logical processor.*/ | |
| 74 | #define PAL_VP_SUSPEND 271 | |
| 75 | /* Renamed from PAL_VP_SUSPEND */ | |
| 76 | #define PAL_VP_SAVE 271 | |
| 77 | /* Stacked Virt. Suspends operation for the specified virtual processor on | |
| 78 | * the logical processor. | |
| 79 | */ | |
| 80 | #define PAL_VP_TERMINATE 272 | |
| 81 | /* Stacked Virt. Terminates operation for the specified virtual processor.*/ | |
| 82 | ||
| 83 | union vac { | |
| 84 | unsigned long value; | |
| 85 | struct { | |
| 86 | int a_int:1; | |
| 87 | int a_from_int_cr:1; | |
| 88 | int a_to_int_cr:1; | |
| 89 | int a_from_psr:1; | |
| 90 | int a_from_cpuid:1; | |
| 91 | int a_cover:1; | |
| 92 | int a_bsw:1; | |
| 93 | long reserved:57; | |
| 94 | }; | |
| 95 | }; | |
| 96 | ||
| 97 | union vdc { | |
| 98 | unsigned long value; | |
| 99 | struct { | |
| 100 | int d_vmsw:1; | |
| 101 | int d_extint:1; | |
| 102 | int d_ibr_dbr:1; | |
| 103 | int d_pmc:1; | |
| 104 | int d_to_pmd:1; | |
| 105 | int d_itm:1; | |
| 106 | long reserved:58; | |
| 107 | }; | |
| 108 | }; | |
| 109 | ||
| 110 | struct vpd { | |
| 111 | union vac vac; | |
| 112 | union vdc vdc; | |
| 113 | unsigned long virt_env_vaddr; | |
| 114 | unsigned long reserved1[29]; | |
| 115 | unsigned long vhpi; | |
| 116 | unsigned long reserved2[95]; | |
| 117 | unsigned long vgr[16]; | |
| 118 | unsigned long vbgr[16]; | |
| 119 | unsigned long vnat; | |
| 120 | unsigned long vbnat; | |
| 121 | unsigned long vcpuid[5]; | |
| 122 | unsigned long reserved3[11]; | |
| 123 | unsigned long vpsr; | |
| 124 | unsigned long vpr; | |
| 125 | unsigned long reserved4[76]; | |
| 126 | union { | |
| 127 | unsigned long vcr[128]; | |
| 128 | struct { | |
| 129 | unsigned long dcr; | |
| 130 | unsigned long itm; | |
| 131 | unsigned long iva; | |
| 132 | unsigned long rsv1[5]; | |
| 133 | unsigned long pta; | |
| 134 | unsigned long rsv2[7]; | |
| 135 | unsigned long ipsr; | |
| 136 | unsigned long isr; | |
| 137 | unsigned long rsv3; | |
| 138 | unsigned long iip; | |
| 139 | unsigned long ifa; | |
| 140 | unsigned long itir; | |
| 141 | unsigned long iipa; | |
| 142 | unsigned long ifs; | |
| 143 | unsigned long iim; | |
| 144 | unsigned long iha; | |
| 145 | unsigned long rsv4[38]; | |
| 146 | unsigned long lid; | |
| 147 | unsigned long ivr; | |
| 148 | unsigned long tpr; | |
| 149 | unsigned long eoi; | |
| 150 | unsigned long irr[4]; | |
| 151 | unsigned long itv; | |
| 152 | unsigned long pmv; | |
| 153 | unsigned long cmcv; | |
| 154 | unsigned long rsv5[5]; | |
| 155 | unsigned long lrr0; | |
| 156 | unsigned long lrr1; | |
| 157 | unsigned long rsv6[46]; | |
| 158 | }; | |
| 159 | }; | |
| 160 | unsigned long reserved5[128]; | |
| 161 | unsigned long reserved6[3456]; | |
| 162 | unsigned long vmm_avail[128]; | |
| 163 | unsigned long reserved7[4096]; | |
| 164 | }; | |
| 165 | ||
| 166 | #define PAL_PROC_VM_BIT (1UL << 40) | |
| 167 | #define PAL_PROC_VMSW_BIT (1UL << 54) | |
| 168 | ||
| 169 | static inline s64 ia64_pal_vp_env_info(u64 *buffer_size, | |
| 170 | u64 *vp_env_info) | |
| 171 | { | |
| 172 | struct ia64_pal_retval iprv; | |
| 173 | PAL_CALL_STK(iprv, PAL_VP_ENV_INFO, 0, 0, 0); | |
| 174 | *buffer_size = iprv.v0; | |
| 175 | *vp_env_info = iprv.v1; | |
| 176 | return iprv.status; | |
| 177 | } | |
| 178 | ||
| 179 | static inline s64 ia64_pal_vp_exit_env(u64 iva) | |
| 180 | { | |
| 181 | struct ia64_pal_retval iprv; | |
| 182 | ||
| 183 | PAL_CALL_STK(iprv, PAL_VP_EXIT_ENV, (u64)iva, 0, 0); | |
| 184 | return iprv.status; | |
| 185 | } | |
| 186 | ||
| 187 | static inline s64 ia64_pal_vp_init_env(u64 config_options, u64 pbase_addr, | |
| 188 | u64 vbase_addr, u64 *vsa_base) | |
| 189 | { | |
| 190 | struct ia64_pal_retval iprv; | |
| 191 | ||
| 192 | PAL_CALL_STK(iprv, PAL_VP_INIT_ENV, config_options, pbase_addr, | |
| 193 | vbase_addr); | |
| 194 | *vsa_base = iprv.v0; | |
| 195 | ||
| 196 | return iprv.status; | |
| 197 | } | |
| 198 | ||
| 199 | static inline s64 ia64_pal_vp_restore(u64 *vpd, u64 pal_proc_vector) | |
| 200 | { | |
| 201 | struct ia64_pal_retval iprv; | |
| 202 | ||
| 203 | PAL_CALL_STK(iprv, PAL_VP_RESTORE, (u64)vpd, pal_proc_vector, 0); | |
| 204 | ||
| 205 | return iprv.status; | |
| 206 | } | |
| 207 | ||
| 208 | static inline s64 ia64_pal_vp_save(u64 *vpd, u64 pal_proc_vector) | |
| 209 | { | |
| 210 | struct ia64_pal_retval iprv; | |
| 211 | ||
| 212 | PAL_CALL_STK(iprv, PAL_VP_SAVE, (u64)vpd, pal_proc_vector, 0); | |
| 213 | ||
| 214 | return iprv.status; | |
| 215 | } | |
| 216 | ||
| 217 | #endif | |
| 218 | ||
| 219 | /*VPD field offset*/ | |
| 220 | #define VPD_VAC_START_OFFSET 0 | |
| 221 | #define VPD_VDC_START_OFFSET 8 | |
| 222 | #define VPD_VHPI_START_OFFSET 256 | |
| 223 | #define VPD_VGR_START_OFFSET 1024 | |
| 224 | #define VPD_VBGR_START_OFFSET 1152 | |
| 225 | #define VPD_VNAT_START_OFFSET 1280 | |
| 226 | #define VPD_VBNAT_START_OFFSET 1288 | |
| 227 | #define VPD_VCPUID_START_OFFSET 1296 | |
| 228 | #define VPD_VPSR_START_OFFSET 1424 | |
| 229 | #define VPD_VPR_START_OFFSET 1432 | |
| 230 | #define VPD_VRSE_CFLE_START_OFFSET 1440 | |
| 231 | #define VPD_VCR_START_OFFSET 2048 | |
| 232 | #define VPD_VTPR_START_OFFSET 2576 | |
| 233 | #define VPD_VRR_START_OFFSET 3072 | |
| 234 | #define VPD_VMM_VAIL_START_OFFSET 31744 | |
| 235 | ||
| 236 | /*Virtualization faults*/ | |
| 237 | ||
| 238 | #define EVENT_MOV_TO_AR 1 | |
| 239 | #define EVENT_MOV_TO_AR_IMM 2 | |
| 240 | #define EVENT_MOV_FROM_AR 3 | |
| 241 | #define EVENT_MOV_TO_CR 4 | |
| 242 | #define EVENT_MOV_FROM_CR 5 | |
| 243 | #define EVENT_MOV_TO_PSR 6 | |
| 244 | #define EVENT_MOV_FROM_PSR 7 | |
| 245 | #define EVENT_ITC_D 8 | |
| 246 | #define EVENT_ITC_I 9 | |
| 247 | #define EVENT_MOV_TO_RR 10 | |
| 248 | #define EVENT_MOV_TO_DBR 11 | |
| 249 | #define EVENT_MOV_TO_IBR 12 | |
| 250 | #define EVENT_MOV_TO_PKR 13 | |
| 251 | #define EVENT_MOV_TO_PMC 14 | |
| 252 | #define EVENT_MOV_TO_PMD 15 | |
| 253 | #define EVENT_ITR_D 16 | |
| 254 | #define EVENT_ITR_I 17 | |
| 255 | #define EVENT_MOV_FROM_RR 18 | |
| 256 | #define EVENT_MOV_FROM_DBR 19 | |
| 257 | #define EVENT_MOV_FROM_IBR 20 | |
| 258 | #define EVENT_MOV_FROM_PKR 21 | |
| 259 | #define EVENT_MOV_FROM_PMC 22 | |
| 260 | #define EVENT_MOV_FROM_CPUID 23 | |
| 261 | #define EVENT_SSM 24 | |
| 262 | #define EVENT_RSM 25 | |
| 263 | #define EVENT_PTC_L 26 | |
| 264 | #define EVENT_PTC_G 27 | |
| 265 | #define EVENT_PTC_GA 28 | |
| 266 | #define EVENT_PTR_D 29 | |
| 267 | #define EVENT_PTR_I 30 | |
| 268 | #define EVENT_THASH 31 | |
| 269 | #define EVENT_TTAG 32 | |
| 270 | #define EVENT_TPA 33 | |
| 271 | #define EVENT_TAK 34 | |
| 272 | #define EVENT_PTC_E 35 | |
| 273 | #define EVENT_COVER 36 | |
| 274 | #define EVENT_RFI 37 | |
| 275 | #define EVENT_BSW_0 38 | |
| 276 | #define EVENT_BSW_1 39 | |
| 277 | #define EVENT_VMSW 40 | |
| 278 | ||
| 279 | /**PAL virtual services offsets */ | |
| 280 | #define PAL_VPS_RESUME_NORMAL 0x0000 | |
| 281 | #define PAL_VPS_RESUME_HANDLER 0x0400 | |
| 282 | #define PAL_VPS_SYNC_READ 0x0800 | |
| 283 | #define PAL_VPS_SYNC_WRITE 0x0c00 | |
| 284 | #define PAL_VPS_SET_PENDING_INTERRUPT 0x1000 | |
| 285 | #define PAL_VPS_THASH 0x1400 | |
| 286 | #define PAL_VPS_TTAG 0x1800 | |
| 287 | #define PAL_VPS_RESTORE 0x1c00 | |
| 288 | #define PAL_VPS_SAVE 0x2000 | |
| 289 | ||
| 290 | #endif/* _VT_I_H*/ |