Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
b02a4a19 | 18 | #include <linux/pci-acpi.h> |
1da177e4 LT |
19 | #include <linux/init.h> |
20 | #include <linux/ioport.h> | |
21 | #include <linux/slab.h> | |
1da177e4 | 22 | #include <linux/spinlock.h> |
175add19 | 23 | #include <linux/bootmem.h> |
bd3ff194 | 24 | #include <linux/export.h> |
1da177e4 LT |
25 | |
26 | #include <asm/machvec.h> | |
27 | #include <asm/page.h> | |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/sal.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/hw_irq.h> | |
33 | ||
1da177e4 LT |
34 | /* |
35 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
36 | * calls are already serialized (via sal_lock), so we don't need another | |
37 | * synchronization mechanism here. | |
38 | */ | |
39 | ||
40 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
41 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
42 | ||
43 | /* SAL 3.2 adds support for extended config space. */ | |
44 | ||
45 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
46 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
47 | ||
b6ce068a | 48 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
49 | int reg, int len, u32 *value) |
50 | { | |
51 | u64 addr, data = 0; | |
52 | int mode, result; | |
53 | ||
54 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
55 | return -EINVAL; | |
56 | ||
57 | if ((seg | reg) <= 255) { | |
58 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
59 | mode = 0; | |
adcd7403 | 60 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
61 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
62 | mode = 1; | |
adcd7403 MW |
63 | } else { |
64 | return -EINVAL; | |
1da177e4 | 65 | } |
adcd7403 | 66 | |
1da177e4 LT |
67 | result = ia64_sal_pci_config_read(addr, mode, len, &data); |
68 | if (result != 0) | |
69 | return -EINVAL; | |
70 | ||
71 | *value = (u32) data; | |
72 | return 0; | |
73 | } | |
74 | ||
b6ce068a | 75 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
76 | int reg, int len, u32 value) |
77 | { | |
78 | u64 addr; | |
79 | int mode, result; | |
80 | ||
81 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
82 | return -EINVAL; | |
83 | ||
84 | if ((seg | reg) <= 255) { | |
85 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
86 | mode = 0; | |
adcd7403 | 87 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
88 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
89 | mode = 1; | |
adcd7403 MW |
90 | } else { |
91 | return -EINVAL; | |
1da177e4 LT |
92 | } |
93 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
94 | if (result != 0) | |
95 | return -EINVAL; | |
96 | return 0; | |
97 | } | |
98 | ||
b6ce068a MW |
99 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
100 | int size, u32 *value) | |
1da177e4 | 101 | { |
b6ce068a | 102 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
103 | devfn, where, size, value); |
104 | } | |
105 | ||
b6ce068a MW |
106 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
107 | int size, u32 value) | |
1da177e4 | 108 | { |
b6ce068a | 109 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
110 | devfn, where, size, value); |
111 | } | |
112 | ||
113 | struct pci_ops pci_root_ops = { | |
114 | .read = pci_read, | |
115 | .write = pci_write, | |
116 | }; | |
117 | ||
1da177e4 LT |
118 | /* Called by ACPI when it finds a new root bus. */ |
119 | ||
5b5e76e9 | 120 | static struct pci_controller *alloc_pci_controller(int seg) |
1da177e4 LT |
121 | { |
122 | struct pci_controller *controller; | |
123 | ||
52fd9108 | 124 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
125 | if (!controller) |
126 | return NULL; | |
127 | ||
1da177e4 LT |
128 | controller->segment = seg; |
129 | return controller; | |
130 | } | |
131 | ||
4f41d5a4 | 132 | struct pci_root_info { |
637b363e | 133 | struct acpi_device *bridge; |
4f41d5a4 | 134 | struct pci_controller *controller; |
e30f9922 | 135 | struct list_head resources; |
5cd7595d YW |
136 | struct resource *res; |
137 | resource_size_t *res_offset; | |
138 | unsigned int res_num; | |
c9e391cf | 139 | struct list_head io_resources; |
4f41d5a4 BH |
140 | char *name; |
141 | }; | |
142 | ||
143 | static unsigned int | |
144 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 145 | { |
4f41d5a4 | 146 | u64 mmio_base; |
1da177e4 LT |
147 | int i; |
148 | ||
4f41d5a4 BH |
149 | if (phys_base == 0) |
150 | return 0; /* legacy I/O port space */ | |
1da177e4 | 151 | |
4f41d5a4 | 152 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 153 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 154 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 155 | io_space[i].sparse == sparse) |
4f41d5a4 | 156 | return i; |
1da177e4 LT |
157 | |
158 | if (num_io_spaces == MAX_IO_SPACES) { | |
c4cbf6b9 | 159 | pr_err("PCI: Too many IO port spaces " |
4f41d5a4 | 160 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); |
1da177e4 LT |
161 | return ~0; |
162 | } | |
163 | ||
164 | i = num_io_spaces++; | |
4f41d5a4 | 165 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
166 | io_space[i].sparse = sparse; |
167 | ||
4f41d5a4 BH |
168 | return i; |
169 | } | |
170 | ||
5b5e76e9 GKH |
171 | static u64 add_io_space(struct pci_root_info *info, |
172 | struct acpi_resource_address64 *addr) | |
4f41d5a4 | 173 | { |
c9e391cf | 174 | struct iospace_resource *iospace; |
4f41d5a4 BH |
175 | struct resource *resource; |
176 | char *name; | |
e088a4ad | 177 | unsigned long base, min, max, base_port; |
4f41d5a4 BH |
178 | unsigned int sparse = 0, space_nr, len; |
179 | ||
c9e391cf JL |
180 | len = strlen(info->name) + 32; |
181 | iospace = kzalloc(sizeof(*iospace) + len, GFP_KERNEL); | |
182 | if (!iospace) { | |
c4cbf6b9 YW |
183 | dev_err(&info->bridge->dev, |
184 | "PCI: No memory for %s I/O port space\n", | |
185 | info->name); | |
4f41d5a4 BH |
186 | goto out; |
187 | } | |
188 | ||
c9e391cf | 189 | name = (char *)(iospace + 1); |
4f41d5a4 | 190 | |
50eca3eb | 191 | min = addr->minimum; |
4f41d5a4 | 192 | max = min + addr->address_length - 1; |
0897831b | 193 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
194 | sparse = 1; |
195 | ||
50eca3eb | 196 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 | 197 | if (space_nr == ~0) |
c9e391cf | 198 | goto free_resource; |
4f41d5a4 BH |
199 | |
200 | base = __pa(io_space[space_nr].mmio_base); | |
201 | base_port = IO_SPACE_BASE(space_nr); | |
202 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
203 | base_port + min, base_port + max); | |
204 | ||
205 | /* | |
206 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
207 | * mapping is done by the processor (not the bridge), ACPI may not | |
208 | * mark it as sparse. | |
209 | */ | |
210 | if (space_nr == 0) | |
211 | sparse = 1; | |
212 | ||
c9e391cf | 213 | resource = &iospace->res; |
4f41d5a4 BH |
214 | resource->name = name; |
215 | resource->flags = IORESOURCE_MEM; | |
216 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
217 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
c9e391cf JL |
218 | if (insert_resource(&iomem_resource, resource)) { |
219 | dev_err(&info->bridge->dev, | |
220 | "can't allocate host bridge io space resource %pR\n", | |
221 | resource); | |
222 | goto free_resource; | |
223 | } | |
4f41d5a4 | 224 | |
c9e391cf | 225 | list_add_tail(&iospace->list, &info->io_resources); |
4f41d5a4 BH |
226 | return base_port; |
227 | ||
4f41d5a4 | 228 | free_resource: |
c9e391cf | 229 | kfree(iospace); |
4f41d5a4 BH |
230 | out: |
231 | return ~0; | |
1da177e4 LT |
232 | } |
233 | ||
5b5e76e9 GKH |
234 | static acpi_status resource_to_window(struct acpi_resource *resource, |
235 | struct acpi_resource_address64 *addr) | |
463eb297 BH |
236 | { |
237 | acpi_status status; | |
238 | ||
239 | /* | |
240 | * We're only interested in _CRS descriptors that are | |
241 | * - address space descriptors for memory or I/O space | |
242 | * - non-zero size | |
243 | * - producers, i.e., the address space is routed downstream, | |
244 | * not consumed by the bridge itself | |
245 | */ | |
246 | status = acpi_resource_to_address64(resource, addr); | |
247 | if (ACPI_SUCCESS(status) && | |
248 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
249 | addr->resource_type == ACPI_IO_RANGE) && | |
250 | addr->address_length && | |
251 | addr->producer_consumer == ACPI_PRODUCER) | |
252 | return AE_OK; | |
253 | ||
254 | return AE_ERROR; | |
255 | } | |
256 | ||
5b5e76e9 | 257 | static acpi_status count_window(struct acpi_resource *resource, void *data) |
1da177e4 LT |
258 | { |
259 | unsigned int *windows = (unsigned int *) data; | |
260 | struct acpi_resource_address64 addr; | |
261 | acpi_status status; | |
262 | ||
463eb297 | 263 | status = resource_to_window(resource, &addr); |
1da177e4 | 264 | if (ACPI_SUCCESS(status)) |
463eb297 | 265 | (*windows)++; |
1da177e4 LT |
266 | |
267 | return AE_OK; | |
268 | } | |
269 | ||
5b5e76e9 | 270 | static acpi_status add_window(struct acpi_resource *res, void *data) |
1da177e4 LT |
271 | { |
272 | struct pci_root_info *info = data; | |
5cd7595d | 273 | struct resource *resource; |
1da177e4 LT |
274 | struct acpi_resource_address64 addr; |
275 | acpi_status status; | |
276 | unsigned long flags, offset = 0; | |
277 | struct resource *root; | |
278 | ||
463eb297 BH |
279 | /* Return AE_OK for non-window resources to keep scanning for more */ |
280 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
281 | if (!ACPI_SUCCESS(status)) |
282 | return AE_OK; | |
283 | ||
1da177e4 LT |
284 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
285 | flags = IORESOURCE_MEM; | |
286 | root = &iomem_resource; | |
50eca3eb | 287 | offset = addr.translation_offset; |
1da177e4 LT |
288 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
289 | flags = IORESOURCE_IO; | |
290 | root = &ioport_resource; | |
4f41d5a4 | 291 | offset = add_io_space(info, &addr); |
1da177e4 LT |
292 | if (offset == ~0) |
293 | return AE_OK; | |
294 | } else | |
295 | return AE_OK; | |
296 | ||
5cd7595d YW |
297 | resource = &info->res[info->res_num]; |
298 | resource->name = info->name; | |
299 | resource->flags = flags; | |
300 | resource->start = addr.minimum + offset; | |
301 | resource->end = resource->start + addr.address_length - 1; | |
302 | info->res_offset[info->res_num] = offset; | |
1da177e4 | 303 | |
5cd7595d | 304 | if (insert_resource(root, resource)) { |
c7dabef8 BH |
305 | dev_err(&info->bridge->dev, |
306 | "can't allocate host bridge window %pR\n", | |
5cd7595d | 307 | resource); |
637b363e BH |
308 | } else { |
309 | if (offset) | |
c7dabef8 | 310 | dev_info(&info->bridge->dev, "host bridge window %pR " |
637b363e | 311 | "(PCI address [%#llx-%#llx])\n", |
5cd7595d YW |
312 | resource, |
313 | resource->start - offset, | |
314 | resource->end - offset); | |
637b363e BH |
315 | else |
316 | dev_info(&info->bridge->dev, | |
5cd7595d | 317 | "host bridge window %pR\n", resource); |
1da177e4 | 318 | } |
e30f9922 BH |
319 | /* HP's firmware has a hack to work around a Windows bug. |
320 | * Ignore these tiny memory ranges */ | |
5cd7595d YW |
321 | if (!((resource->flags & IORESOURCE_MEM) && |
322 | (resource->end - resource->start < 16))) | |
323 | pci_add_resource_offset(&info->resources, resource, | |
324 | info->res_offset[info->res_num]); | |
1da177e4 | 325 | |
5cd7595d | 326 | info->res_num++; |
e30f9922 | 327 | return AE_OK; |
1da177e4 LT |
328 | } |
329 | ||
c9e391cf JL |
330 | static void free_pci_root_info_res(struct pci_root_info *info) |
331 | { | |
332 | struct iospace_resource *iospace, *tmp; | |
333 | ||
334 | list_for_each_entry_safe(iospace, tmp, &info->io_resources, list) | |
335 | kfree(iospace); | |
336 | ||
337 | kfree(info->name); | |
338 | kfree(info->res); | |
339 | info->res = NULL; | |
340 | kfree(info->res_offset); | |
341 | info->res_offset = NULL; | |
342 | info->res_num = 0; | |
343 | kfree(info->controller); | |
344 | info->controller = NULL; | |
345 | } | |
346 | ||
347 | static void __release_pci_root_info(struct pci_root_info *info) | |
348 | { | |
349 | int i; | |
350 | struct resource *res; | |
351 | struct iospace_resource *iospace; | |
352 | ||
353 | list_for_each_entry(iospace, &info->io_resources, list) | |
354 | release_resource(&iospace->res); | |
355 | ||
356 | for (i = 0; i < info->res_num; i++) { | |
357 | res = &info->res[i]; | |
358 | ||
359 | if (!res->parent) | |
360 | continue; | |
361 | ||
362 | if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) | |
363 | continue; | |
364 | ||
365 | release_resource(res); | |
366 | } | |
367 | ||
368 | free_pci_root_info_res(info); | |
369 | kfree(info); | |
370 | } | |
371 | ||
2932239f YW |
372 | static void release_pci_root_info(struct pci_host_bridge *bridge) |
373 | { | |
374 | struct pci_root_info *info = bridge->release_data; | |
375 | ||
376 | __release_pci_root_info(info); | |
377 | } | |
378 | ||
3a72af09 YW |
379 | static int |
380 | probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device, | |
381 | int busnum, int domain) | |
382 | { | |
383 | char *name; | |
384 | ||
385 | name = kmalloc(16, GFP_KERNEL); | |
386 | if (!name) | |
387 | return -ENOMEM; | |
388 | ||
389 | sprintf(name, "PCI Bus %04x:%02x", domain, busnum); | |
390 | info->bridge = device; | |
391 | info->name = name; | |
392 | ||
393 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, | |
394 | &info->res_num); | |
395 | if (info->res_num) { | |
396 | info->res = | |
397 | kzalloc_node(sizeof(*info->res) * info->res_num, | |
398 | GFP_KERNEL, info->controller->node); | |
399 | if (!info->res) { | |
400 | kfree(name); | |
401 | return -ENOMEM; | |
402 | } | |
403 | ||
404 | info->res_offset = | |
405 | kzalloc_node(sizeof(*info->res_offset) * info->res_num, | |
406 | GFP_KERNEL, info->controller->node); | |
407 | if (!info->res_offset) { | |
408 | kfree(name); | |
409 | kfree(info->res); | |
410 | info->res = NULL; | |
411 | return -ENOMEM; | |
412 | } | |
413 | ||
414 | info->res_num = 0; | |
415 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
416 | add_window, info); | |
417 | } else | |
418 | kfree(name); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
5b5e76e9 | 423 | struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) |
1da177e4 | 424 | { |
57283776 BH |
425 | struct acpi_device *device = root->device; |
426 | int domain = root->segment; | |
427 | int bus = root->secondary.start; | |
1da177e4 | 428 | struct pci_controller *controller; |
429ac099 YW |
429 | struct pci_root_info *info = NULL; |
430 | int busnum = root->secondary.start; | |
1da177e4 | 431 | struct pci_bus *pbus; |
b1e9cee7 | 432 | int ret; |
1da177e4 LT |
433 | |
434 | controller = alloc_pci_controller(domain); | |
435 | if (!controller) | |
3a72af09 | 436 | return NULL; |
1da177e4 | 437 | |
7b199811 | 438 | controller->companion = device; |
b1e9cee7 | 439 | controller->node = acpi_get_node(device->handle); |
514604c6 | 440 | |
429ac099 YW |
441 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
442 | if (!info) { | |
c4cbf6b9 | 443 | dev_err(&device->dev, |
429ac099 | 444 | "pci_bus %04x:%02x: ignored (out of memory)\n", |
3a72af09 YW |
445 | domain, busnum); |
446 | kfree(controller); | |
447 | return NULL; | |
429ac099 YW |
448 | } |
449 | ||
3a72af09 | 450 | info->controller = controller; |
c9e391cf | 451 | INIT_LIST_HEAD(&info->io_resources); |
429ac099 | 452 | INIT_LIST_HEAD(&info->resources); |
1da177e4 | 453 | |
3a72af09 YW |
454 | ret = probe_pci_root_info(info, device, busnum, domain); |
455 | if (ret) { | |
456 | kfree(info->controller); | |
457 | kfree(info); | |
458 | return NULL; | |
8a20fd52 | 459 | } |
3a72af09 YW |
460 | /* insert busn resource at first */ |
461 | pci_add_resource(&info->resources, &root->secondary); | |
b87e81e5 | 462 | /* |
463 | * See arch/x86/pci/acpi.c. | |
464 | * The desired pci bus might already be scanned in a quirk. We | |
465 | * should handle the case here, but it appears that IA64 hasn't | |
466 | * such quirk. So we just ignore the case now. | |
467 | */ | |
e30f9922 | 468 | pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller, |
429ac099 | 469 | &info->resources); |
e30f9922 | 470 | if (!pbus) { |
429ac099 | 471 | pci_free_resource_list(&info->resources); |
c9e391cf | 472 | __release_pci_root_info(info); |
79e77f27 | 473 | return NULL; |
e30f9922 | 474 | } |
1da177e4 | 475 | |
2932239f YW |
476 | pci_set_host_bridge_release(to_pci_host_bridge(pbus->bridge), |
477 | release_pci_root_info, info); | |
2661b819 | 478 | pci_scan_child_bus(pbus); |
1da177e4 | 479 | return pbus; |
1da177e4 LT |
480 | } |
481 | ||
6c0cc950 RW |
482 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
483 | { | |
484 | struct pci_controller *controller = bridge->bus->sysdata; | |
485 | ||
7b199811 | 486 | ACPI_COMPANION_SET(&bridge->dev, controller->companion); |
6c0cc950 RW |
487 | return 0; |
488 | } | |
489 | ||
5b5e76e9 | 490 | static int is_valid_resource(struct pci_dev *dev, int idx) |
71c3511c RS |
491 | { |
492 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
89a74ecc | 493 | struct resource *devr = &dev->resource[idx], *busr; |
71c3511c RS |
494 | |
495 | if (!dev->bus) | |
496 | return 0; | |
71c3511c | 497 | |
89a74ecc | 498 | pci_bus_for_each_resource(dev->bus, busr, i) { |
71c3511c RS |
499 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) |
500 | continue; | |
501 | if ((devr->start) && (devr->start >= busr->start) && | |
502 | (devr->end <= busr->end)) | |
503 | return 1; | |
504 | } | |
505 | return 0; | |
506 | } | |
507 | ||
5b5e76e9 | 508 | static void pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) |
1da177e4 | 509 | { |
1da177e4 | 510 | int i; |
1da177e4 | 511 | |
7b9c8ba2 | 512 | for (i = start; i < limit; i++) { |
1da177e4 LT |
513 | if (!dev->resource[i].flags) |
514 | continue; | |
71c3511c RS |
515 | if ((is_valid_resource(dev, i))) |
516 | pci_claim_resource(dev, i); | |
1da177e4 LT |
517 | } |
518 | } | |
519 | ||
5b5e76e9 | 520 | void pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
521 | { |
522 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
523 | } | |
8ea6091f | 524 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 | 525 | |
5b5e76e9 | 526 | static void pcibios_fixup_bridge_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
527 | { |
528 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
529 | } | |
530 | ||
1da177e4 LT |
531 | /* |
532 | * Called after each bus is probed, but before its children are examined. | |
533 | */ | |
5b5e76e9 | 534 | void pcibios_fixup_bus(struct pci_bus *b) |
1da177e4 LT |
535 | { |
536 | struct pci_dev *dev; | |
537 | ||
f7d473d9 RS |
538 | if (b->self) { |
539 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 540 | pcibios_fixup_bridge_resources(b->self); |
f7d473d9 | 541 | } |
1da177e4 LT |
542 | list_for_each_entry(dev, &b->devices, bus_list) |
543 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 544 | platform_pci_fixup_bus(b); |
1da177e4 LT |
545 | } |
546 | ||
b02a4a19 JL |
547 | void pcibios_add_bus(struct pci_bus *bus) |
548 | { | |
549 | acpi_pci_add_bus(bus); | |
550 | } | |
551 | ||
552 | void pcibios_remove_bus(struct pci_bus *bus) | |
553 | { | |
554 | acpi_pci_remove_bus(bus); | |
555 | } | |
556 | ||
91e86df1 MS |
557 | void pcibios_set_master (struct pci_dev *dev) |
558 | { | |
559 | /* No special bus mastering setup handling */ | |
560 | } | |
561 | ||
1da177e4 LT |
562 | int |
563 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
564 | { | |
565 | int ret; | |
566 | ||
d981f163 | 567 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
568 | if (ret < 0) |
569 | return ret; | |
570 | ||
bba6f6fc EB |
571 | if (!dev->msi_enabled) |
572 | return acpi_pci_irq_enable(dev); | |
573 | return 0; | |
1da177e4 LT |
574 | } |
575 | ||
1da177e4 LT |
576 | void |
577 | pcibios_disable_device (struct pci_dev *dev) | |
578 | { | |
c7f570a5 | 579 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
580 | if (!dev->msi_enabled) |
581 | acpi_pci_irq_disable(dev); | |
1da177e4 | 582 | } |
1da177e4 | 583 | |
b26b2d49 | 584 | resource_size_t |
3b7a17fc | 585 | pcibios_align_resource (void *data, const struct resource *res, |
e31dd6e4 | 586 | resource_size_t size, resource_size_t align) |
1da177e4 | 587 | { |
b26b2d49 | 588 | return res->start; |
1da177e4 LT |
589 | } |
590 | ||
1da177e4 LT |
591 | int |
592 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
593 | enum pci_mmap_state mmap_state, int write_combine) | |
594 | { | |
012b7105 AC |
595 | unsigned long size = vma->vm_end - vma->vm_start; |
596 | pgprot_t prot; | |
597 | ||
1da177e4 LT |
598 | /* |
599 | * I/O space cannot be accessed via normal processor loads and | |
600 | * stores on this platform. | |
601 | */ | |
602 | if (mmap_state == pci_mmap_io) | |
603 | /* | |
604 | * XXX we could relax this for I/O spaces for which ACPI | |
605 | * indicates that the space is 1-to-1 mapped. But at the | |
606 | * moment, we don't support multiple PCI address spaces and | |
607 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
608 | */ | |
609 | return -EINVAL; | |
610 | ||
012b7105 AC |
611 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
612 | return -EINVAL; | |
613 | ||
614 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
615 | vma->vm_page_prot); | |
616 | ||
1da177e4 | 617 | /* |
012b7105 AC |
618 | * If the user requested WC, the kernel uses UC or WC for this region, |
619 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
620 | * use the same attribute the kernel uses. | |
1da177e4 | 621 | */ |
012b7105 AC |
622 | if (write_combine && |
623 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
624 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
625 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
626 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
627 | else | |
012b7105 | 628 | vma->vm_page_prot = prot; |
1da177e4 LT |
629 | |
630 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
631 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
632 | return -EAGAIN; | |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
637 | /** | |
638 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
639 | * @bus: bus to get legacy memory base address for | |
640 | * | |
641 | * Find the base of legacy memory for @bus. This is typically the first | |
642 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
643 | * chipsets support legacy I/O and memory routing. Returns the base address | |
644 | * or an error pointer if an error occurred. | |
645 | * | |
646 | * This is the ia64 generic version of this routine. Other platforms | |
647 | * are free to override it with a machine vector. | |
648 | */ | |
649 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
650 | { | |
651 | return (char *)__IA64_UNCACHED_OFFSET; | |
652 | } | |
653 | ||
654 | /** | |
655 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
656 | * @bus: bus whose legacy space we're mapping | |
657 | * @vma: vma passed in by mmap | |
658 | * | |
659 | * Map legacy memory space for this device back to userspace using a machine | |
660 | * vector to get the base address. | |
661 | */ | |
662 | int | |
f19aeb1f BH |
663 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
664 | enum pci_mmap_state mmap_state) | |
1da177e4 | 665 | { |
32e62c63 BH |
666 | unsigned long size = vma->vm_end - vma->vm_start; |
667 | pgprot_t prot; | |
1da177e4 LT |
668 | char *addr; |
669 | ||
f19aeb1f BH |
670 | /* We only support mmap'ing of legacy memory space */ |
671 | if (mmap_state != pci_mmap_mem) | |
672 | return -ENOSYS; | |
673 | ||
32e62c63 BH |
674 | /* |
675 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
676 | * for more details. | |
677 | */ | |
06c67bef | 678 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
679 | return -EINVAL; |
680 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
681 | vma->vm_page_prot); | |
32e62c63 | 682 | |
1da177e4 LT |
683 | addr = pci_get_legacy_mem(bus); |
684 | if (IS_ERR(addr)) | |
685 | return PTR_ERR(addr); | |
686 | ||
687 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 688 | vma->vm_page_prot = prot; |
1da177e4 LT |
689 | |
690 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 691 | size, vma->vm_page_prot)) |
1da177e4 LT |
692 | return -EAGAIN; |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | /** | |
698 | * ia64_pci_legacy_read - read from legacy I/O space | |
699 | * @bus: bus to read | |
700 | * @port: legacy port value | |
701 | * @val: caller allocated storage for returned value | |
702 | * @size: number of bytes to read | |
703 | * | |
704 | * Simply reads @size bytes from @port and puts the result in @val. | |
705 | * | |
706 | * Again, this (and the write routine) are generic versions that can be | |
707 | * overridden by the platform. This is necessary on platforms that don't | |
708 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
709 | */ | |
710 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
711 | { | |
712 | int ret = size; | |
713 | ||
714 | switch (size) { | |
715 | case 1: | |
716 | *val = inb(port); | |
717 | break; | |
718 | case 2: | |
719 | *val = inw(port); | |
720 | break; | |
721 | case 4: | |
722 | *val = inl(port); | |
723 | break; | |
724 | default: | |
725 | ret = -EINVAL; | |
726 | break; | |
727 | } | |
728 | ||
729 | return ret; | |
730 | } | |
731 | ||
732 | /** | |
733 | * ia64_pci_legacy_write - perform a legacy I/O write | |
734 | * @bus: bus pointer | |
735 | * @port: port to write | |
736 | * @val: value to write | |
737 | * @size: number of bytes to write from @val | |
738 | * | |
739 | * Simply writes @size bytes of @val to @port. | |
740 | */ | |
a72391e4 | 741 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 742 | { |
408045af | 743 | int ret = size; |
1da177e4 LT |
744 | |
745 | switch (size) { | |
746 | case 1: | |
747 | outb(val, port); | |
748 | break; | |
749 | case 2: | |
750 | outw(val, port); | |
751 | break; | |
752 | case 4: | |
753 | outl(val, port); | |
754 | break; | |
755 | default: | |
756 | ret = -EINVAL; | |
757 | break; | |
758 | } | |
759 | ||
760 | return ret; | |
761 | } | |
762 | ||
763 | /** | |
3efe2d84 | 764 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
765 | * |
766 | * We want to use the line-size of the outer-most cache. We assume | |
767 | * that this line-size is the same for all CPUs. | |
768 | * | |
769 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 770 | */ |
ac1aa47b | 771 | static void __init set_pci_dfl_cacheline_size(void) |
1da177e4 | 772 | { |
e088a4ad MW |
773 | unsigned long levels, unique_caches; |
774 | long status; | |
1da177e4 | 775 | pal_cache_config_info_t cci; |
1da177e4 LT |
776 | |
777 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
778 | if (status != 0) { | |
c4cbf6b9 | 779 | pr_err("%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 780 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 781 | return; |
1da177e4 LT |
782 | } |
783 | ||
3efe2d84 MW |
784 | status = ia64_pal_cache_config_info(levels - 1, |
785 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 786 | if (status != 0) { |
c4cbf6b9 | 787 | pr_err("%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 788 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 789 | return; |
1da177e4 | 790 | } |
ac1aa47b | 791 | pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
792 | } |
793 | ||
175add19 JK |
794 | u64 ia64_dma_get_required_mask(struct device *dev) |
795 | { | |
796 | u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); | |
797 | u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); | |
798 | u64 mask; | |
799 | ||
800 | if (!high_totalram) { | |
801 | /* convert to mask just covering totalram */ | |
802 | low_totalram = (1 << (fls(low_totalram) - 1)); | |
803 | low_totalram += low_totalram - 1; | |
804 | mask = low_totalram; | |
805 | } else { | |
806 | high_totalram = (1 << (fls(high_totalram) - 1)); | |
807 | high_totalram += high_totalram - 1; | |
808 | mask = (((u64)high_totalram) << 32) + 0xffffffff; | |
809 | } | |
810 | return mask; | |
811 | } | |
812 | EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); | |
813 | ||
814 | u64 dma_get_required_mask(struct device *dev) | |
815 | { | |
816 | return platform_dma_get_required_mask(dev); | |
817 | } | |
818 | EXPORT_SYMBOL_GPL(dma_get_required_mask); | |
819 | ||
3efe2d84 MW |
820 | static int __init pcibios_init(void) |
821 | { | |
ac1aa47b | 822 | set_pci_dfl_cacheline_size(); |
3efe2d84 | 823 | return 0; |
1da177e4 | 824 | } |
3efe2d84 MW |
825 | |
826 | subsys_initcall(pcibios_init); |