Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
b02a4a19 | 18 | #include <linux/pci-acpi.h> |
1da177e4 LT |
19 | #include <linux/init.h> |
20 | #include <linux/ioport.h> | |
21 | #include <linux/slab.h> | |
1da177e4 | 22 | #include <linux/spinlock.h> |
175add19 | 23 | #include <linux/bootmem.h> |
bd3ff194 | 24 | #include <linux/export.h> |
1da177e4 LT |
25 | |
26 | #include <asm/machvec.h> | |
27 | #include <asm/page.h> | |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/sal.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/hw_irq.h> | |
33 | ||
1da177e4 LT |
34 | /* |
35 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
36 | * calls are already serialized (via sal_lock), so we don't need another | |
37 | * synchronization mechanism here. | |
38 | */ | |
39 | ||
40 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
41 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
42 | ||
43 | /* SAL 3.2 adds support for extended config space. */ | |
44 | ||
45 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
46 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
47 | ||
b6ce068a | 48 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
49 | int reg, int len, u32 *value) |
50 | { | |
51 | u64 addr, data = 0; | |
52 | int mode, result; | |
53 | ||
54 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
55 | return -EINVAL; | |
56 | ||
57 | if ((seg | reg) <= 255) { | |
58 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
59 | mode = 0; | |
adcd7403 | 60 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
61 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
62 | mode = 1; | |
adcd7403 MW |
63 | } else { |
64 | return -EINVAL; | |
1da177e4 | 65 | } |
adcd7403 | 66 | |
1da177e4 LT |
67 | result = ia64_sal_pci_config_read(addr, mode, len, &data); |
68 | if (result != 0) | |
69 | return -EINVAL; | |
70 | ||
71 | *value = (u32) data; | |
72 | return 0; | |
73 | } | |
74 | ||
b6ce068a | 75 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
76 | int reg, int len, u32 value) |
77 | { | |
78 | u64 addr; | |
79 | int mode, result; | |
80 | ||
81 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
82 | return -EINVAL; | |
83 | ||
84 | if ((seg | reg) <= 255) { | |
85 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
86 | mode = 0; | |
adcd7403 | 87 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
88 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
89 | mode = 1; | |
adcd7403 MW |
90 | } else { |
91 | return -EINVAL; | |
1da177e4 LT |
92 | } |
93 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
94 | if (result != 0) | |
95 | return -EINVAL; | |
96 | return 0; | |
97 | } | |
98 | ||
b6ce068a MW |
99 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
100 | int size, u32 *value) | |
1da177e4 | 101 | { |
b6ce068a | 102 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
103 | devfn, where, size, value); |
104 | } | |
105 | ||
b6ce068a MW |
106 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
107 | int size, u32 value) | |
1da177e4 | 108 | { |
b6ce068a | 109 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
110 | devfn, where, size, value); |
111 | } | |
112 | ||
113 | struct pci_ops pci_root_ops = { | |
114 | .read = pci_read, | |
115 | .write = pci_write, | |
116 | }; | |
117 | ||
1da177e4 LT |
118 | /* Called by ACPI when it finds a new root bus. */ |
119 | ||
5b5e76e9 | 120 | static struct pci_controller *alloc_pci_controller(int seg) |
1da177e4 LT |
121 | { |
122 | struct pci_controller *controller; | |
123 | ||
52fd9108 | 124 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
125 | if (!controller) |
126 | return NULL; | |
127 | ||
1da177e4 | 128 | controller->segment = seg; |
514604c6 | 129 | controller->node = -1; |
1da177e4 LT |
130 | return controller; |
131 | } | |
132 | ||
4f41d5a4 | 133 | struct pci_root_info { |
637b363e | 134 | struct acpi_device *bridge; |
4f41d5a4 | 135 | struct pci_controller *controller; |
e30f9922 | 136 | struct list_head resources; |
5cd7595d YW |
137 | struct resource *res; |
138 | resource_size_t *res_offset; | |
139 | unsigned int res_num; | |
4f41d5a4 BH |
140 | char *name; |
141 | }; | |
142 | ||
143 | static unsigned int | |
144 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 145 | { |
4f41d5a4 | 146 | u64 mmio_base; |
1da177e4 LT |
147 | int i; |
148 | ||
4f41d5a4 BH |
149 | if (phys_base == 0) |
150 | return 0; /* legacy I/O port space */ | |
1da177e4 | 151 | |
4f41d5a4 | 152 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 153 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 154 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 155 | io_space[i].sparse == sparse) |
4f41d5a4 | 156 | return i; |
1da177e4 LT |
157 | |
158 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
159 | printk(KERN_ERR "PCI: Too many IO port spaces " |
160 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
161 | return ~0; |
162 | } | |
163 | ||
164 | i = num_io_spaces++; | |
4f41d5a4 | 165 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
166 | io_space[i].sparse = sparse; |
167 | ||
4f41d5a4 BH |
168 | return i; |
169 | } | |
170 | ||
5b5e76e9 GKH |
171 | static u64 add_io_space(struct pci_root_info *info, |
172 | struct acpi_resource_address64 *addr) | |
4f41d5a4 BH |
173 | { |
174 | struct resource *resource; | |
175 | char *name; | |
e088a4ad | 176 | unsigned long base, min, max, base_port; |
4f41d5a4 BH |
177 | unsigned int sparse = 0, space_nr, len; |
178 | ||
179 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
180 | if (!resource) { | |
181 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
182 | info->name); | |
183 | goto out; | |
184 | } | |
185 | ||
186 | len = strlen(info->name) + 32; | |
187 | name = kzalloc(len, GFP_KERNEL); | |
188 | if (!name) { | |
189 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
190 | info->name); | |
191 | goto free_resource; | |
192 | } | |
193 | ||
50eca3eb | 194 | min = addr->minimum; |
4f41d5a4 | 195 | max = min + addr->address_length - 1; |
0897831b | 196 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
197 | sparse = 1; |
198 | ||
50eca3eb | 199 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
200 | if (space_nr == ~0) |
201 | goto free_name; | |
202 | ||
203 | base = __pa(io_space[space_nr].mmio_base); | |
204 | base_port = IO_SPACE_BASE(space_nr); | |
205 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
206 | base_port + min, base_port + max); | |
207 | ||
208 | /* | |
209 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
210 | * mapping is done by the processor (not the bridge), ACPI may not | |
211 | * mark it as sparse. | |
212 | */ | |
213 | if (space_nr == 0) | |
214 | sparse = 1; | |
215 | ||
216 | resource->name = name; | |
217 | resource->flags = IORESOURCE_MEM; | |
218 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
219 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
220 | insert_resource(&iomem_resource, resource); | |
221 | ||
222 | return base_port; | |
223 | ||
224 | free_name: | |
225 | kfree(name); | |
226 | free_resource: | |
227 | kfree(resource); | |
228 | out: | |
229 | return ~0; | |
1da177e4 LT |
230 | } |
231 | ||
5b5e76e9 GKH |
232 | static acpi_status resource_to_window(struct acpi_resource *resource, |
233 | struct acpi_resource_address64 *addr) | |
463eb297 BH |
234 | { |
235 | acpi_status status; | |
236 | ||
237 | /* | |
238 | * We're only interested in _CRS descriptors that are | |
239 | * - address space descriptors for memory or I/O space | |
240 | * - non-zero size | |
241 | * - producers, i.e., the address space is routed downstream, | |
242 | * not consumed by the bridge itself | |
243 | */ | |
244 | status = acpi_resource_to_address64(resource, addr); | |
245 | if (ACPI_SUCCESS(status) && | |
246 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
247 | addr->resource_type == ACPI_IO_RANGE) && | |
248 | addr->address_length && | |
249 | addr->producer_consumer == ACPI_PRODUCER) | |
250 | return AE_OK; | |
251 | ||
252 | return AE_ERROR; | |
253 | } | |
254 | ||
5b5e76e9 | 255 | static acpi_status count_window(struct acpi_resource *resource, void *data) |
1da177e4 LT |
256 | { |
257 | unsigned int *windows = (unsigned int *) data; | |
258 | struct acpi_resource_address64 addr; | |
259 | acpi_status status; | |
260 | ||
463eb297 | 261 | status = resource_to_window(resource, &addr); |
1da177e4 | 262 | if (ACPI_SUCCESS(status)) |
463eb297 | 263 | (*windows)++; |
1da177e4 LT |
264 | |
265 | return AE_OK; | |
266 | } | |
267 | ||
5b5e76e9 | 268 | static acpi_status add_window(struct acpi_resource *res, void *data) |
1da177e4 LT |
269 | { |
270 | struct pci_root_info *info = data; | |
5cd7595d | 271 | struct resource *resource; |
1da177e4 LT |
272 | struct acpi_resource_address64 addr; |
273 | acpi_status status; | |
274 | unsigned long flags, offset = 0; | |
275 | struct resource *root; | |
276 | ||
463eb297 BH |
277 | /* Return AE_OK for non-window resources to keep scanning for more */ |
278 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
279 | if (!ACPI_SUCCESS(status)) |
280 | return AE_OK; | |
281 | ||
1da177e4 LT |
282 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
283 | flags = IORESOURCE_MEM; | |
284 | root = &iomem_resource; | |
50eca3eb | 285 | offset = addr.translation_offset; |
1da177e4 LT |
286 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
287 | flags = IORESOURCE_IO; | |
288 | root = &ioport_resource; | |
4f41d5a4 | 289 | offset = add_io_space(info, &addr); |
1da177e4 LT |
290 | if (offset == ~0) |
291 | return AE_OK; | |
292 | } else | |
293 | return AE_OK; | |
294 | ||
5cd7595d YW |
295 | resource = &info->res[info->res_num]; |
296 | resource->name = info->name; | |
297 | resource->flags = flags; | |
298 | resource->start = addr.minimum + offset; | |
299 | resource->end = resource->start + addr.address_length - 1; | |
300 | info->res_offset[info->res_num] = offset; | |
1da177e4 | 301 | |
5cd7595d | 302 | if (insert_resource(root, resource)) { |
c7dabef8 BH |
303 | dev_err(&info->bridge->dev, |
304 | "can't allocate host bridge window %pR\n", | |
5cd7595d | 305 | resource); |
637b363e BH |
306 | } else { |
307 | if (offset) | |
c7dabef8 | 308 | dev_info(&info->bridge->dev, "host bridge window %pR " |
637b363e | 309 | "(PCI address [%#llx-%#llx])\n", |
5cd7595d YW |
310 | resource, |
311 | resource->start - offset, | |
312 | resource->end - offset); | |
637b363e BH |
313 | else |
314 | dev_info(&info->bridge->dev, | |
5cd7595d | 315 | "host bridge window %pR\n", resource); |
1da177e4 | 316 | } |
e30f9922 BH |
317 | /* HP's firmware has a hack to work around a Windows bug. |
318 | * Ignore these tiny memory ranges */ | |
5cd7595d YW |
319 | if (!((resource->flags & IORESOURCE_MEM) && |
320 | (resource->end - resource->start < 16))) | |
321 | pci_add_resource_offset(&info->resources, resource, | |
322 | info->res_offset[info->res_num]); | |
1da177e4 | 323 | |
5cd7595d | 324 | info->res_num++; |
e30f9922 | 325 | return AE_OK; |
1da177e4 LT |
326 | } |
327 | ||
5b5e76e9 | 328 | struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) |
1da177e4 | 329 | { |
57283776 BH |
330 | struct acpi_device *device = root->device; |
331 | int domain = root->segment; | |
332 | int bus = root->secondary.start; | |
1da177e4 | 333 | struct pci_controller *controller; |
429ac099 YW |
334 | struct pci_root_info *info = NULL; |
335 | int busnum = root->secondary.start; | |
1da177e4 LT |
336 | struct pci_bus *pbus; |
337 | char *name; | |
514604c6 | 338 | int pxm; |
1da177e4 LT |
339 | |
340 | controller = alloc_pci_controller(domain); | |
341 | if (!controller) | |
342 | goto out1; | |
343 | ||
344 | controller->acpi_handle = device->handle; | |
345 | ||
514604c6 CL |
346 | pxm = acpi_get_pxm(controller->acpi_handle); |
347 | #ifdef CONFIG_NUMA | |
348 | if (pxm >= 0) | |
762834e8 | 349 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
350 | #endif |
351 | ||
429ac099 YW |
352 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
353 | if (!info) { | |
354 | printk(KERN_WARNING | |
355 | "pci_bus %04x:%02x: ignored (out of memory)\n", | |
356 | root->segment, busnum); | |
357 | goto out2; | |
358 | } | |
359 | ||
360 | INIT_LIST_HEAD(&info->resources); | |
2661b819 | 361 | /* insert busn resource at first */ |
429ac099 | 362 | pci_add_resource(&info->resources, &root->secondary); |
1da177e4 | 363 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
429ac099 YW |
364 | &info->res_num); |
365 | if (info->res_num) { | |
366 | info->res = | |
367 | kzalloc_node(sizeof(*info->res) * info->res_num, | |
a66aa704 | 368 | GFP_KERNEL, controller->node); |
429ac099 YW |
369 | if (!info->res) |
370 | goto out3; | |
1da177e4 | 371 | |
429ac099 YW |
372 | info->res_offset = |
373 | kzalloc_node(sizeof(*info->res_offset) * info->res_num, | |
5cd7595d | 374 | GFP_KERNEL, controller->node); |
429ac099 YW |
375 | if (!info->res_offset) |
376 | goto out4; | |
5cd7595d | 377 | |
8a20fd52 LT |
378 | name = kmalloc(16, GFP_KERNEL); |
379 | if (!name) | |
429ac099 | 380 | goto out5; |
1da177e4 | 381 | |
8a20fd52 | 382 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); |
429ac099 YW |
383 | info->bridge = device; |
384 | info->controller = controller; | |
385 | info->name = name; | |
386 | info->res_num = 0; | |
8a20fd52 | 387 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, |
429ac099 | 388 | add_window, info); |
8a20fd52 | 389 | } |
b87e81e5 | 390 | /* |
391 | * See arch/x86/pci/acpi.c. | |
392 | * The desired pci bus might already be scanned in a quirk. We | |
393 | * should handle the case here, but it appears that IA64 hasn't | |
394 | * such quirk. So we just ignore the case now. | |
395 | */ | |
e30f9922 | 396 | pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller, |
429ac099 | 397 | &info->resources); |
e30f9922 | 398 | if (!pbus) { |
429ac099 | 399 | pci_free_resource_list(&info->resources); |
79e77f27 | 400 | return NULL; |
e30f9922 | 401 | } |
1da177e4 | 402 | |
2661b819 | 403 | pci_scan_child_bus(pbus); |
1da177e4 | 404 | return pbus; |
429ac099 YW |
405 | |
406 | out5: | |
407 | kfree(info->res_offset); | |
5cd7595d | 408 | out4: |
429ac099 | 409 | kfree(info->res); |
1da177e4 | 410 | out3: |
429ac099 | 411 | kfree(info); |
1da177e4 LT |
412 | out2: |
413 | kfree(controller); | |
414 | out1: | |
415 | return NULL; | |
416 | } | |
417 | ||
6c0cc950 RW |
418 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
419 | { | |
420 | struct pci_controller *controller = bridge->bus->sysdata; | |
421 | ||
422 | ACPI_HANDLE_SET(&bridge->dev, controller->acpi_handle); | |
423 | return 0; | |
424 | } | |
425 | ||
5b5e76e9 | 426 | static int is_valid_resource(struct pci_dev *dev, int idx) |
71c3511c RS |
427 | { |
428 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
89a74ecc | 429 | struct resource *devr = &dev->resource[idx], *busr; |
71c3511c RS |
430 | |
431 | if (!dev->bus) | |
432 | return 0; | |
71c3511c | 433 | |
89a74ecc | 434 | pci_bus_for_each_resource(dev->bus, busr, i) { |
71c3511c RS |
435 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) |
436 | continue; | |
437 | if ((devr->start) && (devr->start >= busr->start) && | |
438 | (devr->end <= busr->end)) | |
439 | return 1; | |
440 | } | |
441 | return 0; | |
442 | } | |
443 | ||
5b5e76e9 | 444 | static void pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) |
1da177e4 | 445 | { |
1da177e4 | 446 | int i; |
1da177e4 | 447 | |
7b9c8ba2 | 448 | for (i = start; i < limit; i++) { |
1da177e4 LT |
449 | if (!dev->resource[i].flags) |
450 | continue; | |
71c3511c RS |
451 | if ((is_valid_resource(dev, i))) |
452 | pci_claim_resource(dev, i); | |
1da177e4 LT |
453 | } |
454 | } | |
455 | ||
5b5e76e9 | 456 | void pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
457 | { |
458 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
459 | } | |
8ea6091f | 460 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 | 461 | |
5b5e76e9 | 462 | static void pcibios_fixup_bridge_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
463 | { |
464 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
465 | } | |
466 | ||
1da177e4 LT |
467 | /* |
468 | * Called after each bus is probed, but before its children are examined. | |
469 | */ | |
5b5e76e9 | 470 | void pcibios_fixup_bus(struct pci_bus *b) |
1da177e4 LT |
471 | { |
472 | struct pci_dev *dev; | |
473 | ||
f7d473d9 RS |
474 | if (b->self) { |
475 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 476 | pcibios_fixup_bridge_resources(b->self); |
f7d473d9 | 477 | } |
1da177e4 LT |
478 | list_for_each_entry(dev, &b->devices, bus_list) |
479 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 480 | platform_pci_fixup_bus(b); |
1da177e4 LT |
481 | } |
482 | ||
b02a4a19 JL |
483 | void pcibios_add_bus(struct pci_bus *bus) |
484 | { | |
485 | acpi_pci_add_bus(bus); | |
486 | } | |
487 | ||
488 | void pcibios_remove_bus(struct pci_bus *bus) | |
489 | { | |
490 | acpi_pci_remove_bus(bus); | |
491 | } | |
492 | ||
91e86df1 MS |
493 | void pcibios_set_master (struct pci_dev *dev) |
494 | { | |
495 | /* No special bus mastering setup handling */ | |
496 | } | |
497 | ||
1da177e4 LT |
498 | int |
499 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
500 | { | |
501 | int ret; | |
502 | ||
d981f163 | 503 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
504 | if (ret < 0) |
505 | return ret; | |
506 | ||
bba6f6fc EB |
507 | if (!dev->msi_enabled) |
508 | return acpi_pci_irq_enable(dev); | |
509 | return 0; | |
1da177e4 LT |
510 | } |
511 | ||
1da177e4 LT |
512 | void |
513 | pcibios_disable_device (struct pci_dev *dev) | |
514 | { | |
c7f570a5 | 515 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
516 | if (!dev->msi_enabled) |
517 | acpi_pci_irq_disable(dev); | |
1da177e4 | 518 | } |
1da177e4 | 519 | |
b26b2d49 | 520 | resource_size_t |
3b7a17fc | 521 | pcibios_align_resource (void *data, const struct resource *res, |
e31dd6e4 | 522 | resource_size_t size, resource_size_t align) |
1da177e4 | 523 | { |
b26b2d49 | 524 | return res->start; |
1da177e4 LT |
525 | } |
526 | ||
1da177e4 LT |
527 | int |
528 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
529 | enum pci_mmap_state mmap_state, int write_combine) | |
530 | { | |
012b7105 AC |
531 | unsigned long size = vma->vm_end - vma->vm_start; |
532 | pgprot_t prot; | |
533 | ||
1da177e4 LT |
534 | /* |
535 | * I/O space cannot be accessed via normal processor loads and | |
536 | * stores on this platform. | |
537 | */ | |
538 | if (mmap_state == pci_mmap_io) | |
539 | /* | |
540 | * XXX we could relax this for I/O spaces for which ACPI | |
541 | * indicates that the space is 1-to-1 mapped. But at the | |
542 | * moment, we don't support multiple PCI address spaces and | |
543 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
544 | */ | |
545 | return -EINVAL; | |
546 | ||
012b7105 AC |
547 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
548 | return -EINVAL; | |
549 | ||
550 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
551 | vma->vm_page_prot); | |
552 | ||
1da177e4 | 553 | /* |
012b7105 AC |
554 | * If the user requested WC, the kernel uses UC or WC for this region, |
555 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
556 | * use the same attribute the kernel uses. | |
1da177e4 | 557 | */ |
012b7105 AC |
558 | if (write_combine && |
559 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
560 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
561 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
562 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
563 | else | |
012b7105 | 564 | vma->vm_page_prot = prot; |
1da177e4 LT |
565 | |
566 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
567 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
568 | return -EAGAIN; | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | /** | |
574 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
575 | * @bus: bus to get legacy memory base address for | |
576 | * | |
577 | * Find the base of legacy memory for @bus. This is typically the first | |
578 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
579 | * chipsets support legacy I/O and memory routing. Returns the base address | |
580 | * or an error pointer if an error occurred. | |
581 | * | |
582 | * This is the ia64 generic version of this routine. Other platforms | |
583 | * are free to override it with a machine vector. | |
584 | */ | |
585 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
586 | { | |
587 | return (char *)__IA64_UNCACHED_OFFSET; | |
588 | } | |
589 | ||
590 | /** | |
591 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
592 | * @bus: bus whose legacy space we're mapping | |
593 | * @vma: vma passed in by mmap | |
594 | * | |
595 | * Map legacy memory space for this device back to userspace using a machine | |
596 | * vector to get the base address. | |
597 | */ | |
598 | int | |
f19aeb1f BH |
599 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
600 | enum pci_mmap_state mmap_state) | |
1da177e4 | 601 | { |
32e62c63 BH |
602 | unsigned long size = vma->vm_end - vma->vm_start; |
603 | pgprot_t prot; | |
1da177e4 LT |
604 | char *addr; |
605 | ||
f19aeb1f BH |
606 | /* We only support mmap'ing of legacy memory space */ |
607 | if (mmap_state != pci_mmap_mem) | |
608 | return -ENOSYS; | |
609 | ||
32e62c63 BH |
610 | /* |
611 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
612 | * for more details. | |
613 | */ | |
06c67bef | 614 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
615 | return -EINVAL; |
616 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
617 | vma->vm_page_prot); | |
32e62c63 | 618 | |
1da177e4 LT |
619 | addr = pci_get_legacy_mem(bus); |
620 | if (IS_ERR(addr)) | |
621 | return PTR_ERR(addr); | |
622 | ||
623 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 624 | vma->vm_page_prot = prot; |
1da177e4 LT |
625 | |
626 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 627 | size, vma->vm_page_prot)) |
1da177e4 LT |
628 | return -EAGAIN; |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | /** | |
634 | * ia64_pci_legacy_read - read from legacy I/O space | |
635 | * @bus: bus to read | |
636 | * @port: legacy port value | |
637 | * @val: caller allocated storage for returned value | |
638 | * @size: number of bytes to read | |
639 | * | |
640 | * Simply reads @size bytes from @port and puts the result in @val. | |
641 | * | |
642 | * Again, this (and the write routine) are generic versions that can be | |
643 | * overridden by the platform. This is necessary on platforms that don't | |
644 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
645 | */ | |
646 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
647 | { | |
648 | int ret = size; | |
649 | ||
650 | switch (size) { | |
651 | case 1: | |
652 | *val = inb(port); | |
653 | break; | |
654 | case 2: | |
655 | *val = inw(port); | |
656 | break; | |
657 | case 4: | |
658 | *val = inl(port); | |
659 | break; | |
660 | default: | |
661 | ret = -EINVAL; | |
662 | break; | |
663 | } | |
664 | ||
665 | return ret; | |
666 | } | |
667 | ||
668 | /** | |
669 | * ia64_pci_legacy_write - perform a legacy I/O write | |
670 | * @bus: bus pointer | |
671 | * @port: port to write | |
672 | * @val: value to write | |
673 | * @size: number of bytes to write from @val | |
674 | * | |
675 | * Simply writes @size bytes of @val to @port. | |
676 | */ | |
a72391e4 | 677 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 678 | { |
408045af | 679 | int ret = size; |
1da177e4 LT |
680 | |
681 | switch (size) { | |
682 | case 1: | |
683 | outb(val, port); | |
684 | break; | |
685 | case 2: | |
686 | outw(val, port); | |
687 | break; | |
688 | case 4: | |
689 | outl(val, port); | |
690 | break; | |
691 | default: | |
692 | ret = -EINVAL; | |
693 | break; | |
694 | } | |
695 | ||
696 | return ret; | |
697 | } | |
698 | ||
699 | /** | |
3efe2d84 | 700 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
701 | * |
702 | * We want to use the line-size of the outer-most cache. We assume | |
703 | * that this line-size is the same for all CPUs. | |
704 | * | |
705 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 706 | */ |
ac1aa47b | 707 | static void __init set_pci_dfl_cacheline_size(void) |
1da177e4 | 708 | { |
e088a4ad MW |
709 | unsigned long levels, unique_caches; |
710 | long status; | |
1da177e4 | 711 | pal_cache_config_info_t cci; |
1da177e4 LT |
712 | |
713 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
714 | if (status != 0) { | |
3efe2d84 | 715 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 716 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 717 | return; |
1da177e4 LT |
718 | } |
719 | ||
3efe2d84 MW |
720 | status = ia64_pal_cache_config_info(levels - 1, |
721 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 722 | if (status != 0) { |
3efe2d84 | 723 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 724 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 725 | return; |
1da177e4 | 726 | } |
ac1aa47b | 727 | pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
728 | } |
729 | ||
175add19 JK |
730 | u64 ia64_dma_get_required_mask(struct device *dev) |
731 | { | |
732 | u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); | |
733 | u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); | |
734 | u64 mask; | |
735 | ||
736 | if (!high_totalram) { | |
737 | /* convert to mask just covering totalram */ | |
738 | low_totalram = (1 << (fls(low_totalram) - 1)); | |
739 | low_totalram += low_totalram - 1; | |
740 | mask = low_totalram; | |
741 | } else { | |
742 | high_totalram = (1 << (fls(high_totalram) - 1)); | |
743 | high_totalram += high_totalram - 1; | |
744 | mask = (((u64)high_totalram) << 32) + 0xffffffff; | |
745 | } | |
746 | return mask; | |
747 | } | |
748 | EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); | |
749 | ||
750 | u64 dma_get_required_mask(struct device *dev) | |
751 | { | |
752 | return platform_dma_get_required_mask(dev); | |
753 | } | |
754 | EXPORT_SYMBOL_GPL(dma_get_required_mask); | |
755 | ||
3efe2d84 MW |
756 | static int __init pcibios_init(void) |
757 | { | |
ac1aa47b | 758 | set_pci_dfl_cacheline_size(); |
3efe2d84 | 759 | return 0; |
1da177e4 | 760 | } |
3efe2d84 MW |
761 | |
762 | subsys_initcall(pcibios_init); |