Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
1da177e4 | 21 | #include <linux/spinlock.h> |
175add19 | 22 | #include <linux/bootmem.h> |
bd3ff194 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | |
25 | #include <asm/machvec.h> | |
26 | #include <asm/page.h> | |
1da177e4 LT |
27 | #include <asm/io.h> |
28 | #include <asm/sal.h> | |
29 | #include <asm/smp.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/hw_irq.h> | |
32 | ||
1da177e4 LT |
33 | /* |
34 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
35 | * calls are already serialized (via sal_lock), so we don't need another | |
36 | * synchronization mechanism here. | |
37 | */ | |
38 | ||
39 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
40 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
41 | ||
42 | /* SAL 3.2 adds support for extended config space. */ | |
43 | ||
44 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
45 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
46 | ||
b6ce068a | 47 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
48 | int reg, int len, u32 *value) |
49 | { | |
50 | u64 addr, data = 0; | |
51 | int mode, result; | |
52 | ||
53 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
54 | return -EINVAL; | |
55 | ||
56 | if ((seg | reg) <= 255) { | |
57 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
58 | mode = 0; | |
adcd7403 | 59 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
60 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
61 | mode = 1; | |
adcd7403 MW |
62 | } else { |
63 | return -EINVAL; | |
1da177e4 | 64 | } |
adcd7403 | 65 | |
1da177e4 LT |
66 | result = ia64_sal_pci_config_read(addr, mode, len, &data); |
67 | if (result != 0) | |
68 | return -EINVAL; | |
69 | ||
70 | *value = (u32) data; | |
71 | return 0; | |
72 | } | |
73 | ||
b6ce068a | 74 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
75 | int reg, int len, u32 value) |
76 | { | |
77 | u64 addr; | |
78 | int mode, result; | |
79 | ||
80 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
81 | return -EINVAL; | |
82 | ||
83 | if ((seg | reg) <= 255) { | |
84 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
85 | mode = 0; | |
adcd7403 | 86 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
87 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
88 | mode = 1; | |
adcd7403 MW |
89 | } else { |
90 | return -EINVAL; | |
1da177e4 LT |
91 | } |
92 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
93 | if (result != 0) | |
94 | return -EINVAL; | |
95 | return 0; | |
96 | } | |
97 | ||
b6ce068a MW |
98 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
99 | int size, u32 *value) | |
1da177e4 | 100 | { |
b6ce068a | 101 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
102 | devfn, where, size, value); |
103 | } | |
104 | ||
b6ce068a MW |
105 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
106 | int size, u32 value) | |
1da177e4 | 107 | { |
b6ce068a | 108 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
109 | devfn, where, size, value); |
110 | } | |
111 | ||
112 | struct pci_ops pci_root_ops = { | |
113 | .read = pci_read, | |
114 | .write = pci_write, | |
115 | }; | |
116 | ||
1da177e4 LT |
117 | /* Called by ACPI when it finds a new root bus. */ |
118 | ||
5b5e76e9 | 119 | static struct pci_controller *alloc_pci_controller(int seg) |
1da177e4 LT |
120 | { |
121 | struct pci_controller *controller; | |
122 | ||
52fd9108 | 123 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
124 | if (!controller) |
125 | return NULL; | |
126 | ||
1da177e4 | 127 | controller->segment = seg; |
514604c6 | 128 | controller->node = -1; |
1da177e4 LT |
129 | return controller; |
130 | } | |
131 | ||
4f41d5a4 | 132 | struct pci_root_info { |
637b363e | 133 | struct acpi_device *bridge; |
4f41d5a4 | 134 | struct pci_controller *controller; |
e30f9922 | 135 | struct list_head resources; |
4f41d5a4 BH |
136 | char *name; |
137 | }; | |
138 | ||
139 | static unsigned int | |
140 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 141 | { |
4f41d5a4 | 142 | u64 mmio_base; |
1da177e4 LT |
143 | int i; |
144 | ||
4f41d5a4 BH |
145 | if (phys_base == 0) |
146 | return 0; /* legacy I/O port space */ | |
1da177e4 | 147 | |
4f41d5a4 | 148 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 149 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 150 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 151 | io_space[i].sparse == sparse) |
4f41d5a4 | 152 | return i; |
1da177e4 LT |
153 | |
154 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
155 | printk(KERN_ERR "PCI: Too many IO port spaces " |
156 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
157 | return ~0; |
158 | } | |
159 | ||
160 | i = num_io_spaces++; | |
4f41d5a4 | 161 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
162 | io_space[i].sparse = sparse; |
163 | ||
4f41d5a4 BH |
164 | return i; |
165 | } | |
166 | ||
5b5e76e9 GKH |
167 | static u64 add_io_space(struct pci_root_info *info, |
168 | struct acpi_resource_address64 *addr) | |
4f41d5a4 BH |
169 | { |
170 | struct resource *resource; | |
171 | char *name; | |
e088a4ad | 172 | unsigned long base, min, max, base_port; |
4f41d5a4 BH |
173 | unsigned int sparse = 0, space_nr, len; |
174 | ||
175 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
176 | if (!resource) { | |
177 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
178 | info->name); | |
179 | goto out; | |
180 | } | |
181 | ||
182 | len = strlen(info->name) + 32; | |
183 | name = kzalloc(len, GFP_KERNEL); | |
184 | if (!name) { | |
185 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
186 | info->name); | |
187 | goto free_resource; | |
188 | } | |
189 | ||
50eca3eb | 190 | min = addr->minimum; |
4f41d5a4 | 191 | max = min + addr->address_length - 1; |
0897831b | 192 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
193 | sparse = 1; |
194 | ||
50eca3eb | 195 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
196 | if (space_nr == ~0) |
197 | goto free_name; | |
198 | ||
199 | base = __pa(io_space[space_nr].mmio_base); | |
200 | base_port = IO_SPACE_BASE(space_nr); | |
201 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
202 | base_port + min, base_port + max); | |
203 | ||
204 | /* | |
205 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
206 | * mapping is done by the processor (not the bridge), ACPI may not | |
207 | * mark it as sparse. | |
208 | */ | |
209 | if (space_nr == 0) | |
210 | sparse = 1; | |
211 | ||
212 | resource->name = name; | |
213 | resource->flags = IORESOURCE_MEM; | |
214 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
215 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
216 | insert_resource(&iomem_resource, resource); | |
217 | ||
218 | return base_port; | |
219 | ||
220 | free_name: | |
221 | kfree(name); | |
222 | free_resource: | |
223 | kfree(resource); | |
224 | out: | |
225 | return ~0; | |
1da177e4 LT |
226 | } |
227 | ||
5b5e76e9 GKH |
228 | static acpi_status resource_to_window(struct acpi_resource *resource, |
229 | struct acpi_resource_address64 *addr) | |
463eb297 BH |
230 | { |
231 | acpi_status status; | |
232 | ||
233 | /* | |
234 | * We're only interested in _CRS descriptors that are | |
235 | * - address space descriptors for memory or I/O space | |
236 | * - non-zero size | |
237 | * - producers, i.e., the address space is routed downstream, | |
238 | * not consumed by the bridge itself | |
239 | */ | |
240 | status = acpi_resource_to_address64(resource, addr); | |
241 | if (ACPI_SUCCESS(status) && | |
242 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
243 | addr->resource_type == ACPI_IO_RANGE) && | |
244 | addr->address_length && | |
245 | addr->producer_consumer == ACPI_PRODUCER) | |
246 | return AE_OK; | |
247 | ||
248 | return AE_ERROR; | |
249 | } | |
250 | ||
5b5e76e9 | 251 | static acpi_status count_window(struct acpi_resource *resource, void *data) |
1da177e4 LT |
252 | { |
253 | unsigned int *windows = (unsigned int *) data; | |
254 | struct acpi_resource_address64 addr; | |
255 | acpi_status status; | |
256 | ||
463eb297 | 257 | status = resource_to_window(resource, &addr); |
1da177e4 | 258 | if (ACPI_SUCCESS(status)) |
463eb297 | 259 | (*windows)++; |
1da177e4 LT |
260 | |
261 | return AE_OK; | |
262 | } | |
263 | ||
5b5e76e9 | 264 | static acpi_status add_window(struct acpi_resource *res, void *data) |
1da177e4 LT |
265 | { |
266 | struct pci_root_info *info = data; | |
267 | struct pci_window *window; | |
268 | struct acpi_resource_address64 addr; | |
269 | acpi_status status; | |
270 | unsigned long flags, offset = 0; | |
271 | struct resource *root; | |
272 | ||
463eb297 BH |
273 | /* Return AE_OK for non-window resources to keep scanning for more */ |
274 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
275 | if (!ACPI_SUCCESS(status)) |
276 | return AE_OK; | |
277 | ||
1da177e4 LT |
278 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
279 | flags = IORESOURCE_MEM; | |
280 | root = &iomem_resource; | |
50eca3eb | 281 | offset = addr.translation_offset; |
1da177e4 LT |
282 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
283 | flags = IORESOURCE_IO; | |
284 | root = &ioport_resource; | |
4f41d5a4 | 285 | offset = add_io_space(info, &addr); |
1da177e4 LT |
286 | if (offset == ~0) |
287 | return AE_OK; | |
288 | } else | |
289 | return AE_OK; | |
290 | ||
291 | window = &info->controller->window[info->controller->windows++]; | |
292 | window->resource.name = info->name; | |
293 | window->resource.flags = flags; | |
50eca3eb | 294 | window->resource.start = addr.minimum + offset; |
4f41d5a4 | 295 | window->resource.end = window->resource.start + addr.address_length - 1; |
1da177e4 LT |
296 | window->offset = offset; |
297 | ||
298 | if (insert_resource(root, &window->resource)) { | |
c7dabef8 BH |
299 | dev_err(&info->bridge->dev, |
300 | "can't allocate host bridge window %pR\n", | |
637b363e BH |
301 | &window->resource); |
302 | } else { | |
303 | if (offset) | |
c7dabef8 | 304 | dev_info(&info->bridge->dev, "host bridge window %pR " |
637b363e BH |
305 | "(PCI address [%#llx-%#llx])\n", |
306 | &window->resource, | |
307 | window->resource.start - offset, | |
308 | window->resource.end - offset); | |
309 | else | |
310 | dev_info(&info->bridge->dev, | |
c7dabef8 | 311 | "host bridge window %pR\n", |
637b363e | 312 | &window->resource); |
1da177e4 LT |
313 | } |
314 | ||
e30f9922 BH |
315 | /* HP's firmware has a hack to work around a Windows bug. |
316 | * Ignore these tiny memory ranges */ | |
317 | if (!((window->resource.flags & IORESOURCE_MEM) && | |
318 | (window->resource.end - window->resource.start < 16))) | |
10d1cd2b BH |
319 | pci_add_resource_offset(&info->resources, &window->resource, |
320 | window->offset); | |
1da177e4 | 321 | |
e30f9922 | 322 | return AE_OK; |
1da177e4 LT |
323 | } |
324 | ||
5b5e76e9 | 325 | struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) |
1da177e4 | 326 | { |
57283776 BH |
327 | struct acpi_device *device = root->device; |
328 | int domain = root->segment; | |
329 | int bus = root->secondary.start; | |
1da177e4 LT |
330 | struct pci_controller *controller; |
331 | unsigned int windows = 0; | |
e30f9922 | 332 | struct pci_root_info info; |
1da177e4 LT |
333 | struct pci_bus *pbus; |
334 | char *name; | |
514604c6 | 335 | int pxm; |
1da177e4 LT |
336 | |
337 | controller = alloc_pci_controller(domain); | |
338 | if (!controller) | |
339 | goto out1; | |
340 | ||
341 | controller->acpi_handle = device->handle; | |
342 | ||
514604c6 CL |
343 | pxm = acpi_get_pxm(controller->acpi_handle); |
344 | #ifdef CONFIG_NUMA | |
345 | if (pxm >= 0) | |
762834e8 | 346 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
347 | #endif |
348 | ||
e30f9922 | 349 | INIT_LIST_HEAD(&info.resources); |
2661b819 YL |
350 | /* insert busn resource at first */ |
351 | pci_add_resource(&info.resources, &root->secondary); | |
1da177e4 LT |
352 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
353 | &windows); | |
a66aa704 KK |
354 | if (windows) { |
355 | controller->window = | |
da104919 | 356 | kzalloc_node(sizeof(*controller->window) * windows, |
a66aa704 KK |
357 | GFP_KERNEL, controller->node); |
358 | if (!controller->window) | |
359 | goto out2; | |
1da177e4 | 360 | |
8a20fd52 LT |
361 | name = kmalloc(16, GFP_KERNEL); |
362 | if (!name) | |
363 | goto out3; | |
1da177e4 | 364 | |
8a20fd52 | 365 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); |
637b363e | 366 | info.bridge = device; |
8a20fd52 LT |
367 | info.controller = controller; |
368 | info.name = name; | |
369 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
370 | add_window, &info); | |
371 | } | |
b87e81e5 | 372 | /* |
373 | * See arch/x86/pci/acpi.c. | |
374 | * The desired pci bus might already be scanned in a quirk. We | |
375 | * should handle the case here, but it appears that IA64 hasn't | |
376 | * such quirk. So we just ignore the case now. | |
377 | */ | |
e30f9922 BH |
378 | pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller, |
379 | &info.resources); | |
380 | if (!pbus) { | |
381 | pci_free_resource_list(&info.resources); | |
79e77f27 | 382 | return NULL; |
e30f9922 | 383 | } |
1da177e4 | 384 | |
2661b819 | 385 | pci_scan_child_bus(pbus); |
1da177e4 LT |
386 | return pbus; |
387 | ||
388 | out3: | |
389 | kfree(controller->window); | |
390 | out2: | |
391 | kfree(controller); | |
392 | out1: | |
393 | return NULL; | |
394 | } | |
395 | ||
6c0cc950 RW |
396 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
397 | { | |
398 | struct pci_controller *controller = bridge->bus->sysdata; | |
399 | ||
400 | ACPI_HANDLE_SET(&bridge->dev, controller->acpi_handle); | |
401 | return 0; | |
402 | } | |
403 | ||
5b5e76e9 | 404 | static int is_valid_resource(struct pci_dev *dev, int idx) |
71c3511c RS |
405 | { |
406 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
89a74ecc | 407 | struct resource *devr = &dev->resource[idx], *busr; |
71c3511c RS |
408 | |
409 | if (!dev->bus) | |
410 | return 0; | |
71c3511c | 411 | |
89a74ecc | 412 | pci_bus_for_each_resource(dev->bus, busr, i) { |
71c3511c RS |
413 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) |
414 | continue; | |
415 | if ((devr->start) && (devr->start >= busr->start) && | |
416 | (devr->end <= busr->end)) | |
417 | return 1; | |
418 | } | |
419 | return 0; | |
420 | } | |
421 | ||
5b5e76e9 | 422 | static void pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) |
1da177e4 | 423 | { |
1da177e4 | 424 | int i; |
1da177e4 | 425 | |
7b9c8ba2 | 426 | for (i = start; i < limit; i++) { |
1da177e4 LT |
427 | if (!dev->resource[i].flags) |
428 | continue; | |
71c3511c RS |
429 | if ((is_valid_resource(dev, i))) |
430 | pci_claim_resource(dev, i); | |
1da177e4 LT |
431 | } |
432 | } | |
433 | ||
5b5e76e9 | 434 | void pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
435 | { |
436 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
437 | } | |
8ea6091f | 438 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 | 439 | |
5b5e76e9 | 440 | static void pcibios_fixup_bridge_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
441 | { |
442 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
443 | } | |
444 | ||
1da177e4 LT |
445 | /* |
446 | * Called after each bus is probed, but before its children are examined. | |
447 | */ | |
5b5e76e9 | 448 | void pcibios_fixup_bus(struct pci_bus *b) |
1da177e4 LT |
449 | { |
450 | struct pci_dev *dev; | |
451 | ||
f7d473d9 RS |
452 | if (b->self) { |
453 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 454 | pcibios_fixup_bridge_resources(b->self); |
f7d473d9 | 455 | } |
1da177e4 LT |
456 | list_for_each_entry(dev, &b->devices, bus_list) |
457 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 458 | platform_pci_fixup_bus(b); |
1da177e4 LT |
459 | } |
460 | ||
91e86df1 MS |
461 | void pcibios_set_master (struct pci_dev *dev) |
462 | { | |
463 | /* No special bus mastering setup handling */ | |
464 | } | |
465 | ||
1da177e4 LT |
466 | int |
467 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
468 | { | |
469 | int ret; | |
470 | ||
d981f163 | 471 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
472 | if (ret < 0) |
473 | return ret; | |
474 | ||
bba6f6fc EB |
475 | if (!dev->msi_enabled) |
476 | return acpi_pci_irq_enable(dev); | |
477 | return 0; | |
1da177e4 LT |
478 | } |
479 | ||
1da177e4 LT |
480 | void |
481 | pcibios_disable_device (struct pci_dev *dev) | |
482 | { | |
c7f570a5 | 483 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
484 | if (!dev->msi_enabled) |
485 | acpi_pci_irq_disable(dev); | |
1da177e4 | 486 | } |
1da177e4 | 487 | |
b26b2d49 | 488 | resource_size_t |
3b7a17fc | 489 | pcibios_align_resource (void *data, const struct resource *res, |
e31dd6e4 | 490 | resource_size_t size, resource_size_t align) |
1da177e4 | 491 | { |
b26b2d49 | 492 | return res->start; |
1da177e4 LT |
493 | } |
494 | ||
1da177e4 LT |
495 | int |
496 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
497 | enum pci_mmap_state mmap_state, int write_combine) | |
498 | { | |
012b7105 AC |
499 | unsigned long size = vma->vm_end - vma->vm_start; |
500 | pgprot_t prot; | |
501 | ||
1da177e4 LT |
502 | /* |
503 | * I/O space cannot be accessed via normal processor loads and | |
504 | * stores on this platform. | |
505 | */ | |
506 | if (mmap_state == pci_mmap_io) | |
507 | /* | |
508 | * XXX we could relax this for I/O spaces for which ACPI | |
509 | * indicates that the space is 1-to-1 mapped. But at the | |
510 | * moment, we don't support multiple PCI address spaces and | |
511 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
512 | */ | |
513 | return -EINVAL; | |
514 | ||
012b7105 AC |
515 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
516 | return -EINVAL; | |
517 | ||
518 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
519 | vma->vm_page_prot); | |
520 | ||
1da177e4 | 521 | /* |
012b7105 AC |
522 | * If the user requested WC, the kernel uses UC or WC for this region, |
523 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
524 | * use the same attribute the kernel uses. | |
1da177e4 | 525 | */ |
012b7105 AC |
526 | if (write_combine && |
527 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
528 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
529 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
530 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
531 | else | |
012b7105 | 532 | vma->vm_page_prot = prot; |
1da177e4 LT |
533 | |
534 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
535 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
536 | return -EAGAIN; | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | /** | |
542 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
543 | * @bus: bus to get legacy memory base address for | |
544 | * | |
545 | * Find the base of legacy memory for @bus. This is typically the first | |
546 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
547 | * chipsets support legacy I/O and memory routing. Returns the base address | |
548 | * or an error pointer if an error occurred. | |
549 | * | |
550 | * This is the ia64 generic version of this routine. Other platforms | |
551 | * are free to override it with a machine vector. | |
552 | */ | |
553 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
554 | { | |
555 | return (char *)__IA64_UNCACHED_OFFSET; | |
556 | } | |
557 | ||
558 | /** | |
559 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
560 | * @bus: bus whose legacy space we're mapping | |
561 | * @vma: vma passed in by mmap | |
562 | * | |
563 | * Map legacy memory space for this device back to userspace using a machine | |
564 | * vector to get the base address. | |
565 | */ | |
566 | int | |
f19aeb1f BH |
567 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
568 | enum pci_mmap_state mmap_state) | |
1da177e4 | 569 | { |
32e62c63 BH |
570 | unsigned long size = vma->vm_end - vma->vm_start; |
571 | pgprot_t prot; | |
1da177e4 LT |
572 | char *addr; |
573 | ||
f19aeb1f BH |
574 | /* We only support mmap'ing of legacy memory space */ |
575 | if (mmap_state != pci_mmap_mem) | |
576 | return -ENOSYS; | |
577 | ||
32e62c63 BH |
578 | /* |
579 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
580 | * for more details. | |
581 | */ | |
06c67bef | 582 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
583 | return -EINVAL; |
584 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
585 | vma->vm_page_prot); | |
32e62c63 | 586 | |
1da177e4 LT |
587 | addr = pci_get_legacy_mem(bus); |
588 | if (IS_ERR(addr)) | |
589 | return PTR_ERR(addr); | |
590 | ||
591 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 592 | vma->vm_page_prot = prot; |
1da177e4 LT |
593 | |
594 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 595 | size, vma->vm_page_prot)) |
1da177e4 LT |
596 | return -EAGAIN; |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /** | |
602 | * ia64_pci_legacy_read - read from legacy I/O space | |
603 | * @bus: bus to read | |
604 | * @port: legacy port value | |
605 | * @val: caller allocated storage for returned value | |
606 | * @size: number of bytes to read | |
607 | * | |
608 | * Simply reads @size bytes from @port and puts the result in @val. | |
609 | * | |
610 | * Again, this (and the write routine) are generic versions that can be | |
611 | * overridden by the platform. This is necessary on platforms that don't | |
612 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
613 | */ | |
614 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
615 | { | |
616 | int ret = size; | |
617 | ||
618 | switch (size) { | |
619 | case 1: | |
620 | *val = inb(port); | |
621 | break; | |
622 | case 2: | |
623 | *val = inw(port); | |
624 | break; | |
625 | case 4: | |
626 | *val = inl(port); | |
627 | break; | |
628 | default: | |
629 | ret = -EINVAL; | |
630 | break; | |
631 | } | |
632 | ||
633 | return ret; | |
634 | } | |
635 | ||
636 | /** | |
637 | * ia64_pci_legacy_write - perform a legacy I/O write | |
638 | * @bus: bus pointer | |
639 | * @port: port to write | |
640 | * @val: value to write | |
641 | * @size: number of bytes to write from @val | |
642 | * | |
643 | * Simply writes @size bytes of @val to @port. | |
644 | */ | |
a72391e4 | 645 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 646 | { |
408045af | 647 | int ret = size; |
1da177e4 LT |
648 | |
649 | switch (size) { | |
650 | case 1: | |
651 | outb(val, port); | |
652 | break; | |
653 | case 2: | |
654 | outw(val, port); | |
655 | break; | |
656 | case 4: | |
657 | outl(val, port); | |
658 | break; | |
659 | default: | |
660 | ret = -EINVAL; | |
661 | break; | |
662 | } | |
663 | ||
664 | return ret; | |
665 | } | |
666 | ||
667 | /** | |
3efe2d84 | 668 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
669 | * |
670 | * We want to use the line-size of the outer-most cache. We assume | |
671 | * that this line-size is the same for all CPUs. | |
672 | * | |
673 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 674 | */ |
ac1aa47b | 675 | static void __init set_pci_dfl_cacheline_size(void) |
1da177e4 | 676 | { |
e088a4ad MW |
677 | unsigned long levels, unique_caches; |
678 | long status; | |
1da177e4 | 679 | pal_cache_config_info_t cci; |
1da177e4 LT |
680 | |
681 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
682 | if (status != 0) { | |
3efe2d84 | 683 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 684 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 685 | return; |
1da177e4 LT |
686 | } |
687 | ||
3efe2d84 MW |
688 | status = ia64_pal_cache_config_info(levels - 1, |
689 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 690 | if (status != 0) { |
3efe2d84 | 691 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 692 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 693 | return; |
1da177e4 | 694 | } |
ac1aa47b | 695 | pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
696 | } |
697 | ||
175add19 JK |
698 | u64 ia64_dma_get_required_mask(struct device *dev) |
699 | { | |
700 | u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); | |
701 | u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); | |
702 | u64 mask; | |
703 | ||
704 | if (!high_totalram) { | |
705 | /* convert to mask just covering totalram */ | |
706 | low_totalram = (1 << (fls(low_totalram) - 1)); | |
707 | low_totalram += low_totalram - 1; | |
708 | mask = low_totalram; | |
709 | } else { | |
710 | high_totalram = (1 << (fls(high_totalram) - 1)); | |
711 | high_totalram += high_totalram - 1; | |
712 | mask = (((u64)high_totalram) << 32) + 0xffffffff; | |
713 | } | |
714 | return mask; | |
715 | } | |
716 | EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); | |
717 | ||
718 | u64 dma_get_required_mask(struct device *dev) | |
719 | { | |
720 | return platform_dma_get_required_mask(dev); | |
721 | } | |
722 | EXPORT_SYMBOL_GPL(dma_get_required_mask); | |
723 | ||
3efe2d84 MW |
724 | static int __init pcibios_init(void) |
725 | { | |
ac1aa47b | 726 | set_pci_dfl_cacheline_size(); |
3efe2d84 | 727 | return 0; |
1da177e4 | 728 | } |
3efe2d84 MW |
729 | |
730 | subsys_initcall(pcibios_init); |