Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
1da177e4 | 21 | #include <linux/spinlock.h> |
175add19 | 22 | #include <linux/bootmem.h> |
bd3ff194 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | |
25 | #include <asm/machvec.h> | |
26 | #include <asm/page.h> | |
1da177e4 LT |
27 | #include <asm/system.h> |
28 | #include <asm/io.h> | |
29 | #include <asm/sal.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/hw_irq.h> | |
33 | ||
1da177e4 LT |
34 | /* |
35 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
36 | * calls are already serialized (via sal_lock), so we don't need another | |
37 | * synchronization mechanism here. | |
38 | */ | |
39 | ||
40 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
41 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
42 | ||
43 | /* SAL 3.2 adds support for extended config space. */ | |
44 | ||
45 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
46 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
47 | ||
b6ce068a | 48 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
49 | int reg, int len, u32 *value) |
50 | { | |
51 | u64 addr, data = 0; | |
52 | int mode, result; | |
53 | ||
54 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
55 | return -EINVAL; | |
56 | ||
57 | if ((seg | reg) <= 255) { | |
58 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
59 | mode = 0; | |
adcd7403 | 60 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
61 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
62 | mode = 1; | |
adcd7403 MW |
63 | } else { |
64 | return -EINVAL; | |
1da177e4 | 65 | } |
adcd7403 | 66 | |
1da177e4 LT |
67 | result = ia64_sal_pci_config_read(addr, mode, len, &data); |
68 | if (result != 0) | |
69 | return -EINVAL; | |
70 | ||
71 | *value = (u32) data; | |
72 | return 0; | |
73 | } | |
74 | ||
b6ce068a | 75 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
76 | int reg, int len, u32 value) |
77 | { | |
78 | u64 addr; | |
79 | int mode, result; | |
80 | ||
81 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
82 | return -EINVAL; | |
83 | ||
84 | if ((seg | reg) <= 255) { | |
85 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
86 | mode = 0; | |
adcd7403 | 87 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
88 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
89 | mode = 1; | |
adcd7403 MW |
90 | } else { |
91 | return -EINVAL; | |
1da177e4 LT |
92 | } |
93 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
94 | if (result != 0) | |
95 | return -EINVAL; | |
96 | return 0; | |
97 | } | |
98 | ||
b6ce068a MW |
99 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
100 | int size, u32 *value) | |
1da177e4 | 101 | { |
b6ce068a | 102 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
103 | devfn, where, size, value); |
104 | } | |
105 | ||
b6ce068a MW |
106 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
107 | int size, u32 value) | |
1da177e4 | 108 | { |
b6ce068a | 109 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
110 | devfn, where, size, value); |
111 | } | |
112 | ||
113 | struct pci_ops pci_root_ops = { | |
114 | .read = pci_read, | |
115 | .write = pci_write, | |
116 | }; | |
117 | ||
1da177e4 LT |
118 | /* Called by ACPI when it finds a new root bus. */ |
119 | ||
120 | static struct pci_controller * __devinit | |
121 | alloc_pci_controller (int seg) | |
122 | { | |
123 | struct pci_controller *controller; | |
124 | ||
52fd9108 | 125 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
126 | if (!controller) |
127 | return NULL; | |
128 | ||
1da177e4 | 129 | controller->segment = seg; |
514604c6 | 130 | controller->node = -1; |
1da177e4 LT |
131 | return controller; |
132 | } | |
133 | ||
4f41d5a4 | 134 | struct pci_root_info { |
637b363e | 135 | struct acpi_device *bridge; |
4f41d5a4 BH |
136 | struct pci_controller *controller; |
137 | char *name; | |
138 | }; | |
139 | ||
140 | static unsigned int | |
141 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 142 | { |
4f41d5a4 | 143 | u64 mmio_base; |
1da177e4 LT |
144 | int i; |
145 | ||
4f41d5a4 BH |
146 | if (phys_base == 0) |
147 | return 0; /* legacy I/O port space */ | |
1da177e4 | 148 | |
4f41d5a4 | 149 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 150 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 151 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 152 | io_space[i].sparse == sparse) |
4f41d5a4 | 153 | return i; |
1da177e4 LT |
154 | |
155 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
156 | printk(KERN_ERR "PCI: Too many IO port spaces " |
157 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
158 | return ~0; |
159 | } | |
160 | ||
161 | i = num_io_spaces++; | |
4f41d5a4 | 162 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
163 | io_space[i].sparse = sparse; |
164 | ||
4f41d5a4 BH |
165 | return i; |
166 | } | |
167 | ||
168 | static u64 __devinit | |
169 | add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) | |
170 | { | |
171 | struct resource *resource; | |
172 | char *name; | |
e088a4ad | 173 | unsigned long base, min, max, base_port; |
4f41d5a4 BH |
174 | unsigned int sparse = 0, space_nr, len; |
175 | ||
176 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
177 | if (!resource) { | |
178 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
179 | info->name); | |
180 | goto out; | |
181 | } | |
182 | ||
183 | len = strlen(info->name) + 32; | |
184 | name = kzalloc(len, GFP_KERNEL); | |
185 | if (!name) { | |
186 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
187 | info->name); | |
188 | goto free_resource; | |
189 | } | |
190 | ||
50eca3eb | 191 | min = addr->minimum; |
4f41d5a4 | 192 | max = min + addr->address_length - 1; |
0897831b | 193 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
194 | sparse = 1; |
195 | ||
50eca3eb | 196 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
197 | if (space_nr == ~0) |
198 | goto free_name; | |
199 | ||
200 | base = __pa(io_space[space_nr].mmio_base); | |
201 | base_port = IO_SPACE_BASE(space_nr); | |
202 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
203 | base_port + min, base_port + max); | |
204 | ||
205 | /* | |
206 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
207 | * mapping is done by the processor (not the bridge), ACPI may not | |
208 | * mark it as sparse. | |
209 | */ | |
210 | if (space_nr == 0) | |
211 | sparse = 1; | |
212 | ||
213 | resource->name = name; | |
214 | resource->flags = IORESOURCE_MEM; | |
215 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
216 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
217 | insert_resource(&iomem_resource, resource); | |
218 | ||
219 | return base_port; | |
220 | ||
221 | free_name: | |
222 | kfree(name); | |
223 | free_resource: | |
224 | kfree(resource); | |
225 | out: | |
226 | return ~0; | |
1da177e4 LT |
227 | } |
228 | ||
463eb297 BH |
229 | static acpi_status __devinit resource_to_window(struct acpi_resource *resource, |
230 | struct acpi_resource_address64 *addr) | |
231 | { | |
232 | acpi_status status; | |
233 | ||
234 | /* | |
235 | * We're only interested in _CRS descriptors that are | |
236 | * - address space descriptors for memory or I/O space | |
237 | * - non-zero size | |
238 | * - producers, i.e., the address space is routed downstream, | |
239 | * not consumed by the bridge itself | |
240 | */ | |
241 | status = acpi_resource_to_address64(resource, addr); | |
242 | if (ACPI_SUCCESS(status) && | |
243 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
244 | addr->resource_type == ACPI_IO_RANGE) && | |
245 | addr->address_length && | |
246 | addr->producer_consumer == ACPI_PRODUCER) | |
247 | return AE_OK; | |
248 | ||
249 | return AE_ERROR; | |
250 | } | |
251 | ||
1da177e4 LT |
252 | static acpi_status __devinit |
253 | count_window (struct acpi_resource *resource, void *data) | |
254 | { | |
255 | unsigned int *windows = (unsigned int *) data; | |
256 | struct acpi_resource_address64 addr; | |
257 | acpi_status status; | |
258 | ||
463eb297 | 259 | status = resource_to_window(resource, &addr); |
1da177e4 | 260 | if (ACPI_SUCCESS(status)) |
463eb297 | 261 | (*windows)++; |
1da177e4 LT |
262 | |
263 | return AE_OK; | |
264 | } | |
265 | ||
1da177e4 LT |
266 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) |
267 | { | |
268 | struct pci_root_info *info = data; | |
269 | struct pci_window *window; | |
270 | struct acpi_resource_address64 addr; | |
271 | acpi_status status; | |
272 | unsigned long flags, offset = 0; | |
273 | struct resource *root; | |
274 | ||
463eb297 BH |
275 | /* Return AE_OK for non-window resources to keep scanning for more */ |
276 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
277 | if (!ACPI_SUCCESS(status)) |
278 | return AE_OK; | |
279 | ||
1da177e4 LT |
280 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
281 | flags = IORESOURCE_MEM; | |
282 | root = &iomem_resource; | |
50eca3eb | 283 | offset = addr.translation_offset; |
1da177e4 LT |
284 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
285 | flags = IORESOURCE_IO; | |
286 | root = &ioport_resource; | |
4f41d5a4 | 287 | offset = add_io_space(info, &addr); |
1da177e4 LT |
288 | if (offset == ~0) |
289 | return AE_OK; | |
290 | } else | |
291 | return AE_OK; | |
292 | ||
293 | window = &info->controller->window[info->controller->windows++]; | |
294 | window->resource.name = info->name; | |
295 | window->resource.flags = flags; | |
50eca3eb | 296 | window->resource.start = addr.minimum + offset; |
4f41d5a4 | 297 | window->resource.end = window->resource.start + addr.address_length - 1; |
1da177e4 LT |
298 | window->resource.child = NULL; |
299 | window->offset = offset; | |
300 | ||
301 | if (insert_resource(root, &window->resource)) { | |
c7dabef8 BH |
302 | dev_err(&info->bridge->dev, |
303 | "can't allocate host bridge window %pR\n", | |
637b363e BH |
304 | &window->resource); |
305 | } else { | |
306 | if (offset) | |
c7dabef8 | 307 | dev_info(&info->bridge->dev, "host bridge window %pR " |
637b363e BH |
308 | "(PCI address [%#llx-%#llx])\n", |
309 | &window->resource, | |
310 | window->resource.start - offset, | |
311 | window->resource.end - offset); | |
312 | else | |
313 | dev_info(&info->bridge->dev, | |
c7dabef8 | 314 | "host bridge window %pR\n", |
637b363e | 315 | &window->resource); |
1da177e4 LT |
316 | } |
317 | ||
318 | return AE_OK; | |
319 | } | |
320 | ||
321 | static void __devinit | |
322 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
323 | { | |
2fe2abf8 | 324 | int i; |
1da177e4 | 325 | |
2fe2abf8 | 326 | pci_bus_remove_resources(bus); |
1da177e4 LT |
327 | for (i = 0; i < ctrl->windows; i++) { |
328 | struct resource *res = &ctrl->window[i].resource; | |
329 | /* HP's firmware has a hack to work around a Windows bug. | |
330 | * Ignore these tiny memory ranges */ | |
331 | if ((res->flags & IORESOURCE_MEM) && | |
332 | (res->end - res->start < 16)) | |
333 | continue; | |
2fe2abf8 | 334 | pci_bus_add_resource(bus, res, 0); |
1da177e4 LT |
335 | } |
336 | } | |
337 | ||
338 | struct pci_bus * __devinit | |
57283776 | 339 | pci_acpi_scan_root(struct acpi_pci_root *root) |
1da177e4 | 340 | { |
57283776 BH |
341 | struct acpi_device *device = root->device; |
342 | int domain = root->segment; | |
343 | int bus = root->secondary.start; | |
1da177e4 LT |
344 | struct pci_controller *controller; |
345 | unsigned int windows = 0; | |
346 | struct pci_bus *pbus; | |
347 | char *name; | |
514604c6 | 348 | int pxm; |
1da177e4 LT |
349 | |
350 | controller = alloc_pci_controller(domain); | |
351 | if (!controller) | |
352 | goto out1; | |
353 | ||
354 | controller->acpi_handle = device->handle; | |
355 | ||
514604c6 CL |
356 | pxm = acpi_get_pxm(controller->acpi_handle); |
357 | #ifdef CONFIG_NUMA | |
358 | if (pxm >= 0) | |
762834e8 | 359 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
360 | #endif |
361 | ||
1da177e4 LT |
362 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
363 | &windows); | |
a66aa704 | 364 | if (windows) { |
8a20fd52 LT |
365 | struct pci_root_info info; |
366 | ||
a66aa704 KK |
367 | controller->window = |
368 | kmalloc_node(sizeof(*controller->window) * windows, | |
369 | GFP_KERNEL, controller->node); | |
370 | if (!controller->window) | |
371 | goto out2; | |
1da177e4 | 372 | |
8a20fd52 LT |
373 | name = kmalloc(16, GFP_KERNEL); |
374 | if (!name) | |
375 | goto out3; | |
1da177e4 | 376 | |
8a20fd52 | 377 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); |
637b363e | 378 | info.bridge = device; |
8a20fd52 LT |
379 | info.controller = controller; |
380 | info.name = name; | |
381 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
382 | add_window, &info); | |
383 | } | |
b87e81e5 | 384 | /* |
385 | * See arch/x86/pci/acpi.c. | |
386 | * The desired pci bus might already be scanned in a quirk. We | |
387 | * should handle the case here, but it appears that IA64 hasn't | |
388 | * such quirk. So we just ignore the case now. | |
389 | */ | |
79e77f27 BH |
390 | pbus = pci_create_bus(NULL, bus, &pci_root_ops, controller); |
391 | if (!pbus) | |
392 | return NULL; | |
1da177e4 | 393 | |
79e77f27 | 394 | pbus->subordinate = pci_scan_child_bus(pbus); |
1da177e4 LT |
395 | return pbus; |
396 | ||
397 | out3: | |
398 | kfree(controller->window); | |
399 | out2: | |
400 | kfree(controller); | |
401 | out1: | |
402 | return NULL; | |
403 | } | |
404 | ||
405 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
406 | struct pci_bus_region *region, struct resource *res) | |
407 | { | |
408 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
409 | unsigned long offset = 0; | |
410 | int i; | |
411 | ||
412 | for (i = 0; i < controller->windows; i++) { | |
413 | struct pci_window *window = &controller->window[i]; | |
414 | if (!(window->resource.flags & res->flags)) | |
415 | continue; | |
416 | if (window->resource.start > res->start) | |
417 | continue; | |
418 | if (window->resource.end < res->end) | |
419 | continue; | |
420 | offset = window->offset; | |
421 | break; | |
422 | } | |
423 | ||
424 | region->start = res->start - offset; | |
425 | region->end = res->end - offset; | |
426 | } | |
427 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
428 | ||
429 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
430 | struct resource *res, struct pci_bus_region *region) | |
431 | { | |
432 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
433 | unsigned long offset = 0; | |
434 | int i; | |
435 | ||
436 | for (i = 0; i < controller->windows; i++) { | |
437 | struct pci_window *window = &controller->window[i]; | |
438 | if (!(window->resource.flags & res->flags)) | |
439 | continue; | |
440 | if (window->resource.start - window->offset > region->start) | |
441 | continue; | |
442 | if (window->resource.end - window->offset < region->end) | |
443 | continue; | |
444 | offset = window->offset; | |
445 | break; | |
446 | } | |
447 | ||
448 | res->start = region->start + offset; | |
449 | res->end = region->end + offset; | |
450 | } | |
41290c14 | 451 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 452 | |
71c3511c RS |
453 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
454 | { | |
455 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
89a74ecc | 456 | struct resource *devr = &dev->resource[idx], *busr; |
71c3511c RS |
457 | |
458 | if (!dev->bus) | |
459 | return 0; | |
71c3511c | 460 | |
89a74ecc | 461 | pci_bus_for_each_resource(dev->bus, busr, i) { |
71c3511c RS |
462 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) |
463 | continue; | |
464 | if ((devr->start) && (devr->start >= busr->start) && | |
465 | (devr->end <= busr->end)) | |
466 | return 1; | |
467 | } | |
468 | return 0; | |
469 | } | |
470 | ||
7b9c8ba2 KK |
471 | static void __devinit |
472 | pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) | |
1da177e4 LT |
473 | { |
474 | struct pci_bus_region region; | |
475 | int i; | |
1da177e4 | 476 | |
7b9c8ba2 | 477 | for (i = start; i < limit; i++) { |
1da177e4 LT |
478 | if (!dev->resource[i].flags) |
479 | continue; | |
480 | region.start = dev->resource[i].start; | |
481 | region.end = dev->resource[i].end; | |
482 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
483 | if ((is_valid_resource(dev, i))) |
484 | pci_claim_resource(dev, i); | |
1da177e4 LT |
485 | } |
486 | } | |
487 | ||
8ea6091f | 488 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
489 | { |
490 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
491 | } | |
8ea6091f | 492 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 KK |
493 | |
494 | static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) | |
495 | { | |
496 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
497 | } | |
498 | ||
1da177e4 LT |
499 | /* |
500 | * Called after each bus is probed, but before its children are examined. | |
501 | */ | |
502 | void __devinit | |
503 | pcibios_fixup_bus (struct pci_bus *b) | |
504 | { | |
505 | struct pci_dev *dev; | |
506 | ||
f7d473d9 RS |
507 | if (b->self) { |
508 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 509 | pcibios_fixup_bridge_resources(b->self); |
1d89b30c MW |
510 | } else { |
511 | pcibios_setup_root_windows(b, b->sysdata); | |
f7d473d9 | 512 | } |
1da177e4 LT |
513 | list_for_each_entry(dev, &b->devices, bus_list) |
514 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 515 | platform_pci_fixup_bus(b); |
1da177e4 LT |
516 | |
517 | return; | |
518 | } | |
519 | ||
91e86df1 MS |
520 | void pcibios_set_master (struct pci_dev *dev) |
521 | { | |
522 | /* No special bus mastering setup handling */ | |
523 | } | |
524 | ||
1da177e4 LT |
525 | void __devinit |
526 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
527 | { | |
528 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
529 | ||
530 | /* ??? FIXME -- record old value for shutdown. */ | |
531 | } | |
532 | ||
1da177e4 LT |
533 | int |
534 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
535 | { | |
536 | int ret; | |
537 | ||
d981f163 | 538 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
539 | if (ret < 0) |
540 | return ret; | |
541 | ||
bba6f6fc EB |
542 | if (!dev->msi_enabled) |
543 | return acpi_pci_irq_enable(dev); | |
544 | return 0; | |
1da177e4 LT |
545 | } |
546 | ||
1da177e4 LT |
547 | void |
548 | pcibios_disable_device (struct pci_dev *dev) | |
549 | { | |
c7f570a5 | 550 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
551 | if (!dev->msi_enabled) |
552 | acpi_pci_irq_disable(dev); | |
1da177e4 | 553 | } |
1da177e4 | 554 | |
b26b2d49 | 555 | resource_size_t |
3b7a17fc | 556 | pcibios_align_resource (void *data, const struct resource *res, |
e31dd6e4 | 557 | resource_size_t size, resource_size_t align) |
1da177e4 | 558 | { |
b26b2d49 | 559 | return res->start; |
1da177e4 LT |
560 | } |
561 | ||
562 | /* | |
563 | * PCI BIOS setup, always defaults to SAL interface | |
564 | */ | |
944c54e7 | 565 | char * __init |
1da177e4 LT |
566 | pcibios_setup (char *str) |
567 | { | |
ac311ac2 | 568 | return str; |
1da177e4 LT |
569 | } |
570 | ||
571 | int | |
572 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
573 | enum pci_mmap_state mmap_state, int write_combine) | |
574 | { | |
012b7105 AC |
575 | unsigned long size = vma->vm_end - vma->vm_start; |
576 | pgprot_t prot; | |
577 | ||
1da177e4 LT |
578 | /* |
579 | * I/O space cannot be accessed via normal processor loads and | |
580 | * stores on this platform. | |
581 | */ | |
582 | if (mmap_state == pci_mmap_io) | |
583 | /* | |
584 | * XXX we could relax this for I/O spaces for which ACPI | |
585 | * indicates that the space is 1-to-1 mapped. But at the | |
586 | * moment, we don't support multiple PCI address spaces and | |
587 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
588 | */ | |
589 | return -EINVAL; | |
590 | ||
012b7105 AC |
591 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
592 | return -EINVAL; | |
593 | ||
594 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
595 | vma->vm_page_prot); | |
596 | ||
1da177e4 | 597 | /* |
012b7105 AC |
598 | * If the user requested WC, the kernel uses UC or WC for this region, |
599 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
600 | * use the same attribute the kernel uses. | |
1da177e4 | 601 | */ |
012b7105 AC |
602 | if (write_combine && |
603 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
604 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
605 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
606 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
607 | else | |
012b7105 | 608 | vma->vm_page_prot = prot; |
1da177e4 LT |
609 | |
610 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
611 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
612 | return -EAGAIN; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | /** | |
618 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
619 | * @bus: bus to get legacy memory base address for | |
620 | * | |
621 | * Find the base of legacy memory for @bus. This is typically the first | |
622 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
623 | * chipsets support legacy I/O and memory routing. Returns the base address | |
624 | * or an error pointer if an error occurred. | |
625 | * | |
626 | * This is the ia64 generic version of this routine. Other platforms | |
627 | * are free to override it with a machine vector. | |
628 | */ | |
629 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
630 | { | |
631 | return (char *)__IA64_UNCACHED_OFFSET; | |
632 | } | |
633 | ||
634 | /** | |
635 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
636 | * @bus: bus whose legacy space we're mapping | |
637 | * @vma: vma passed in by mmap | |
638 | * | |
639 | * Map legacy memory space for this device back to userspace using a machine | |
640 | * vector to get the base address. | |
641 | */ | |
642 | int | |
f19aeb1f BH |
643 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
644 | enum pci_mmap_state mmap_state) | |
1da177e4 | 645 | { |
32e62c63 BH |
646 | unsigned long size = vma->vm_end - vma->vm_start; |
647 | pgprot_t prot; | |
1da177e4 LT |
648 | char *addr; |
649 | ||
f19aeb1f BH |
650 | /* We only support mmap'ing of legacy memory space */ |
651 | if (mmap_state != pci_mmap_mem) | |
652 | return -ENOSYS; | |
653 | ||
32e62c63 BH |
654 | /* |
655 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
656 | * for more details. | |
657 | */ | |
06c67bef | 658 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
659 | return -EINVAL; |
660 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
661 | vma->vm_page_prot); | |
32e62c63 | 662 | |
1da177e4 LT |
663 | addr = pci_get_legacy_mem(bus); |
664 | if (IS_ERR(addr)) | |
665 | return PTR_ERR(addr); | |
666 | ||
667 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 668 | vma->vm_page_prot = prot; |
1da177e4 LT |
669 | |
670 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 671 | size, vma->vm_page_prot)) |
1da177e4 LT |
672 | return -EAGAIN; |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | /** | |
678 | * ia64_pci_legacy_read - read from legacy I/O space | |
679 | * @bus: bus to read | |
680 | * @port: legacy port value | |
681 | * @val: caller allocated storage for returned value | |
682 | * @size: number of bytes to read | |
683 | * | |
684 | * Simply reads @size bytes from @port and puts the result in @val. | |
685 | * | |
686 | * Again, this (and the write routine) are generic versions that can be | |
687 | * overridden by the platform. This is necessary on platforms that don't | |
688 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
689 | */ | |
690 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
691 | { | |
692 | int ret = size; | |
693 | ||
694 | switch (size) { | |
695 | case 1: | |
696 | *val = inb(port); | |
697 | break; | |
698 | case 2: | |
699 | *val = inw(port); | |
700 | break; | |
701 | case 4: | |
702 | *val = inl(port); | |
703 | break; | |
704 | default: | |
705 | ret = -EINVAL; | |
706 | break; | |
707 | } | |
708 | ||
709 | return ret; | |
710 | } | |
711 | ||
712 | /** | |
713 | * ia64_pci_legacy_write - perform a legacy I/O write | |
714 | * @bus: bus pointer | |
715 | * @port: port to write | |
716 | * @val: value to write | |
717 | * @size: number of bytes to write from @val | |
718 | * | |
719 | * Simply writes @size bytes of @val to @port. | |
720 | */ | |
a72391e4 | 721 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 722 | { |
408045af | 723 | int ret = size; |
1da177e4 LT |
724 | |
725 | switch (size) { | |
726 | case 1: | |
727 | outb(val, port); | |
728 | break; | |
729 | case 2: | |
730 | outw(val, port); | |
731 | break; | |
732 | case 4: | |
733 | outl(val, port); | |
734 | break; | |
735 | default: | |
736 | ret = -EINVAL; | |
737 | break; | |
738 | } | |
739 | ||
740 | return ret; | |
741 | } | |
742 | ||
743 | /** | |
3efe2d84 | 744 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
745 | * |
746 | * We want to use the line-size of the outer-most cache. We assume | |
747 | * that this line-size is the same for all CPUs. | |
748 | * | |
749 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 750 | */ |
ac1aa47b | 751 | static void __init set_pci_dfl_cacheline_size(void) |
1da177e4 | 752 | { |
e088a4ad MW |
753 | unsigned long levels, unique_caches; |
754 | long status; | |
1da177e4 | 755 | pal_cache_config_info_t cci; |
1da177e4 LT |
756 | |
757 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
758 | if (status != 0) { | |
3efe2d84 | 759 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 760 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 761 | return; |
1da177e4 LT |
762 | } |
763 | ||
3efe2d84 MW |
764 | status = ia64_pal_cache_config_info(levels - 1, |
765 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 766 | if (status != 0) { |
3efe2d84 | 767 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 768 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 769 | return; |
1da177e4 | 770 | } |
ac1aa47b | 771 | pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
772 | } |
773 | ||
175add19 JK |
774 | u64 ia64_dma_get_required_mask(struct device *dev) |
775 | { | |
776 | u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); | |
777 | u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); | |
778 | u64 mask; | |
779 | ||
780 | if (!high_totalram) { | |
781 | /* convert to mask just covering totalram */ | |
782 | low_totalram = (1 << (fls(low_totalram) - 1)); | |
783 | low_totalram += low_totalram - 1; | |
784 | mask = low_totalram; | |
785 | } else { | |
786 | high_totalram = (1 << (fls(high_totalram) - 1)); | |
787 | high_totalram += high_totalram - 1; | |
788 | mask = (((u64)high_totalram) << 32) + 0xffffffff; | |
789 | } | |
790 | return mask; | |
791 | } | |
792 | EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); | |
793 | ||
794 | u64 dma_get_required_mask(struct device *dev) | |
795 | { | |
796 | return platform_dma_get_required_mask(dev); | |
797 | } | |
798 | EXPORT_SYMBOL_GPL(dma_get_required_mask); | |
799 | ||
3efe2d84 MW |
800 | static int __init pcibios_init(void) |
801 | { | |
ac1aa47b | 802 | set_pci_dfl_cacheline_size(); |
3efe2d84 | 803 | return 0; |
1da177e4 | 804 | } |
3efe2d84 MW |
805 | |
806 | subsys_initcall(pcibios_init); |