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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
13 | #include <linux/config.h> | |
14 | ||
15 | #include <linux/acpi.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/smp_lock.h> | |
23 | #include <linux/spinlock.h> | |
24 | ||
25 | #include <asm/machvec.h> | |
26 | #include <asm/page.h> | |
27 | #include <asm/segment.h> | |
28 | #include <asm/system.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/sal.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/irq.h> | |
33 | #include <asm/hw_irq.h> | |
34 | ||
35 | ||
1da177e4 LT |
36 | /* |
37 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
38 | * calls are already serialized (via sal_lock), so we don't need another | |
39 | * synchronization mechanism here. | |
40 | */ | |
41 | ||
42 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
43 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
44 | ||
45 | /* SAL 3.2 adds support for extended config space. */ | |
46 | ||
47 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
48 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
49 | ||
50 | static int | |
51 | pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn, | |
52 | int reg, int len, u32 *value) | |
53 | { | |
54 | u64 addr, data = 0; | |
55 | int mode, result; | |
56 | ||
57 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
58 | return -EINVAL; | |
59 | ||
60 | if ((seg | reg) <= 255) { | |
61 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
62 | mode = 0; | |
63 | } else { | |
64 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
65 | mode = 1; | |
66 | } | |
67 | result = ia64_sal_pci_config_read(addr, mode, len, &data); | |
68 | if (result != 0) | |
69 | return -EINVAL; | |
70 | ||
71 | *value = (u32) data; | |
72 | return 0; | |
73 | } | |
74 | ||
75 | static int | |
76 | pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn, | |
77 | int reg, int len, u32 value) | |
78 | { | |
79 | u64 addr; | |
80 | int mode, result; | |
81 | ||
82 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
83 | return -EINVAL; | |
84 | ||
85 | if ((seg | reg) <= 255) { | |
86 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
87 | mode = 0; | |
88 | } else { | |
89 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
90 | mode = 1; | |
91 | } | |
92 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
93 | if (result != 0) | |
94 | return -EINVAL; | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static struct pci_raw_ops pci_sal_ops = { | |
99 | .read = pci_sal_read, | |
100 | .write = pci_sal_write | |
101 | }; | |
102 | ||
103 | struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; | |
104 | ||
105 | static int | |
106 | pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) | |
107 | { | |
108 | return raw_pci_ops->read(pci_domain_nr(bus), bus->number, | |
109 | devfn, where, size, value); | |
110 | } | |
111 | ||
112 | static int | |
113 | pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) | |
114 | { | |
115 | return raw_pci_ops->write(pci_domain_nr(bus), bus->number, | |
116 | devfn, where, size, value); | |
117 | } | |
118 | ||
119 | struct pci_ops pci_root_ops = { | |
120 | .read = pci_read, | |
121 | .write = pci_write, | |
122 | }; | |
123 | ||
124 | #ifdef CONFIG_NUMA | |
125 | extern acpi_status acpi_map_iosapic(acpi_handle, u32, void *, void **); | |
126 | static void acpi_map_iosapics(void) | |
127 | { | |
128 | acpi_get_devices(NULL, acpi_map_iosapic, NULL, NULL); | |
129 | } | |
130 | #else | |
131 | static void acpi_map_iosapics(void) | |
132 | { | |
133 | return; | |
134 | } | |
135 | #endif /* CONFIG_NUMA */ | |
136 | ||
137 | static int __init | |
138 | pci_acpi_init (void) | |
139 | { | |
1da177e4 LT |
140 | acpi_map_iosapics(); |
141 | ||
1da177e4 LT |
142 | return 0; |
143 | } | |
144 | ||
145 | subsys_initcall(pci_acpi_init); | |
146 | ||
147 | /* Called by ACPI when it finds a new root bus. */ | |
148 | ||
149 | static struct pci_controller * __devinit | |
150 | alloc_pci_controller (int seg) | |
151 | { | |
152 | struct pci_controller *controller; | |
153 | ||
154 | controller = kmalloc(sizeof(*controller), GFP_KERNEL); | |
155 | if (!controller) | |
156 | return NULL; | |
157 | ||
158 | memset(controller, 0, sizeof(*controller)); | |
159 | controller->segment = seg; | |
160 | return controller; | |
161 | } | |
162 | ||
163 | static u64 __devinit | |
164 | add_io_space (struct acpi_resource_address64 *addr) | |
165 | { | |
166 | u64 offset; | |
167 | int sparse = 0; | |
168 | int i; | |
169 | ||
170 | if (addr->address_translation_offset == 0) | |
171 | return IO_SPACE_BASE(0); /* part of legacy IO space */ | |
172 | ||
173 | if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION) | |
174 | sparse = 1; | |
175 | ||
176 | offset = (u64) ioremap(addr->address_translation_offset, 0); | |
177 | for (i = 0; i < num_io_spaces; i++) | |
178 | if (io_space[i].mmio_base == offset && | |
179 | io_space[i].sparse == sparse) | |
180 | return IO_SPACE_BASE(i); | |
181 | ||
182 | if (num_io_spaces == MAX_IO_SPACES) { | |
183 | printk("Too many IO port spaces\n"); | |
184 | return ~0; | |
185 | } | |
186 | ||
187 | i = num_io_spaces++; | |
188 | io_space[i].mmio_base = offset; | |
189 | io_space[i].sparse = sparse; | |
190 | ||
191 | return IO_SPACE_BASE(i); | |
192 | } | |
193 | ||
194 | static acpi_status __devinit | |
195 | count_window (struct acpi_resource *resource, void *data) | |
196 | { | |
197 | unsigned int *windows = (unsigned int *) data; | |
198 | struct acpi_resource_address64 addr; | |
199 | acpi_status status; | |
200 | ||
201 | status = acpi_resource_to_address64(resource, &addr); | |
202 | if (ACPI_SUCCESS(status)) | |
203 | if (addr.resource_type == ACPI_MEMORY_RANGE || | |
204 | addr.resource_type == ACPI_IO_RANGE) | |
205 | (*windows)++; | |
206 | ||
207 | return AE_OK; | |
208 | } | |
209 | ||
210 | struct pci_root_info { | |
211 | struct pci_controller *controller; | |
212 | char *name; | |
213 | }; | |
214 | ||
215 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) | |
216 | { | |
217 | struct pci_root_info *info = data; | |
218 | struct pci_window *window; | |
219 | struct acpi_resource_address64 addr; | |
220 | acpi_status status; | |
221 | unsigned long flags, offset = 0; | |
222 | struct resource *root; | |
223 | ||
224 | status = acpi_resource_to_address64(res, &addr); | |
225 | if (!ACPI_SUCCESS(status)) | |
226 | return AE_OK; | |
227 | ||
228 | if (!addr.address_length) | |
229 | return AE_OK; | |
230 | ||
231 | if (addr.resource_type == ACPI_MEMORY_RANGE) { | |
232 | flags = IORESOURCE_MEM; | |
233 | root = &iomem_resource; | |
234 | offset = addr.address_translation_offset; | |
235 | } else if (addr.resource_type == ACPI_IO_RANGE) { | |
236 | flags = IORESOURCE_IO; | |
237 | root = &ioport_resource; | |
238 | offset = add_io_space(&addr); | |
239 | if (offset == ~0) | |
240 | return AE_OK; | |
241 | } else | |
242 | return AE_OK; | |
243 | ||
244 | window = &info->controller->window[info->controller->windows++]; | |
245 | window->resource.name = info->name; | |
246 | window->resource.flags = flags; | |
247 | window->resource.start = addr.min_address_range + offset; | |
248 | window->resource.end = addr.max_address_range + offset; | |
249 | window->resource.child = NULL; | |
250 | window->offset = offset; | |
251 | ||
252 | if (insert_resource(root, &window->resource)) { | |
253 | printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n", | |
254 | window->resource.start, window->resource.end, | |
255 | root->name, info->name); | |
256 | } | |
257 | ||
258 | return AE_OK; | |
259 | } | |
260 | ||
261 | static void __devinit | |
262 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
263 | { | |
264 | int i, j; | |
265 | ||
266 | j = 0; | |
267 | for (i = 0; i < ctrl->windows; i++) { | |
268 | struct resource *res = &ctrl->window[i].resource; | |
269 | /* HP's firmware has a hack to work around a Windows bug. | |
270 | * Ignore these tiny memory ranges */ | |
271 | if ((res->flags & IORESOURCE_MEM) && | |
272 | (res->end - res->start < 16)) | |
273 | continue; | |
274 | if (j >= PCI_BUS_NUM_RESOURCES) { | |
275 | printk("Ignoring range [%lx-%lx] (%lx)\n", res->start, | |
276 | res->end, res->flags); | |
277 | continue; | |
278 | } | |
279 | bus->resource[j++] = res; | |
280 | } | |
281 | } | |
282 | ||
283 | struct pci_bus * __devinit | |
284 | pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) | |
285 | { | |
286 | struct pci_root_info info; | |
287 | struct pci_controller *controller; | |
288 | unsigned int windows = 0; | |
289 | struct pci_bus *pbus; | |
290 | char *name; | |
291 | ||
292 | controller = alloc_pci_controller(domain); | |
293 | if (!controller) | |
294 | goto out1; | |
295 | ||
296 | controller->acpi_handle = device->handle; | |
297 | ||
298 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, | |
299 | &windows); | |
300 | controller->window = kmalloc(sizeof(*controller->window) * windows, | |
301 | GFP_KERNEL); | |
302 | if (!controller->window) | |
303 | goto out2; | |
304 | ||
305 | name = kmalloc(16, GFP_KERNEL); | |
306 | if (!name) | |
307 | goto out3; | |
308 | ||
309 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); | |
310 | info.controller = controller; | |
311 | info.name = name; | |
312 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, | |
313 | &info); | |
314 | ||
c431ada4 | 315 | pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); |
1da177e4 LT |
316 | if (pbus) |
317 | pcibios_setup_root_windows(pbus, controller); | |
318 | ||
319 | return pbus; | |
320 | ||
321 | out3: | |
322 | kfree(controller->window); | |
323 | out2: | |
324 | kfree(controller); | |
325 | out1: | |
326 | return NULL; | |
327 | } | |
328 | ||
329 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
330 | struct pci_bus_region *region, struct resource *res) | |
331 | { | |
332 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
333 | unsigned long offset = 0; | |
334 | int i; | |
335 | ||
336 | for (i = 0; i < controller->windows; i++) { | |
337 | struct pci_window *window = &controller->window[i]; | |
338 | if (!(window->resource.flags & res->flags)) | |
339 | continue; | |
340 | if (window->resource.start > res->start) | |
341 | continue; | |
342 | if (window->resource.end < res->end) | |
343 | continue; | |
344 | offset = window->offset; | |
345 | break; | |
346 | } | |
347 | ||
348 | region->start = res->start - offset; | |
349 | region->end = res->end - offset; | |
350 | } | |
351 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
352 | ||
353 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
354 | struct resource *res, struct pci_bus_region *region) | |
355 | { | |
356 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
357 | unsigned long offset = 0; | |
358 | int i; | |
359 | ||
360 | for (i = 0; i < controller->windows; i++) { | |
361 | struct pci_window *window = &controller->window[i]; | |
362 | if (!(window->resource.flags & res->flags)) | |
363 | continue; | |
364 | if (window->resource.start - window->offset > region->start) | |
365 | continue; | |
366 | if (window->resource.end - window->offset < region->end) | |
367 | continue; | |
368 | offset = window->offset; | |
369 | break; | |
370 | } | |
371 | ||
372 | res->start = region->start + offset; | |
373 | res->end = region->end + offset; | |
374 | } | |
375 | ||
71c3511c RS |
376 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
377 | { | |
378 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
379 | struct resource *devr = &dev->resource[idx]; | |
380 | ||
381 | if (!dev->bus) | |
382 | return 0; | |
383 | for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) { | |
384 | struct resource *busr = dev->bus->resource[i]; | |
385 | ||
386 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) | |
387 | continue; | |
388 | if ((devr->start) && (devr->start >= busr->start) && | |
389 | (devr->end <= busr->end)) | |
390 | return 1; | |
391 | } | |
392 | return 0; | |
393 | } | |
394 | ||
1da177e4 LT |
395 | static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
396 | { | |
397 | struct pci_bus_region region; | |
398 | int i; | |
399 | int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \ | |
400 | PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES; | |
401 | ||
402 | for (i = 0; i < limit; i++) { | |
403 | if (!dev->resource[i].flags) | |
404 | continue; | |
405 | region.start = dev->resource[i].start; | |
406 | region.end = dev->resource[i].end; | |
407 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
408 | if ((is_valid_resource(dev, i))) |
409 | pci_claim_resource(dev, i); | |
1da177e4 LT |
410 | } |
411 | } | |
412 | ||
413 | /* | |
414 | * Called after each bus is probed, but before its children are examined. | |
415 | */ | |
416 | void __devinit | |
417 | pcibios_fixup_bus (struct pci_bus *b) | |
418 | { | |
419 | struct pci_dev *dev; | |
420 | ||
f7d473d9 RS |
421 | if (b->self) { |
422 | pci_read_bridge_bases(b); | |
423 | pcibios_fixup_device_resources(b->self); | |
424 | } | |
1da177e4 LT |
425 | list_for_each_entry(dev, &b->devices, bus_list) |
426 | pcibios_fixup_device_resources(dev); | |
427 | ||
428 | return; | |
429 | } | |
430 | ||
431 | void __devinit | |
432 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
433 | { | |
434 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
435 | ||
436 | /* ??? FIXME -- record old value for shutdown. */ | |
437 | } | |
438 | ||
439 | static inline int | |
440 | pcibios_enable_resources (struct pci_dev *dev, int mask) | |
441 | { | |
442 | u16 cmd, old_cmd; | |
443 | int idx; | |
444 | struct resource *r; | |
fab3fb0a | 445 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM; |
1da177e4 LT |
446 | |
447 | if (!dev) | |
448 | return -EINVAL; | |
449 | ||
450 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
451 | old_cmd = cmd; | |
fab3fb0a | 452 | for (idx=0; idx<PCI_NUM_RESOURCES; idx++) { |
1da177e4 LT |
453 | /* Only set up the desired resources. */ |
454 | if (!(mask & (1 << idx))) | |
455 | continue; | |
456 | ||
457 | r = &dev->resource[idx]; | |
fab3fb0a RS |
458 | if (!(r->flags & type_mask)) |
459 | continue; | |
460 | if ((idx == PCI_ROM_RESOURCE) && | |
461 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
462 | continue; | |
1da177e4 LT |
463 | if (!r->start && r->end) { |
464 | printk(KERN_ERR | |
465 | "PCI: Device %s not available because of resource collisions\n", | |
466 | pci_name(dev)); | |
467 | return -EINVAL; | |
468 | } | |
469 | if (r->flags & IORESOURCE_IO) | |
470 | cmd |= PCI_COMMAND_IO; | |
471 | if (r->flags & IORESOURCE_MEM) | |
472 | cmd |= PCI_COMMAND_MEMORY; | |
473 | } | |
1da177e4 LT |
474 | if (cmd != old_cmd) { |
475 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); | |
476 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
477 | } | |
478 | return 0; | |
479 | } | |
480 | ||
481 | int | |
482 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
483 | { | |
484 | int ret; | |
485 | ||
486 | ret = pcibios_enable_resources(dev, mask); | |
487 | if (ret < 0) | |
488 | return ret; | |
489 | ||
490 | return acpi_pci_irq_enable(dev); | |
491 | } | |
492 | ||
493 | #ifdef CONFIG_ACPI_DEALLOCATE_IRQ | |
494 | void | |
495 | pcibios_disable_device (struct pci_dev *dev) | |
496 | { | |
497 | acpi_pci_irq_disable(dev); | |
498 | } | |
499 | #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */ | |
500 | ||
501 | void | |
502 | pcibios_align_resource (void *data, struct resource *res, | |
503 | unsigned long size, unsigned long align) | |
504 | { | |
505 | } | |
506 | ||
507 | /* | |
508 | * PCI BIOS setup, always defaults to SAL interface | |
509 | */ | |
510 | char * __init | |
511 | pcibios_setup (char *str) | |
512 | { | |
1da177e4 LT |
513 | return NULL; |
514 | } | |
515 | ||
516 | int | |
517 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
518 | enum pci_mmap_state mmap_state, int write_combine) | |
519 | { | |
520 | /* | |
521 | * I/O space cannot be accessed via normal processor loads and | |
522 | * stores on this platform. | |
523 | */ | |
524 | if (mmap_state == pci_mmap_io) | |
525 | /* | |
526 | * XXX we could relax this for I/O spaces for which ACPI | |
527 | * indicates that the space is 1-to-1 mapped. But at the | |
528 | * moment, we don't support multiple PCI address spaces and | |
529 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
530 | */ | |
531 | return -EINVAL; | |
532 | ||
533 | /* | |
534 | * Leave vm_pgoff as-is, the PCI space address is the physical | |
535 | * address on this platform. | |
536 | */ | |
537 | vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO); | |
538 | ||
539 | if (write_combine && efi_range_is_wc(vma->vm_start, | |
540 | vma->vm_end - vma->vm_start)) | |
541 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
542 | else | |
543 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
544 | ||
545 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
546 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
547 | return -EAGAIN; | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | /** | |
553 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
554 | * @bus: bus to get legacy memory base address for | |
555 | * | |
556 | * Find the base of legacy memory for @bus. This is typically the first | |
557 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
558 | * chipsets support legacy I/O and memory routing. Returns the base address | |
559 | * or an error pointer if an error occurred. | |
560 | * | |
561 | * This is the ia64 generic version of this routine. Other platforms | |
562 | * are free to override it with a machine vector. | |
563 | */ | |
564 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
565 | { | |
566 | return (char *)__IA64_UNCACHED_OFFSET; | |
567 | } | |
568 | ||
569 | /** | |
570 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
571 | * @bus: bus whose legacy space we're mapping | |
572 | * @vma: vma passed in by mmap | |
573 | * | |
574 | * Map legacy memory space for this device back to userspace using a machine | |
575 | * vector to get the base address. | |
576 | */ | |
577 | int | |
578 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma) | |
579 | { | |
580 | char *addr; | |
581 | ||
582 | addr = pci_get_legacy_mem(bus); | |
583 | if (IS_ERR(addr)) | |
584 | return PTR_ERR(addr); | |
585 | ||
586 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
587 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
588 | vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO); | |
589 | ||
590 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
591 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
592 | return -EAGAIN; | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | /** | |
598 | * ia64_pci_legacy_read - read from legacy I/O space | |
599 | * @bus: bus to read | |
600 | * @port: legacy port value | |
601 | * @val: caller allocated storage for returned value | |
602 | * @size: number of bytes to read | |
603 | * | |
604 | * Simply reads @size bytes from @port and puts the result in @val. | |
605 | * | |
606 | * Again, this (and the write routine) are generic versions that can be | |
607 | * overridden by the platform. This is necessary on platforms that don't | |
608 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
609 | */ | |
610 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
611 | { | |
612 | int ret = size; | |
613 | ||
614 | switch (size) { | |
615 | case 1: | |
616 | *val = inb(port); | |
617 | break; | |
618 | case 2: | |
619 | *val = inw(port); | |
620 | break; | |
621 | case 4: | |
622 | *val = inl(port); | |
623 | break; | |
624 | default: | |
625 | ret = -EINVAL; | |
626 | break; | |
627 | } | |
628 | ||
629 | return ret; | |
630 | } | |
631 | ||
632 | /** | |
633 | * ia64_pci_legacy_write - perform a legacy I/O write | |
634 | * @bus: bus pointer | |
635 | * @port: port to write | |
636 | * @val: value to write | |
637 | * @size: number of bytes to write from @val | |
638 | * | |
639 | * Simply writes @size bytes of @val to @port. | |
640 | */ | |
641 | int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size) | |
642 | { | |
643 | int ret = 0; | |
644 | ||
645 | switch (size) { | |
646 | case 1: | |
647 | outb(val, port); | |
648 | break; | |
649 | case 2: | |
650 | outw(val, port); | |
651 | break; | |
652 | case 4: | |
653 | outl(val, port); | |
654 | break; | |
655 | default: | |
656 | ret = -EINVAL; | |
657 | break; | |
658 | } | |
659 | ||
660 | return ret; | |
661 | } | |
662 | ||
663 | /** | |
664 | * pci_cacheline_size - determine cacheline size for PCI devices | |
665 | * @dev: void | |
666 | * | |
667 | * We want to use the line-size of the outer-most cache. We assume | |
668 | * that this line-size is the same for all CPUs. | |
669 | * | |
670 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
671 | * | |
672 | * RETURNS: An appropriate -ERRNO error value on eror, or zero for success. | |
673 | */ | |
674 | static unsigned long | |
675 | pci_cacheline_size (void) | |
676 | { | |
677 | u64 levels, unique_caches; | |
678 | s64 status; | |
679 | pal_cache_config_info_t cci; | |
680 | static u8 cacheline_size; | |
681 | ||
682 | if (cacheline_size) | |
683 | return cacheline_size; | |
684 | ||
685 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
686 | if (status != 0) { | |
687 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", | |
688 | __FUNCTION__, status); | |
689 | return SMP_CACHE_BYTES; | |
690 | } | |
691 | ||
692 | status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2, | |
693 | &cci); | |
694 | if (status != 0) { | |
695 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n", | |
696 | __FUNCTION__, status); | |
697 | return SMP_CACHE_BYTES; | |
698 | } | |
699 | cacheline_size = 1 << cci.pcci_line_size; | |
700 | return cacheline_size; | |
701 | } | |
702 | ||
703 | /** | |
704 | * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi() | |
705 | * @dev: the PCI device for which MWI is enabled | |
706 | * | |
707 | * For ia64, we can get the cacheline sizes from PAL. | |
708 | * | |
709 | * RETURNS: An appropriate -ERRNO error value on eror, or zero for success. | |
710 | */ | |
711 | int | |
712 | pcibios_prep_mwi (struct pci_dev *dev) | |
713 | { | |
714 | unsigned long desired_linesize, current_linesize; | |
715 | int rc = 0; | |
716 | u8 pci_linesize; | |
717 | ||
718 | desired_linesize = pci_cacheline_size(); | |
719 | ||
720 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize); | |
721 | current_linesize = 4 * pci_linesize; | |
722 | if (desired_linesize != current_linesize) { | |
723 | printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,", | |
724 | pci_name(dev), current_linesize); | |
725 | if (current_linesize > desired_linesize) { | |
726 | printk(" expected %lu bytes instead\n", desired_linesize); | |
727 | rc = -EINVAL; | |
728 | } else { | |
729 | printk(" correcting to %lu\n", desired_linesize); | |
730 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4); | |
731 | } | |
732 | } | |
733 | return rc; | |
734 | } | |
735 | ||
736 | int pci_vector_resources(int last, int nr_released) | |
737 | { | |
738 | int count = nr_released; | |
739 | ||
740 | count += (IA64_LAST_DEVICE_VECTOR - last); | |
741 | ||
742 | return count; | |
743 | } |