[deliverable/linux.git] / arch / ia64 / sn / kernel / irq.c

/*
 * Platform dependent support for SGI SN
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2000-2005 Silicon Graphics, Inc.  All Rights Reserved.
 */

#include <linux/irq.h>
#include <linux/spinlock.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/shub_mmr.h>
#include <asm/sn/sn_sal.h>

static void force_interrupt(int irq);
static void register_intr_pda(struct sn_irq_info *sn_irq_info);
static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);

int sn_force_interrupt_flag = 1;
extern int sn_ioif_inited;
static struct list_head **sn_irq_lh;
static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */

static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
				     u64 sn_irq_info,
				     int req_irq, nasid_t req_nasid,
				     int req_slice)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
			(u64) local_widget, (u64) sn_irq_info, (u64) req_irq,
			(u64) req_nasid, (u64) req_slice);
	return ret_stuff.status;
}

static inline void sn_intr_free(nasid_t local_nasid, int local_widget,
				struct sn_irq_info *sn_irq_info)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_FREE, (u64) local_nasid,
			(u64) local_widget, (u64) sn_irq_info->irq_irq,
			(u64) sn_irq_info->irq_cookie, 0, 0);
}

static unsigned int sn_startup_irq(unsigned int irq)
{
	return 0;
}

static void sn_shutdown_irq(unsigned int irq)
{
}

static void sn_disable_irq(unsigned int irq)
{
}

static void sn_enable_irq(unsigned int irq)
{
}

static void sn_ack_irq(unsigned int irq)
{
	u64 event_occurred, mask = 0;

	irq = irq & 0xff;
	event_occurred =
	    HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
	mask = event_occurred & SH_ALL_INT_MASK;
	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS),
	      mask);
	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);

	move_native_irq(irq);
}

static void sn_end_irq(unsigned int irq)
{
	int ivec;
	u64 event_occurred;

	ivec = irq & 0xff;
	if (ivec == SGI_UART_VECTOR) {
		event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
		/* If the UART bit is set here, we may have received an
		 * interrupt from the UART that the driver missed.  To
		 * make sure, we IPI ourselves to force us to look again.
		 */
		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
			platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
					  IA64_IPI_DM_INT, 0);
		}
	}
	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
	if (sn_force_interrupt_flag)
		force_interrupt(irq);
}

static void sn_irq_info_free(struct rcu_head *head);

static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
{
	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
	int cpuid, cpuphys;

	cpuid = first_cpu(mask);
	cpuphys = cpu_physical_id(cpuid);

	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
				 sn_irq_lh[irq], list) {
		u64 bridge;
		int local_widget, status;
		nasid_t local_nasid;
		struct sn_irq_info *new_irq_info;
		struct sn_pcibus_provider *pci_provider;

		new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
		if (new_irq_info == NULL)
			break;
		memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));

		bridge = (u64) new_irq_info->irq_bridge;
		if (!bridge) {
			kfree(new_irq_info);
			break; /* irq is not a device interrupt */
		}

		local_nasid = NASID_GET(bridge);

		if (local_nasid & 1)
			local_widget = TIO_SWIN_WIDGETNUM(bridge);
		else
			local_widget = SWIN_WIDGETNUM(bridge);

		/* Free the old PROM new_irq_info structure */
		sn_intr_free(local_nasid, local_widget, new_irq_info);
		/* Update kernels new_irq_info with new target info */
		unregister_intr_pda(new_irq_info);

		/* allocate a new PROM new_irq_info struct */
		status = sn_intr_alloc(local_nasid, local_widget,
				       __pa(new_irq_info), irq,
				       cpuid_to_nasid(cpuid),
				       cpuid_to_slice(cpuid));

		/* SAL call failed */
		if (status) {
			kfree(new_irq_info);
			break;
		}

		new_irq_info->irq_cpuid = cpuid;
		register_intr_pda(new_irq_info);

		pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
		if (pci_provider && pci_provider->target_interrupt)
			(pci_provider->target_interrupt)(new_irq_info);

		spin_lock(&sn_irq_info_lock);
		list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
		spin_unlock(&sn_irq_info_lock);
		call_rcu(&sn_irq_info->rcu, sn_irq_info_free);

#ifdef CONFIG_SMP
		set_irq_affinity_info((irq & 0xff), cpuphys, 0);
#endif
	}
}

struct hw_interrupt_type irq_type_sn = {
	.typename	= "SN hub",
	.startup	= sn_startup_irq,
	.shutdown	= sn_shutdown_irq,
	.enable		= sn_enable_irq,
	.disable	= sn_disable_irq,
	.ack		= sn_ack_irq,
	.end		= sn_end_irq,
	.set_affinity	= sn_set_affinity_irq
};

unsigned int sn_local_vector_to_irq(u8 vector)
{
	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
}

void sn_irq_init(void)
{
	int i;
	irq_desc_t *base_desc = irq_desc;

	for (i = 0; i < NR_IRQS; i++) {
		if (base_desc[i].handler == &no_irq_type) {
			base_desc[i].handler = &irq_type_sn;
		}
	}
}

static void register_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;

	if (pdacpu(cpu)->sn_last_irq < irq) {
		pdacpu(cpu)->sn_last_irq = irq;
	}

	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq) {
		pdacpu(cpu)->sn_first_irq = irq;
	}
}

static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;
	struct sn_irq_info *tmp_irq_info;
	int i, foundmatch;

	rcu_read_lock();
	if (pdacpu(cpu)->sn_last_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_last_irq - 1;
		     i && !foundmatch; i--) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_last_irq = i;
	}

	if (pdacpu(cpu)->sn_first_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_first_irq + 1;
		     i < NR_IRQS && !foundmatch; i++) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	}
	rcu_read_unlock();
}

static void sn_irq_info_free(struct rcu_head *head)
{
	struct sn_irq_info *sn_irq_info;

	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
	kfree(sn_irq_info);
}

void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
{
	nasid_t nasid = sn_irq_info->irq_nasid;
	int slice = sn_irq_info->irq_slice;
	int cpu = nasid_slice_to_cpuid(nasid, slice);

	pci_dev_get(pci_dev);
	sn_irq_info->irq_cpuid = cpu;
	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);

	/* link it into the sn_irq[irq] list */
	spin_lock(&sn_irq_info_lock);
	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
	spin_unlock(&sn_irq_info_lock);

	(void)register_intr_pda(sn_irq_info);
}

void sn_irq_unfixup(struct pci_dev *pci_dev)
{
	struct sn_irq_info *sn_irq_info;

	/* Only cleanup IRQ stuff if this device has a host bus context */
	if (!SN_PCIDEV_BUSSOFT(pci_dev))
		return;

	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
	if (!sn_irq_info || !sn_irq_info->irq_irq) {
		kfree(sn_irq_info);
		return;
	}

	unregister_intr_pda(sn_irq_info);
	spin_lock(&sn_irq_info_lock);
	list_del_rcu(&sn_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
	pci_dev_put(pci_dev);
}

static inline void
sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
{
	struct sn_pcibus_provider *pci_provider;

	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
	if (pci_provider && pci_provider->force_interrupt)
		(*pci_provider->force_interrupt)(sn_irq_info);
}

static void force_interrupt(int irq)
{
	struct sn_irq_info *sn_irq_info;

	if (!sn_ioif_inited)
		return;

	rcu_read_lock();
	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
		sn_call_force_intr_provider(sn_irq_info);

	rcu_read_unlock();
}

/*
 * Check for lost interrupts.  If the PIC int_status reg. says that
 * an interrupt has been sent, but not handled, and the interrupt
 * is not pending in either the cpu irr regs or in the soft irr regs,
 * and the interrupt is not in service, then the interrupt may have
 * been lost.  Force an interrupt on that pin.  It is possible that
 * the interrupt is in flight, so we may generate a spurious interrupt,
 * but we should never miss a real lost interrupt.
 */
static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
{
	u64 regval;
	int irr_reg_num;
	int irr_bit;
	u64 irr_reg;
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;

	/*
	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
	 * since they do not target Shub II interrupt registers.  If that
	 * ever changes, this check needs to accomodate.
	 */
	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (!pcidev_info)
		return;

	pcibus_info =
	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	    pdi_pcibus_info;
	regval = pcireg_intr_status_get(pcibus_info);

	irr_reg_num = irq_to_vector(irq) / 64;
	irr_bit = irq_to_vector(irq) % 64;
	switch (irr_reg_num) {
	case 0:
		irr_reg = ia64_getreg(_IA64_REG_CR_IRR0);
		break;
	case 1:
		irr_reg = ia64_getreg(_IA64_REG_CR_IRR1);
		break;
	case 2:
		irr_reg = ia64_getreg(_IA64_REG_CR_IRR2);
		break;
	case 3:
		irr_reg = ia64_getreg(_IA64_REG_CR_IRR3);
		break;
	}
	if (!test_bit(irr_bit, &irr_reg)) {
		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
			regval &= 0xff;
			if (sn_irq_info->irq_int_bit & regval &
			    sn_irq_info->irq_last_intr) {
				regval &= ~(sn_irq_info->irq_int_bit & regval);
				sn_call_force_intr_provider(sn_irq_info);
			}
		}
	}
	sn_irq_info->irq_last_intr = regval;
}

void sn_lb_int_war_check(void)
{
	struct sn_irq_info *sn_irq_info;
	int i;

	if (!sn_ioif_inited || pda->sn_first_irq == 0)
		return;

	rcu_read_lock();
	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
			sn_check_intr(i, sn_irq_info);
		}
	}
	rcu_read_unlock();
}

void sn_irq_lh_init(void)
{
	int i;

	sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
	if (!sn_irq_lh)
		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");

	for (i = 0; i < NR_IRQS; i++) {
		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
		if (!sn_irq_lh[i])
			panic("SN PCI INIT: Failed IRQ memory allocation\n");

		INIT_LIST_HEAD(sn_irq_lh[i]);
	}

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Platform dependent support for SGI SN
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
0aa2c72e	8	* Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
1da177e4 LT	9	*/
	10
	11	#include <linux/irq.h>
cb4cb2cb	12	#include <linux/spinlock.h>
1da177e4 LT	13	#include <asm/sn/addrs.h>
1da177e4 LT	14	#include <asm/sn/arch.h>
c13cf371 PB	15	#include <asm/sn/intr.h>
c13cf371 PB	16	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	17	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	18	#include <asm/sn/pcidev.h>
1da177e4 LT	19	#include <asm/sn/shub_mmr.h>
	20	#include <asm/sn/sn_sal.h>
	21
	22	static void force_interrupt(int irq);
	23	static void register_intr_pda(struct sn_irq_info *sn_irq_info);
	24	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
	25
d0d59b98	26	int sn_force_interrupt_flag = 1;
1da177e4	27	extern int sn_ioif_inited;
cb4cb2cb PB	28	static struct list_head **sn_irq_lh;
cb4cb2cb PB	29	static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */
1da177e4	30
53493dcf	31	static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
1da177e4 LT	32	u64 sn_irq_info,
	33	int req_irq, nasid_t req_nasid,
	34	int req_slice)
	35	{
	36	struct ia64_sal_retval ret_stuff;
	37	ret_stuff.status = 0;
	38	ret_stuff.v0 = 0;
	39
	40	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	41	(u64) SAL_INTR_ALLOC, (u64) local_nasid,
	42	(u64) local_widget, (u64) sn_irq_info, (u64) req_irq,
	43	(u64) req_nasid, (u64) req_slice);
	44	return ret_stuff.status;
	45	}
	46
	47	static inline void sn_intr_free(nasid_t local_nasid, int local_widget,
	48	struct sn_irq_info *sn_irq_info)
	49	{
	50	struct ia64_sal_retval ret_stuff;
	51	ret_stuff.status = 0;
	52	ret_stuff.v0 = 0;
	53
	54	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	55	(u64) SAL_INTR_FREE, (u64) local_nasid,
	56	(u64) local_widget, (u64) sn_irq_info->irq_irq,
	57	(u64) sn_irq_info->irq_cookie, 0, 0);
	58	}
	59
	60	static unsigned int sn_startup_irq(unsigned int irq)
	61	{
	62	return 0;
	63	}
	64
	65	static void sn_shutdown_irq(unsigned int irq)
	66	{
	67	}
	68
	69	static void sn_disable_irq(unsigned int irq)
	70	{
	71	}
	72
	73	static void sn_enable_irq(unsigned int irq)
	74	{
	75	}
	76
	77	static void sn_ack_irq(unsigned int irq)
	78	{
0aa2c72e	79	u64 event_occurred, mask = 0;
1da177e4 LT	80
1da177e4 LT	81	irq = irq & 0xff;
1da177e4	82	event_occurred =
0aa2c72e	83	HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
be539c73	84	mask = event_occurred & SH_ALL_INT_MASK;
0aa2c72e JS	85	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS),
0aa2c72e JS	86	mask);
1da177e4 LT	87	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
1da177e4 LT	88
689388bb	89	move_native_irq(irq);
1da177e4 LT	90	}
	91
	92	static void sn_end_irq(unsigned int irq)
	93	{
1da177e4	94	int ivec;
0aa2c72e	95	u64 event_occurred;
1da177e4 LT	96
	97	ivec = irq & 0xff;
	98	if (ivec == SGI_UART_VECTOR) {
0aa2c72e	99	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
cb4cb2cb	100	/* If the UART bit is set here, we may have received an
1da177e4 LT	101	* interrupt from the UART that the driver missed. To
	102	* make sure, we IPI ourselves to force us to look again.
	103	*/
	104	if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
	105	platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
	106	IA64_IPI_DM_INT, 0);
	107	}
	108	}
	109	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
	110	if (sn_force_interrupt_flag)
	111	force_interrupt(irq);
	112	}
	113
cb4cb2cb PB	114	static void sn_irq_info_free(struct rcu_head *head);
cb4cb2cb PB	115
1da177e4 LT	116	static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
1da177e4 LT	117	{
cb4cb2cb	118	struct sn_irq_info sn_irq_info, sn_irq_info_safe;
1da177e4	119	int cpuid, cpuphys;
1da177e4 LT	120
	121	cpuid = first_cpu(mask);
	122	cpuphys = cpu_physical_id(cpuid);
1da177e4	123
cb4cb2cb PB	124	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
cb4cb2cb PB	125	sn_irq_lh[irq], list) {
53493dcf	126	u64 bridge;
cb4cb2cb PB	127	int local_widget, status;
	128	nasid_t local_nasid;
	129	struct sn_irq_info *new_irq_info;
8409668b	130	struct sn_pcibus_provider *pci_provider;
cb4cb2cb PB	131
	132	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
	133	if (new_irq_info == NULL)
	134	break;
	135	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
	136
53493dcf	137	bridge = (u64) new_irq_info->irq_bridge;
cb4cb2cb PB	138	if (!bridge) {
	139	kfree(new_irq_info);
	140	break; /* irq is not a device interrupt */
	141	}
1da177e4	142
cb4cb2cb	143	local_nasid = NASID_GET(bridge);
1da177e4 LT	144
	145	if (local_nasid & 1)
	146	local_widget = TIO_SWIN_WIDGETNUM(bridge);
	147	else
	148	local_widget = SWIN_WIDGETNUM(bridge);
	149
cb4cb2cb PB	150	/* Free the old PROM new_irq_info structure */
	151	sn_intr_free(local_nasid, local_widget, new_irq_info);
	152	/* Update kernels new_irq_info with new target info */
	153	unregister_intr_pda(new_irq_info);
1da177e4	154
cb4cb2cb	155	/* allocate a new PROM new_irq_info struct */
1da177e4	156	status = sn_intr_alloc(local_nasid, local_widget,
cb4cb2cb PB	157	__pa(new_irq_info), irq,
	158	cpuid_to_nasid(cpuid),
	159	cpuid_to_slice(cpuid));
	160
	161	/* SAL call failed */
	162	if (status) {
	163	kfree(new_irq_info);
	164	break;
	165	}
1da177e4	166
cb4cb2cb PB	167	new_irq_info->irq_cpuid = cpuid;
	168	register_intr_pda(new_irq_info);
	169
8409668b MM	170	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
	171	if (pci_provider && pci_provider->target_interrupt)
	172	(pci_provider->target_interrupt)(new_irq_info);
cb4cb2cb PB	173
	174	spin_lock(&sn_irq_info_lock);
	175	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	176	spin_unlock(&sn_irq_info_lock);
	177	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
1da177e4 LT	178
1da177e4 LT	179	#ifdef CONFIG_SMP
cb4cb2cb	180	set_irq_affinity_info((irq & 0xff), cpuphys, 0);
1da177e4	181	#endif
1da177e4	182	}
1da177e4 LT	183	}
	184
	185	struct hw_interrupt_type irq_type_sn = {
cb4cb2cb PB	186	.typename = "SN hub",
	187	.startup = sn_startup_irq,
	188	.shutdown = sn_shutdown_irq,
	189	.enable = sn_enable_irq,
	190	.disable = sn_disable_irq,
	191	.ack = sn_ack_irq,
	192	.end = sn_end_irq,
	193	.set_affinity = sn_set_affinity_irq
1da177e4 LT	194	};
	195
	196	unsigned int sn_local_vector_to_irq(u8 vector)
	197	{
	198	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
	199	}
	200
	201	void sn_irq_init(void)
	202	{
	203	int i;
	204	irq_desc_t *base_desc = irq_desc;
	205
	206	for (i = 0; i < NR_IRQS; i++) {
	207	if (base_desc[i].handler == &no_irq_type) {
	208	base_desc[i].handler = &irq_type_sn;
	209	}
	210	}
	211	}
	212
	213	static void register_intr_pda(struct sn_irq_info *sn_irq_info)
	214	{
	215	int irq = sn_irq_info->irq_irq;
	216	int cpu = sn_irq_info->irq_cpuid;
	217
	218	if (pdacpu(cpu)->sn_last_irq < irq) {
	219	pdacpu(cpu)->sn_last_irq = irq;
	220	}
	221
	222	if (pdacpu(cpu)->sn_first_irq == 0 \|\| pdacpu(cpu)->sn_first_irq > irq) {
	223	pdacpu(cpu)->sn_first_irq = irq;
	224	}
	225	}
	226
	227	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
	228	{
	229	int irq = sn_irq_info->irq_irq;
	230	int cpu = sn_irq_info->irq_cpuid;
	231	struct sn_irq_info *tmp_irq_info;
	232	int i, foundmatch;
	233
cb4cb2cb	234	rcu_read_lock();
1da177e4 LT	235	if (pdacpu(cpu)->sn_last_irq == irq) {
1da177e4 LT	236	foundmatch = 0;
cb4cb2cb PB	237	for (i = pdacpu(cpu)->sn_last_irq - 1;
	238	i && !foundmatch; i--) {
	239	list_for_each_entry_rcu(tmp_irq_info,
	240	sn_irq_lh[i],
	241	list) {
1da177e4	242	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	243	foundmatch = 1;
1da177e4 LT	244	break;
1da177e4 LT	245	}
1da177e4 LT	246	}
	247	}
	248	pdacpu(cpu)->sn_last_irq = i;
	249	}
	250
	251	if (pdacpu(cpu)->sn_first_irq == irq) {
	252	foundmatch = 0;
cb4cb2cb PB	253	for (i = pdacpu(cpu)->sn_first_irq + 1;
	254	i < NR_IRQS && !foundmatch; i++) {
	255	list_for_each_entry_rcu(tmp_irq_info,
	256	sn_irq_lh[i],
	257	list) {
1da177e4	258	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	259	foundmatch = 1;
1da177e4 LT	260	break;
1da177e4 LT	261	}
1da177e4 LT	262	}
	263	}
	264	pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	265	}
cb4cb2cb	266	rcu_read_unlock();
1da177e4 LT	267	}
1da177e4 LT	268
cb4cb2cb	269	static void sn_irq_info_free(struct rcu_head *head)
1da177e4 LT	270	{
1da177e4 LT	271	struct sn_irq_info *sn_irq_info;
1da177e4	272
cb4cb2cb	273	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
1da177e4 LT	274	kfree(sn_irq_info);
	275	}
	276
	277	void sn_irq_fixup(struct pci_dev pci_dev, struct sn_irq_info sn_irq_info)
	278	{
	279	nasid_t nasid = sn_irq_info->irq_nasid;
	280	int slice = sn_irq_info->irq_slice;
	281	int cpu = nasid_slice_to_cpuid(nasid, slice);
	282
cb4cb2cb	283	pci_dev_get(pci_dev);
1da177e4 LT	284	sn_irq_info->irq_cpuid = cpu;
	285	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
	286
	287	/* link it into the sn_irq[irq] list */
cb4cb2cb PB	288	spin_lock(&sn_irq_info_lock);
	289	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
	290	spin_unlock(&sn_irq_info_lock);
1da177e4 LT	291
	292	(void)register_intr_pda(sn_irq_info);
	293	}
	294
cb4cb2cb PB	295	void sn_irq_unfixup(struct pci_dev *pci_dev)
	296	{
	297	struct sn_irq_info *sn_irq_info;
	298
	299	/* Only cleanup IRQ stuff if this device has a host bus context */
	300	if (!SN_PCIDEV_BUSSOFT(pci_dev))
	301	return;
	302
	303	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
6f354b01 PB	304	if (!sn_irq_info \|\| !sn_irq_info->irq_irq) {
6f354b01 PB	305	kfree(sn_irq_info);
cb4cb2cb	306	return;
6f354b01	307	}
cb4cb2cb PB	308
	309	unregister_intr_pda(sn_irq_info);
	310	spin_lock(&sn_irq_info_lock);
	311	list_del_rcu(&sn_irq_info->list);
	312	spin_unlock(&sn_irq_info_lock);
	313	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
cb4cb2cb PB	314	pci_dev_put(pci_dev);
	315	}
	316
735e60f4 MM	317	static inline void
	318	sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
	319	{
	320	struct sn_pcibus_provider *pci_provider;
	321
	322	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
	323	if (pci_provider && pci_provider->force_interrupt)
	324	(*pci_provider->force_interrupt)(sn_irq_info);
	325	}
	326
1da177e4 LT	327	static void force_interrupt(int irq)
	328	{
	329	struct sn_irq_info *sn_irq_info;
	330
	331	if (!sn_ioif_inited)
	332	return;
cb4cb2cb PB	333
cb4cb2cb PB	334	rcu_read_lock();
735e60f4 MM	335	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
	336	sn_call_force_intr_provider(sn_irq_info);
	337
cb4cb2cb	338	rcu_read_unlock();
1da177e4 LT	339	}
	340
	341	/*
	342	* Check for lost interrupts. If the PIC int_status reg. says that
	343	* an interrupt has been sent, but not handled, and the interrupt
	344	* is not pending in either the cpu irr regs or in the soft irr regs,
	345	* and the interrupt is not in service, then the interrupt may have
	346	* been lost. Force an interrupt on that pin. It is possible that
	347	* the interrupt is in flight, so we may generate a spurious interrupt,
	348	* but we should never miss a real lost interrupt.
	349	*/
	350	static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
	351	{
53493dcf	352	u64 regval;
1da177e4 LT	353	int irr_reg_num;
1da177e4 LT	354	int irr_bit;
53493dcf	355	u64 irr_reg;
1da177e4 LT	356	struct pcidev_info *pcidev_info;
	357	struct pcibus_info *pcibus_info;
	358
735e60f4 MM	359	/*
	360	* Bridge types attached to TIO (anything but PIC) do not need this WAR
	361	* since they do not target Shub II interrupt registers. If that
	362	* ever changes, this check needs to accomodate.
	363	*/
	364	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
	365	return;
	366
1da177e4 LT	367	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	368	if (!pcidev_info)
	369	return;
	370
	371	pcibus_info =
	372	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	373	pdi_pcibus_info;
	374	regval = pcireg_intr_status_get(pcibus_info);
	375
	376	irr_reg_num = irq_to_vector(irq) / 64;
	377	irr_bit = irq_to_vector(irq) % 64;
	378	switch (irr_reg_num) {
	379	case 0:
	380	irr_reg = ia64_getreg(_IA64_REG_CR_IRR0);
	381	break;
	382	case 1:
	383	irr_reg = ia64_getreg(_IA64_REG_CR_IRR1);
	384	break;
	385	case 2:
	386	irr_reg = ia64_getreg(_IA64_REG_CR_IRR2);
	387	break;
	388	case 3:
	389	irr_reg = ia64_getreg(_IA64_REG_CR_IRR3);
	390	break;
	391	}
	392	if (!test_bit(irr_bit, &irr_reg)) {
735e60f4 MM	393	if (!test_bit(irq, pda->sn_in_service_ivecs)) {
	394	regval &= 0xff;
	395	if (sn_irq_info->irq_int_bit & regval &
	396	sn_irq_info->irq_last_intr) {
	397	regval &= ~(sn_irq_info->irq_int_bit & regval);
	398	sn_call_force_intr_provider(sn_irq_info);
1da177e4 LT	399	}
	400	}
	401	}
	402	sn_irq_info->irq_last_intr = regval;
	403	}
	404
	405	void sn_lb_int_war_check(void)
	406	{
cb4cb2cb	407	struct sn_irq_info *sn_irq_info;
1da177e4 LT	408	int i;
	409
	410	if (!sn_ioif_inited \|\| pda->sn_first_irq == 0)
	411	return;
cb4cb2cb PB	412
cb4cb2cb PB	413	rcu_read_lock();
1da177e4	414	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
cb4cb2cb	415	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
735e60f4	416	sn_check_intr(i, sn_irq_info);
1da177e4 LT	417	}
1da177e4 LT	418	}
cb4cb2cb PB	419	rcu_read_unlock();
	420	}
	421
	422	void sn_irq_lh_init(void)
	423	{
	424	int i;
	425
	426	sn_irq_lh = kmalloc(sizeof(struct list_head ) NR_IRQS, GFP_KERNEL);
	427	if (!sn_irq_lh)
	428	panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
	429
	430	for (i = 0; i < NR_IRQS; i++) {
	431	sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
	432	if (!sn_irq_lh[i])
	433	panic("SN PCI INIT: Failed IRQ memory allocation\n");
	434
	435	INIT_LIST_HEAD(sn_irq_lh[i]);
	436	}
	437
1da177e4	438	}