[deliverable/linux.git] / arch / ia64 / sn / pci / pci_dma.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
 *
 * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
 * a description of how these routines should be used.
 */

#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <asm/dma.h>
#include <asm/sn/intr.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/sn_sal.h>

#define SG_ENT_VIRT_ADDRESS(sg)	(sg_virt((sg)))
#define SG_ENT_PHYS_ADDRESS(SG)	virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))

/**
 * sn_dma_supported - test a DMA mask
 * @dev: device to test
 * @mask: DMA mask to test
 *
 * Return whether the given PCI device DMA address mask can be supported
 * properly.  For example, if your device can only drive the low 24-bits
 * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
 * this function.  Of course, SN only supports devices that have 32 or more
 * address bits when using the PMU.
 */
static int sn_dma_supported(struct device *dev, u64 mask)
{
	BUG_ON(dev->bus != &pci_bus_type);

	if (mask < 0x7fffffff)
		return 0;
	return 1;
}

/**
 * sn_dma_set_mask - set the DMA mask
 * @dev: device to set
 * @dma_mask: new mask
 *
 * Set @dev's DMA mask if the hw supports it.
 */
int sn_dma_set_mask(struct device *dev, u64 dma_mask)
{
	BUG_ON(dev->bus != &pci_bus_type);

	if (!sn_dma_supported(dev, dma_mask))
		return 0;

	*dev->dma_mask = dma_mask;
	return 1;
}
EXPORT_SYMBOL(sn_dma_set_mask);

/**
 * sn_dma_alloc_coherent - allocate memory for coherent DMA
 * @dev: device to allocate for
 * @size: size of the region
 * @dma_handle: DMA (bus) address
 * @flags: memory allocation flags
 *
 * dma_alloc_coherent() returns a pointer to a memory region suitable for
 * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
 * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
 *
 * This interface is usually used for "command" streams (e.g. the command
 * queue for a SCSI controller).  See Documentation/DMA-API.txt for
 * more information.
 */
static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
				   dma_addr_t * dma_handle, gfp_t flags)
{
	void *cpuaddr;
	unsigned long phys_addr;
	int node;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);

	BUG_ON(dev->bus != &pci_bus_type);

	/*
	 * Allocate the memory.
	 */
	node = pcibus_to_node(pdev->bus);
	if (likely(node >=0)) {
		struct page *p = alloc_pages_node(node, flags, get_order(size));

		if (likely(p))
			cpuaddr = page_address(p);
		else
			return NULL;
	} else
		cpuaddr = (void *)__get_free_pages(flags, get_order(size));

	if (unlikely(!cpuaddr))
		return NULL;

	memset(cpuaddr, 0x0, size);

	/* physical addr. of the memory we just got */
	phys_addr = __pa(cpuaddr);

	/*
	 * 64 bit address translations should never fail.
	 * 32 bit translations can fail if there are insufficient mapping
	 * resources.
	 */

	*dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
						   SN_DMA_ADDR_PHYS);
	if (!*dma_handle) {
		printk(KERN_ERR "%s: out of ATEs\n", __func__);
		free_pages((unsigned long)cpuaddr, get_order(size));
		return NULL;
	}

	return cpuaddr;
}

/**
 * sn_pci_free_coherent - free memory associated with coherent DMAable region
 * @dev: device to free for
 * @size: size to free
 * @cpu_addr: kernel virtual address to free
 * @dma_handle: DMA address associated with this region
 *
 * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
 * any associated IOMMU mappings.
 */
static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
				 dma_addr_t dma_handle)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);

	BUG_ON(dev->bus != &pci_bus_type);

	provider->dma_unmap(pdev, dma_handle, 0);
	free_pages((unsigned long)cpu_addr, get_order(size));
}

/**
 * sn_dma_map_single_attrs - map a single page for DMA
 * @dev: device to map for
 * @cpu_addr: kernel virtual address of the region to map
 * @size: size of the region
 * @direction: DMA direction
 * @attrs: optional dma attributes
 *
 * Map the region pointed to by @cpu_addr for DMA and return the
 * DMA address.
 *
 * We map this to the one step pcibr_dmamap_trans interface rather than
 * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
 * no way of saving the dmamap handle from the alloc to later free
 * (which is pretty much unacceptable).
 *
 * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
 * dma_map_consistent() so that writes force a flush of pending DMA.
 * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
 * Document Number: 007-4763-001)
 *
 * TODO: simplify our interface;
 *       figure out how to save dmamap handle so can use two step.
 */
static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page,
				  unsigned long offset, size_t size,
				  enum dma_data_direction dir,
				  struct dma_attrs *attrs)
{
	void *cpu_addr = page_address(page) + offset;
	dma_addr_t dma_addr;
	unsigned long phys_addr;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
	int dmabarr;

	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);

	BUG_ON(dev->bus != &pci_bus_type);

	phys_addr = __pa(cpu_addr);
	if (dmabarr)
		dma_addr = provider->dma_map_consistent(pdev, phys_addr,
							size, SN_DMA_ADDR_PHYS);
	else
		dma_addr = provider->dma_map(pdev, phys_addr, size,
					     SN_DMA_ADDR_PHYS);

	if (!dma_addr) {
		printk(KERN_ERR "%s: out of ATEs\n", __func__);
		return 0;
	}
	return dma_addr;
}

/**
 * sn_dma_unmap_single_attrs - unamp a DMA mapped page
 * @dev: device to sync
 * @dma_addr: DMA address to sync
 * @size: size of region
 * @direction: DMA direction
 * @attrs: optional dma attributes
 *
 * This routine is supposed to sync the DMA region specified
 * by @dma_handle into the coherence domain.  On SN, we're always cache
 * coherent, so we just need to free any ATEs associated with this mapping.
 */
static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
			      size_t size, enum dma_data_direction dir,
			      struct dma_attrs *attrs)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);

	BUG_ON(dev->bus != &pci_bus_type);

	provider->dma_unmap(pdev, dma_addr, dir);
}

/**
 * sn_dma_unmap_sg - unmap a DMA scatterlist
 * @dev: device to unmap
 * @sg: scatterlist to unmap
 * @nhwentries: number of scatterlist entries
 * @direction: DMA direction
 * @attrs: optional dma attributes
 *
 * Unmap a set of streaming mode DMA translations.
 */
static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
			    int nhwentries, enum dma_data_direction dir,
			    struct dma_attrs *attrs)
{
	int i;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
	struct scatterlist *sg;

	BUG_ON(dev->bus != &pci_bus_type);

	for_each_sg(sgl, sg, nhwentries, i) {
		provider->dma_unmap(pdev, sg->dma_address, dir);
		sg->dma_address = (dma_addr_t) NULL;
		sg->dma_length = 0;
	}
}

/**
 * sn_dma_map_sg - map a scatterlist for DMA
 * @dev: device to map for
 * @sg: scatterlist to map
 * @nhwentries: number of entries
 * @direction: direction of the DMA transaction
 * @attrs: optional dma attributes
 *
 * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
 * dma_map_consistent() so that writes force a flush of pending DMA.
 * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
 * Document Number: 007-4763-001)
 *
 * Maps each entry of @sg for DMA.
 */
static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
			 int nhwentries, enum dma_data_direction dir,
			 struct dma_attrs *attrs)
{
	unsigned long phys_addr;
	struct scatterlist *saved_sg = sgl, *sg;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
	int i;
	int dmabarr;

	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);

	BUG_ON(dev->bus != &pci_bus_type);

	/*
	 * Setup a DMA address for each entry in the scatterlist.
	 */
	for_each_sg(sgl, sg, nhwentries, i) {
		dma_addr_t dma_addr;
		phys_addr = SG_ENT_PHYS_ADDRESS(sg);
		if (dmabarr)
			dma_addr = provider->dma_map_consistent(pdev,
								phys_addr,
								sg->length,
								SN_DMA_ADDR_PHYS);
		else
			dma_addr = provider->dma_map(pdev, phys_addr,
						     sg->length,
						     SN_DMA_ADDR_PHYS);

		sg->dma_address = dma_addr;
		if (!sg->dma_address) {
			printk(KERN_ERR "%s: out of ATEs\n", __func__);

			/*
			 * Free any successfully allocated entries.
			 */
			if (i > 0)
				sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs);
			return 0;
		}

		sg->dma_length = sg->length;
	}

	return nhwentries;
}

static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
				       size_t size, enum dma_data_direction dir)
{
	BUG_ON(dev->bus != &pci_bus_type);
}

static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
					  size_t size,
					  enum dma_data_direction dir)
{
	BUG_ON(dev->bus != &pci_bus_type);
}

static void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
				   int nelems, enum dma_data_direction dir)
{
	BUG_ON(dev->bus != &pci_bus_type);
}

static void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
				      int nelems, enum dma_data_direction dir)
{
	BUG_ON(dev->bus != &pci_bus_type);
}

static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return 0;
}

u64 sn_dma_get_required_mask(struct device *dev)
{
	return DMA_64BIT_MASK;
}
EXPORT_SYMBOL_GPL(sn_dma_get_required_mask);

char *sn_pci_get_legacy_mem(struct pci_bus *bus)
{
	if (!SN_PCIBUS_BUSSOFT(bus))
		return ERR_PTR(-ENODEV);

	return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
}

int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
{
	unsigned long addr;
	int ret;
	struct ia64_sal_retval isrv;

	/*
	 * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
	 * around hw issues at the pci bus level.  SGI proms older than
	 * 4.10 don't implement this.
	 */

	SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
		 pci_domain_nr(bus), bus->number,
		 0, /* io */
		 0, /* read */
		 port, size, __pa(val));

	if (isrv.status == 0)
		return size;

	/*
	 * If the above failed, retry using the SAL_PROBE call which should
	 * be present in all proms (but which cannot work round PCI chipset
	 * bugs).  This code is retained for compatibility with old
	 * pre-4.10 proms, and should be removed at some point in the future.
	 */

	if (!SN_PCIBUS_BUSSOFT(bus))
		return -ENODEV;

	addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
	addr += port;

	ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);

	if (ret == 2)
		return -EINVAL;

	if (ret == 1)
		*val = -1;

	return size;
}

int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
{
	int ret = size;
	unsigned long paddr;
	unsigned long *addr;
	struct ia64_sal_retval isrv;

	/*
	 * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
	 * around hw issues at the pci bus level.  SGI proms older than
	 * 4.10 don't implement this.
	 */

	SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
		 pci_domain_nr(bus), bus->number,
		 0, /* io */
		 1, /* write */
		 port, size, __pa(&val));

	if (isrv.status == 0)
		return size;

	/*
	 * If the above failed, retry using the SAL_PROBE call which should
	 * be present in all proms (but which cannot work round PCI chipset
	 * bugs).  This code is retained for compatibility with old
	 * pre-4.10 proms, and should be removed at some point in the future.
	 */

	if (!SN_PCIBUS_BUSSOFT(bus)) {
		ret = -ENODEV;
		goto out;
	}

	/* Put the phys addr in uncached space */
	paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
	paddr += port;
	addr = (unsigned long *)paddr;

	switch (size) {
	case 1:
		*(volatile u8 *)(addr) = (u8)(val);
		break;
	case 2:
		*(volatile u16 *)(addr) = (u16)(val);
		break;
	case 4:
		*(volatile u32 *)(addr) = (u32)(val);
		break;
	default:
		ret = -EINVAL;
		break;
	}
 out:
	return ret;
}

static struct dma_map_ops sn_dma_ops = {
	.alloc_coherent		= sn_dma_alloc_coherent,
	.free_coherent		= sn_dma_free_coherent,
	.map_page		= sn_dma_map_page,
	.unmap_page		= sn_dma_unmap_page,
	.map_sg			= sn_dma_map_sg,
	.unmap_sg		= sn_dma_unmap_sg,
	.sync_single_for_cpu 	= sn_dma_sync_single_for_cpu,
	.sync_sg_for_cpu	= sn_dma_sync_sg_for_cpu,
	.sync_single_for_device = sn_dma_sync_single_for_device,
	.sync_sg_for_device	= sn_dma_sync_sg_for_device,
	.mapping_error		= sn_dma_mapping_error,
	.dma_supported		= sn_dma_supported,
};

void sn_dma_init(void)
{
	dma_ops = &sn_dma_ops;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
	7	*
	8	* Routines for PCI DMA mapping. See Documentation/DMA-API.txt for
	9	* a description of how these routines should be used.
	10	*/
	11
	12	#include <linux/module.h>
b4391dd1	13	#include <linux/dma-mapping.h>
1da177e4	14	#include <asm/dma.h>
83821d3f	15	#include <asm/sn/intr.h>
9b08ebd1 MM	16	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	17	#include <asm/sn/pcidev.h>
c13cf371	18	#include <asm/sn/sn_sal.h>
1da177e4	19
58b053e4	20	#define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg)))
1da177e4 LT	21	#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
	22
	23	/**
	24	* sn_dma_supported - test a DMA mask
	25	* @dev: device to test
	26	* @mask: DMA mask to test
	27	*
	28	* Return whether the given PCI device DMA address mask can be supported
	29	* properly. For example, if your device can only drive the low 24-bits
	30	* during PCI bus mastering, then you would pass 0x00ffffff as the mask to
	31	* this function. Of course, SN only supports devices that have 32 or more
	32	* address bits when using the PMU.
	33	*/
cdc28d59	34	static int sn_dma_supported(struct device *dev, u64 mask)
1da177e4 LT	35	{
	36	BUG_ON(dev->bus != &pci_bus_type);
	37
	38	if (mask < 0x7fffffff)
	39	return 0;
	40	return 1;
	41	}
1da177e4 LT	42
	43	/**
	44	* sn_dma_set_mask - set the DMA mask
	45	* @dev: device to set
	46	* @dma_mask: new mask
	47	*
	48	* Set @dev's DMA mask if the hw supports it.
	49	*/
	50	int sn_dma_set_mask(struct device *dev, u64 dma_mask)
	51	{
	52	BUG_ON(dev->bus != &pci_bus_type);
	53
	54	if (!sn_dma_supported(dev, dma_mask))
	55	return 0;
	56
	57	*dev->dma_mask = dma_mask;
	58	return 1;
	59	}
	60	EXPORT_SYMBOL(sn_dma_set_mask);
	61
	62	/**
	63	* sn_dma_alloc_coherent - allocate memory for coherent DMA
	64	* @dev: device to allocate for
	65	* @size: size of the region
	66	* @dma_handle: DMA (bus) address
	67	* @flags: memory allocation flags
	68	*
	69	* dma_alloc_coherent() returns a pointer to a memory region suitable for
	70	* coherent DMA traffic to/from a PCI device. On SN platforms, this means
	71	* that @dma_handle will have the %PCIIO_DMA_CMD flag set.
	72	*
	73	* This interface is usually used for "command" streams (e.g. the command
	74	* queue for a SCSI controller). See Documentation/DMA-API.txt for
	75	* more information.
	76	*/
cdc28d59 FT	77	static void sn_dma_alloc_coherent(struct device dev, size_t size,
cdc28d59 FT	78	dma_addr_t * dma_handle, gfp_t flags)
1da177e4 LT	79	{
	80	void *cpuaddr;
	81	unsigned long phys_addr;
7c2a6c62	82	int node;
e955d825 MM	83	struct pci_dev *pdev = to_pci_dev(dev);
e955d825 MM	84	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
1da177e4 LT	85
	86	BUG_ON(dev->bus != &pci_bus_type);
	87
	88	/*
	89	* Allocate the memory.
1da177e4	90	*/
7c2a6c62 CL	91	node = pcibus_to_node(pdev->bus);
7c2a6c62 CL	92	if (likely(node >=0)) {
dc641613	93	struct page *p = alloc_pages_node(node, flags, get_order(size));
7c2a6c62 CL	94
	95	if (likely(p))
	96	cpuaddr = page_address(p);
	97	else
	98	return NULL;
	99	} else
dc641613	100	cpuaddr = (void *)__get_free_pages(flags, get_order(size));
7c2a6c62 CL	101
7c2a6c62 CL	102	if (unlikely(!cpuaddr))
1da177e4 LT	103	return NULL;
	104
	105	memset(cpuaddr, 0x0, size);
	106
	107	/* physical addr. of the memory we just got */
	108	phys_addr = __pa(cpuaddr);
	109
	110	/*
	111	* 64 bit address translations should never fail.
	112	* 32 bit translations can fail if there are insufficient mapping
	113	* resources.
	114	*/
	115
83821d3f MM	116	*dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
83821d3f MM	117	SN_DMA_ADDR_PHYS);
1da177e4	118	if (!*dma_handle) {
d4ed8084	119	printk(KERN_ERR "%s: out of ATEs\n", __func__);
1da177e4 LT	120	free_pages((unsigned long)cpuaddr, get_order(size));
	121	return NULL;
	122	}
	123
	124	return cpuaddr;
	125	}
1da177e4 LT	126
	127	/**
	128	* sn_pci_free_coherent - free memory associated with coherent DMAable region
	129	* @dev: device to free for
	130	* @size: size to free
	131	* @cpu_addr: kernel virtual address to free
	132	* @dma_handle: DMA address associated with this region
	133	*
	134	* Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
	135	* any associated IOMMU mappings.
	136	*/
cdc28d59 FT	137	static void sn_dma_free_coherent(struct device dev, size_t size, void cpu_addr,
cdc28d59 FT	138	dma_addr_t dma_handle)
1da177e4	139	{
e955d825 MM	140	struct pci_dev *pdev = to_pci_dev(dev);
e955d825 MM	141	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
1da177e4 LT	142
	143	BUG_ON(dev->bus != &pci_bus_type);
	144
e955d825	145	provider->dma_unmap(pdev, dma_handle, 0);
1da177e4 LT	146	free_pages((unsigned long)cpu_addr, get_order(size));
1da177e4 LT	147	}
1da177e4 LT	148
1da177e4 LT	149	/**
309df0c5	150	* sn_dma_map_single_attrs - map a single page for DMA
1da177e4 LT	151	* @dev: device to map for
	152	* @cpu_addr: kernel virtual address of the region to map
	153	* @size: size of the region
	154	* @direction: DMA direction
309df0c5	155	* @attrs: optional dma attributes
1da177e4 LT	156	*
	157	* Map the region pointed to by @cpu_addr for DMA and return the
	158	* DMA address.
	159	*
	160	* We map this to the one step pcibr_dmamap_trans interface rather than
	161	* the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
	162	* no way of saving the dmamap handle from the alloc to later free
	163	* (which is pretty much unacceptable).
	164	*
309df0c5 AK	165	* mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
	166	* dma_map_consistent() so that writes force a flush of pending DMA.
	167	* (See "SGI Altix Architecture Considerations for Linux Device Drivers",
	168	* Document Number: 007-4763-001)
	169	*
1da177e4 LT	170	* TODO: simplify our interface;
	171	* figure out how to save dmamap handle so can use two step.
	172	*/
160c1d8e FT	173	static dma_addr_t sn_dma_map_page(struct device dev, struct page page,
	174	unsigned long offset, size_t size,
	175	enum dma_data_direction dir,
	176	struct dma_attrs *attrs)
1da177e4	177	{
160c1d8e	178	void *cpu_addr = page_address(page) + offset;
1da177e4 LT	179	dma_addr_t dma_addr;
1da177e4 LT	180	unsigned long phys_addr;
e955d825 MM	181	struct pci_dev *pdev = to_pci_dev(dev);
e955d825 MM	182	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
309df0c5 AK	183	int dmabarr;
	184
	185	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
1da177e4 LT	186
	187	BUG_ON(dev->bus != &pci_bus_type);
	188
	189	phys_addr = __pa(cpu_addr);
309df0c5 AK	190	if (dmabarr)
	191	dma_addr = provider->dma_map_consistent(pdev, phys_addr,
	192	size, SN_DMA_ADDR_PHYS);
	193	else
	194	dma_addr = provider->dma_map(pdev, phys_addr, size,
	195	SN_DMA_ADDR_PHYS);
	196
1da177e4	197	if (!dma_addr) {
d4ed8084	198	printk(KERN_ERR "%s: out of ATEs\n", __func__);
1da177e4 LT	199	return 0;
	200	}
	201	return dma_addr;
	202	}
1da177e4 LT	203
1da177e4 LT	204	/**
309df0c5	205	* sn_dma_unmap_single_attrs - unamp a DMA mapped page
1da177e4 LT	206	* @dev: device to sync
	207	* @dma_addr: DMA address to sync
	208	* @size: size of region
	209	* @direction: DMA direction
309df0c5	210	* @attrs: optional dma attributes
1da177e4 LT	211	*
	212	* This routine is supposed to sync the DMA region specified
	213	* by @dma_handle into the coherence domain. On SN, we're always cache
	214	* coherent, so we just need to free any ATEs associated with this mapping.
	215	*/
160c1d8e FT	216	static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
	217	size_t size, enum dma_data_direction dir,
	218	struct dma_attrs *attrs)
1da177e4	219	{
e955d825 MM	220	struct pci_dev *pdev = to_pci_dev(dev);
e955d825 MM	221	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
1da177e4 LT	222
1da177e4 LT	223	BUG_ON(dev->bus != &pci_bus_type);
e955d825	224
160c1d8e	225	provider->dma_unmap(pdev, dma_addr, dir);
1da177e4	226	}
1da177e4 LT	227
1da177e4 LT	228	/**
160c1d8e	229	* sn_dma_unmap_sg - unmap a DMA scatterlist
1da177e4 LT	230	* @dev: device to unmap
	231	* @sg: scatterlist to unmap
	232	* @nhwentries: number of scatterlist entries
	233	* @direction: DMA direction
309df0c5	234	* @attrs: optional dma attributes
1da177e4 LT	235	*
	236	* Unmap a set of streaming mode DMA translations.
	237	*/
160c1d8e FT	238	static void sn_dma_unmap_sg(struct device dev, struct scatterlist sgl,
	239	int nhwentries, enum dma_data_direction dir,
	240	struct dma_attrs *attrs)
1da177e4 LT	241	{
1da177e4 LT	242	int i;
e955d825 MM	243	struct pci_dev *pdev = to_pci_dev(dev);
e955d825 MM	244	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
9b6eccfc	245	struct scatterlist *sg;
1da177e4 LT	246
	247	BUG_ON(dev->bus != &pci_bus_type);
	248
9b6eccfc	249	for_each_sg(sgl, sg, nhwentries, i) {
160c1d8e	250	provider->dma_unmap(pdev, sg->dma_address, dir);
1da177e4 LT	251	sg->dma_address = (dma_addr_t) NULL;
	252	sg->dma_length = 0;
	253	}
	254	}
1da177e4 LT	255
1da177e4 LT	256	/**
160c1d8e	257	* sn_dma_map_sg - map a scatterlist for DMA
1da177e4 LT	258	* @dev: device to map for
	259	* @sg: scatterlist to map
	260	* @nhwentries: number of entries
	261	* @direction: direction of the DMA transaction
309df0c5 AK	262	* @attrs: optional dma attributes
	263	*
	264	* mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
	265	* dma_map_consistent() so that writes force a flush of pending DMA.
	266	* (See "SGI Altix Architecture Considerations for Linux Device Drivers",
	267	* Document Number: 007-4763-001)
1da177e4 LT	268	*
	269	* Maps each entry of @sg for DMA.
	270	*/
160c1d8e FT	271	static int sn_dma_map_sg(struct device dev, struct scatterlist sgl,
	272	int nhwentries, enum dma_data_direction dir,
	273	struct dma_attrs *attrs)
1da177e4 LT	274	{
1da177e4 LT	275	unsigned long phys_addr;
9b6eccfc	276	struct scatterlist saved_sg = sgl, sg;
e955d825 MM	277	struct pci_dev *pdev = to_pci_dev(dev);
e955d825 MM	278	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
1da177e4	279	int i;
309df0c5 AK	280	int dmabarr;
	281
	282	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
1da177e4 LT	283
	284	BUG_ON(dev->bus != &pci_bus_type);
	285
	286	/*
	287	* Setup a DMA address for each entry in the scatterlist.
	288	*/
9b6eccfc	289	for_each_sg(sgl, sg, nhwentries, i) {
309df0c5	290	dma_addr_t dma_addr;
1da177e4	291	phys_addr = SG_ENT_PHYS_ADDRESS(sg);
309df0c5 AK	292	if (dmabarr)
	293	dma_addr = provider->dma_map_consistent(pdev,
	294	phys_addr,
	295	sg->length,
	296	SN_DMA_ADDR_PHYS);
	297	else
	298	dma_addr = provider->dma_map(pdev, phys_addr,
	299	sg->length,
	300	SN_DMA_ADDR_PHYS);
1da177e4	301
309df0c5	302	sg->dma_address = dma_addr;
1da177e4	303	if (!sg->dma_address) {
d4ed8084	304	printk(KERN_ERR "%s: out of ATEs\n", __func__);
1da177e4 LT	305
	306	/*
	307	* Free any successfully allocated entries.
	308	*/
	309	if (i > 0)
160c1d8e	310	sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs);
1da177e4 LT	311	return 0;
	312	}
	313
	314	sg->dma_length = sg->length;
	315	}
	316
	317	return nhwentries;
	318	}
1da177e4	319
cdc28d59	320	static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
160c1d8e	321	size_t size, enum dma_data_direction dir)
1da177e4 LT	322	{
	323	BUG_ON(dev->bus != &pci_bus_type);
	324	}
1da177e4	325
cdc28d59	326	static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
160c1d8e FT	327	size_t size,
160c1d8e FT	328	enum dma_data_direction dir)
1da177e4 LT	329	{
	330	BUG_ON(dev->bus != &pci_bus_type);
	331	}
1da177e4	332
cdc28d59	333	static void sn_dma_sync_sg_for_cpu(struct device dev, struct scatterlist sg,
160c1d8e	334	int nelems, enum dma_data_direction dir)
1da177e4 LT	335	{
	336	BUG_ON(dev->bus != &pci_bus_type);
	337	}
1da177e4	338
cdc28d59	339	static void sn_dma_sync_sg_for_device(struct device dev, struct scatterlist sg,
160c1d8e	340	int nelems, enum dma_data_direction dir)
1da177e4 LT	341	{
	342	BUG_ON(dev->bus != &pci_bus_type);
	343	}
1da177e4	344
cdc28d59	345	static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
1da177e4 LT	346	{
	347	return 0;
	348	}
1da177e4	349
175add19 JK	350	u64 sn_dma_get_required_mask(struct device *dev)
	351	{
	352	return DMA_64BIT_MASK;
	353	}
	354	EXPORT_SYMBOL_GPL(sn_dma_get_required_mask);
	355
1da177e4 LT	356	char sn_pci_get_legacy_mem(struct pci_bus bus)
	357	{
	358	if (!SN_PCIBUS_BUSSOFT(bus))
	359	return ERR_PTR(-ENODEV);
	360
	361	return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem \| __IA64_UNCACHED_OFFSET);
	362	}
	363
	364	int sn_pci_legacy_read(struct pci_bus bus, u16 port, u32 val, u8 size)
	365	{
	366	unsigned long addr;
	367	int ret;
61b9cf7c MM	368	struct ia64_sal_retval isrv;
	369
	370	/*
	371	* First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
	372	* around hw issues at the pci bus level. SGI proms older than
72fdbdce	373	* 4.10 don't implement this.
61b9cf7c MM	374	*/
	375
	376	SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
8ed9b2c7 JS	377	pci_domain_nr(bus), bus->number,
	378	0, /* io */
	379	0, /* read */
	380	port, size, __pa(val));
61b9cf7c MM	381
	382	if (isrv.status == 0)
	383	return size;
	384
	385	/*
	386	* If the above failed, retry using the SAL_PROBE call which should
	387	* be present in all proms (but which cannot work round PCI chipset
72fdbdce	388	* bugs). This code is retained for compatibility with old
61b9cf7c MM	389	* pre-4.10 proms, and should be removed at some point in the future.
61b9cf7c MM	390	*/
1da177e4 LT	391
	392	if (!SN_PCIBUS_BUSSOFT(bus))
	393	return -ENODEV;
	394
	395	addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io \| __IA64_UNCACHED_OFFSET;
	396	addr += port;
	397
	398	ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
	399
	400	if (ret == 2)
	401	return -EINVAL;
	402
	403	if (ret == 1)
	404	*val = -1;
	405
	406	return size;
	407	}
	408
	409	int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
	410	{
	411	int ret = size;
	412	unsigned long paddr;
	413	unsigned long *addr;
61b9cf7c MM	414	struct ia64_sal_retval isrv;
	415
	416	/*
	417	* First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
	418	* around hw issues at the pci bus level. SGI proms older than
72fdbdce	419	* 4.10 don't implement this.
61b9cf7c MM	420	*/
	421
	422	SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
8ed9b2c7 JS	423	pci_domain_nr(bus), bus->number,
	424	0, /* io */
	425	1, /* write */
	426	port, size, __pa(&val));
61b9cf7c MM	427
	428	if (isrv.status == 0)
	429	return size;
	430
	431	/*
	432	* If the above failed, retry using the SAL_PROBE call which should
	433	* be present in all proms (but which cannot work round PCI chipset
72fdbdce	434	* bugs). This code is retained for compatibility with old
61b9cf7c MM	435	* pre-4.10 proms, and should be removed at some point in the future.
61b9cf7c MM	436	*/
1da177e4 LT	437
	438	if (!SN_PCIBUS_BUSSOFT(bus)) {
	439	ret = -ENODEV;
	440	goto out;
	441	}
	442
	443	/* Put the phys addr in uncached space */
	444	paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io \| __IA64_UNCACHED_OFFSET;
	445	paddr += port;
	446	addr = (unsigned long *)paddr;
	447
	448	switch (size) {
	449	case 1:
	450	(volatile u8 )(addr) = (u8)(val);
	451	break;
	452	case 2:
	453	(volatile u16 )(addr) = (u16)(val);
	454	break;
	455	case 4:
	456	(volatile u32 )(addr) = (u32)(val);
	457	break;
	458	default:
	459	ret = -EINVAL;
	460	break;
	461	}
	462	out:
	463	return ret;
	464	}
b4391dd1	465
160c1d8e	466	static struct dma_map_ops sn_dma_ops = {
b4391dd1 FT	467	.alloc_coherent = sn_dma_alloc_coherent,
b4391dd1 FT	468	.free_coherent = sn_dma_free_coherent,
160c1d8e FT	469	.map_page = sn_dma_map_page,
	470	.unmap_page = sn_dma_unmap_page,
	471	.map_sg = sn_dma_map_sg,
	472	.unmap_sg = sn_dma_unmap_sg,
b4391dd1 FT	473	.sync_single_for_cpu = sn_dma_sync_single_for_cpu,
	474	.sync_sg_for_cpu = sn_dma_sync_sg_for_cpu,
	475	.sync_single_for_device = sn_dma_sync_single_for_device,
	476	.sync_sg_for_device = sn_dma_sync_sg_for_device,
	477	.mapping_error = sn_dma_mapping_error,
160c1d8e	478	.dma_supported = sn_dma_supported,
b4391dd1	479	};
4d9b977c FT	480
	481	void sn_dma_init(void)
	482	{
	483	dma_ops = &sn_dma_ops;
	484	}