[deliverable/linux.git] / arch / ia64 / sn / pci / pcibr / pcibr_provider.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/sn/addrs.h>
#include <asm/sn/geo.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/sn2/sn_hwperf.h>
#include "xtalk/xwidgetdev.h"
#include "xtalk/hubdev.h"

int
sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	u64 segment;

	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
			busnum, (u64) device, (u64) resp, 0, 0, 0);

	return (int)ret_stuff.v0;
}

int
sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
		       void *resp)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	u64 segment;

	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
			segment, busnum, (u64) device, (u64) action,
			(u64) resp, 0, 0);

	return (int)ret_stuff.v0;
}

static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	int segment;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff,
			(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
			(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);

	return (int)ret_stuff.v0;
}

/* 
 * PCI Bridge Error interrupt handler.  Gets invoked whenever a PCI 
 * bridge sends an error interrupt.
 */
static irqreturn_t
pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *regs)
{
	struct pcibus_info *soft = (struct pcibus_info *)arg;

	if (sal_pcibr_error_interrupt(soft) < 0) {
		panic("pcibr_error_intr_handler(): Fatal Bridge Error");
	}
	return IRQ_HANDLED;
}

void *
pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
{
	int nasid, cnode, j;
	cnodeid_t near_cnode;
	struct hubdev_info *hubdev_info;
	struct pcibus_info *soft;
	struct sn_flush_device_kernel *sn_flush_device_kernel;
	struct sn_flush_device_common *common;

	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
		return NULL;
	}

	/*
	 * Allocate kernel bus soft and copy from prom.
	 */

	soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
	if (!soft) {
		return NULL;
	}

	memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
	soft->pbi_buscommon.bs_base =
	    (((u64) soft->pbi_buscommon.
	      bs_base << 4) >> 4) | __IA64_UNCACHED_OFFSET;

	spin_lock_init(&soft->pbi_lock);

	/*
	 * register the bridge's error interrupt handler
	 */
	if (request_irq(SGI_PCIASIC_ERROR, (void *)pcibr_error_intr_handler,
			SA_SHIRQ, "PCIBR error", (void *)(soft))) {
		printk(KERN_WARNING
		       "pcibr cannot allocate interrupt for error handler\n");
	}

	/* 
	 * Update the Bridge with the "kernel" pagesize 
	 */
	if (PAGE_SIZE < 16384) {
		pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
	} else {
		pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
	}

	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
	cnode = nasid_to_cnodeid(nasid);
	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);

	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
		sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
		    widget_p[(int)soft->pbi_buscommon.bs_xid];
		if (sn_flush_device_kernel) {
			for (j = 0; j < DEV_PER_WIDGET;
			     j++, sn_flush_device_kernel++) {
				common = sn_flush_device_kernel->common;
				if (common->sfdl_slot == -1)
					continue;
				if ((common->sfdl_persistent_segment ==
				     soft->pbi_buscommon.bs_persist_segment) &&
				     (common->sfdl_persistent_busnum ==
				     soft->pbi_buscommon.bs_persist_busnum))
					common->sfdl_pcibus_info =
					    soft;
			}
		}
	}

	/* Setup the PMU ATE map */
	soft->pbi_int_ate_resource.lowest_free_index = 0;
	soft->pbi_int_ate_resource.ate =
	    kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);

	if (!soft->pbi_int_ate_resource.ate) {
		kfree(soft);
		return NULL;
	}

	if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
		/* TIO PCI Bridge: find nearest node with CPUs */
		int e = sn_hwperf_get_nearest_node(cnode, NULL, &near_cnode);

		if (e < 0) {
			near_cnode = (cnodeid_t)-1; /* use any node */
			printk(KERN_WARNING "pcibr_bus_fixup: failed to find "
				"near node with CPUs to TIO node %d, err=%d\n",
				cnode, e);
		}
		controller->node = near_cnode;
	}
	else
		controller->node = cnode;
	return soft;
}

void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
{
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;
	int bit = sn_irq_info->irq_int_bit;

	if (! sn_irq_info->irq_bridge)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (pcidev_info) {
		pcibus_info =
		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
		    pdi_pcibus_info;
		pcireg_force_intr_set(pcibus_info, bit);
	}
}

void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
{
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;
	int bit = sn_irq_info->irq_int_bit;
	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (pcidev_info) {
		pcibus_info =
		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
		    pdi_pcibus_info;

		/* Disable the device's IRQ   */
		pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));

		/* Change the device's IRQ    */
		pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);

		/* Re-enable the device's IRQ */
		pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));

		pcibr_force_interrupt(sn_irq_info);
	}
}

/*
 * Provider entries for PIC/CP
 */

struct sn_pcibus_provider pcibr_provider = {
	.dma_map = pcibr_dma_map,
	.dma_map_consistent = pcibr_dma_map_consistent,
	.dma_unmap = pcibr_dma_unmap,
	.bus_fixup = pcibr_bus_fixup,
	.force_interrupt = pcibr_force_interrupt,
	.target_interrupt = pcibr_target_interrupt
};

int
pcibr_init_provider(void)
{
	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;

	return 0;
}

EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
	7	*/
	8
1da177e4	9	#include <linux/interrupt.h>
c13cf371	10	#include <linux/types.h>
1da177e4	11	#include <linux/pci.h>
c13cf371	12	#include <asm/sn/addrs.h>
1da177e4	13	#include <asm/sn/geo.h>
c13cf371	14	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	15	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	16	#include <asm/sn/pcidev.h>
c13cf371	17	#include <asm/sn/sn_sal.h>
5390970d	18	#include <asm/sn/sn2/sn_hwperf.h>
c13cf371 PB	19	#include "xtalk/xwidgetdev.h"
c13cf371 PB	20	#include "xtalk/hubdev.h"
1da177e4	21
6f354b01 PB	22	int
	23	sal_pcibr_slot_enable(struct pcibus_info soft, int device, void resp)
	24	{
	25	struct ia64_sal_retval ret_stuff;
53493dcf	26	u64 busnum;
ac354a89	27	u64 segment;
6f354b01 PB	28
	29	ret_stuff.status = 0;
	30	ret_stuff.v0 = 0;
	31
ac354a89	32	segment = soft->pbi_buscommon.bs_persist_segment;
6f354b01	33	busnum = soft->pbi_buscommon.bs_persist_busnum;
ac354a89 MH	34	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
ac354a89 MH	35	busnum, (u64) device, (u64) resp, 0, 0, 0);
6f354b01 PB	36
	37	return (int)ret_stuff.v0;
	38	}
	39
	40	int
	41	sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
	42	void *resp)
	43	{
	44	struct ia64_sal_retval ret_stuff;
53493dcf	45	u64 busnum;
ac354a89	46	u64 segment;
6f354b01 PB	47
	48	ret_stuff.status = 0;
	49	ret_stuff.v0 = 0;
	50
ac354a89	51	segment = soft->pbi_buscommon.bs_persist_segment;
6f354b01 PB	52	busnum = soft->pbi_buscommon.bs_persist_busnum;
6f354b01 PB	53	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
ac354a89 MH	54	segment, busnum, (u64) device, (u64) action,
ac354a89 MH	55	(u64) resp, 0, 0);
6f354b01 PB	56
	57	return (int)ret_stuff.v0;
	58	}
	59
1da177e4 LT	60	static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
	61	{
	62	struct ia64_sal_retval ret_stuff;
53493dcf	63	u64 busnum;
1da177e4 LT	64	int segment;
	65	ret_stuff.status = 0;
	66	ret_stuff.v0 = 0;
	67
674c6479	68	segment = soft->pbi_buscommon.bs_persist_segment;
1da177e4 LT	69	busnum = soft->pbi_buscommon.bs_persist_busnum;
	70	SAL_CALL_NOLOCK(ret_stuff,
	71	(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
	72	(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
	73
	74	return (int)ret_stuff.v0;
	75	}
	76
	77	/*
	78	* PCI Bridge Error interrupt handler. Gets invoked whenever a PCI
	79	* bridge sends an error interrupt.
	80	*/
	81	static irqreturn_t
	82	pcibr_error_intr_handler(int irq, void arg, struct pt_regs regs)
	83	{
	84	struct pcibus_info soft = (struct pcibus_info )arg;
	85
	86	if (sal_pcibr_error_interrupt(soft) < 0) {
	87	panic("pcibr_error_intr_handler(): Fatal Bridge Error");
	88	}
	89	return IRQ_HANDLED;
	90	}
	91
	92	void *
7c2a6c62	93	pcibr_bus_fixup(struct pcibus_bussoft prom_bussoft, struct pci_controller controller)
1da177e4 LT	94	{
1da177e4 LT	95	int nasid, cnode, j;
5390970d	96	cnodeid_t near_cnode;
1da177e4 LT	97	struct hubdev_info *hubdev_info;
1da177e4 LT	98	struct pcibus_info *soft;
6d6e4200 PB	99	struct sn_flush_device_kernel *sn_flush_device_kernel;
6d6e4200 PB	100	struct sn_flush_device_common *common;
1da177e4 LT	101
	102	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
	103	return NULL;
	104	}
	105
	106	/*
	107	* Allocate kernel bus soft and copy from prom.
	108	*/
	109
	110	soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
	111	if (!soft) {
	112	return NULL;
	113	}
	114
	115	memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
	116	soft->pbi_buscommon.bs_base =
	117	(((u64) soft->pbi_buscommon.
	118	bs_base << 4) >> 4) \| __IA64_UNCACHED_OFFSET;
	119
	120	spin_lock_init(&soft->pbi_lock);
	121
	122	/*
	123	* register the bridge's error interrupt handler
	124	*/
89963d16	125	if (request_irq(SGI_PCIASIC_ERROR, (void *)pcibr_error_intr_handler,
1da177e4 LT	126	SA_SHIRQ, "PCIBR error", (void *)(soft))) {
	127	printk(KERN_WARNING
	128	"pcibr cannot allocate interrupt for error handler\n");
	129	}
	130
	131	/*
	132	* Update the Bridge with the "kernel" pagesize
	133	*/
	134	if (PAGE_SIZE < 16384) {
	135	pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
	136	} else {
	137	pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
	138	}
	139
	140	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
	141	cnode = nasid_to_cnodeid(nasid);
	142	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
	143
	144	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
6d6e4200	145	sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
1da177e4	146	widget_p[(int)soft->pbi_buscommon.bs_xid];
6d6e4200	147	if (sn_flush_device_kernel) {
1da177e4	148	for (j = 0; j < DEV_PER_WIDGET;
6d6e4200 PB	149	j++, sn_flush_device_kernel++) {
	150	common = sn_flush_device_kernel->common;
	151	if (common->sfdl_slot == -1)
1da177e4	152	continue;
6d6e4200	153	if ((common->sfdl_persistent_segment ==
674c6479	154	soft->pbi_buscommon.bs_persist_segment) &&
6d6e4200	155	(common->sfdl_persistent_busnum ==
674c6479	156	soft->pbi_buscommon.bs_persist_busnum))
6d6e4200	157	common->sfdl_pcibus_info =
1da177e4 LT	158	soft;
	159	}
	160	}
	161	}
	162
	163	/* Setup the PMU ATE map */
	164	soft->pbi_int_ate_resource.lowest_free_index = 0;
	165	soft->pbi_int_ate_resource.ate =
8ed9b2c7 JS	166	kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
	167
	168	if (!soft->pbi_int_ate_resource.ate) {
	169	kfree(soft);
	170	return NULL;
	171	}
1da177e4	172
5390970d MG	173	if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
	174	/* TIO PCI Bridge: find nearest node with CPUs */
	175	int e = sn_hwperf_get_nearest_node(cnode, NULL, &near_cnode);
	176
	177	if (e < 0) {
	178	near_cnode = (cnodeid_t)-1; /* use any node */
	179	printk(KERN_WARNING "pcibr_bus_fixup: failed to find "
	180	"near node with CPUs to TIO node %d, err=%d\n",
	181	cnode, e);
	182	}
	183	controller->node = near_cnode;
	184	}
7c2a6c62 CL	185	else
7c2a6c62 CL	186	controller->node = cnode;
1da177e4 LT	187	return soft;
	188	}
	189
	190	void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
	191	{
	192	struct pcidev_info *pcidev_info;
	193	struct pcibus_info *pcibus_info;
	194	int bit = sn_irq_info->irq_int_bit;
	195
735e60f4 MM	196	if (! sn_irq_info->irq_bridge)
	197	return;
	198
1da177e4 LT	199	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	200	if (pcidev_info) {
	201	pcibus_info =
	202	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	203	pdi_pcibus_info;
	204	pcireg_force_intr_set(pcibus_info, bit);
	205	}
	206	}
	207
8409668b	208	void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
1da177e4 LT	209	{
	210	struct pcidev_info *pcidev_info;
	211	struct pcibus_info *pcibus_info;
	212	int bit = sn_irq_info->irq_int_bit;
53493dcf	213	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
1da177e4 LT	214
	215	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	216	if (pcidev_info) {
	217	pcibus_info =
	218	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	219	pdi_pcibus_info;
	220
	221	/* Disable the device's IRQ */
6fb93a92	222	pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
1da177e4 LT	223
	224	/* Change the device's IRQ */
	225	pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
	226
	227	/* Re-enable the device's IRQ */
6fb93a92	228	pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
1da177e4 LT	229
	230	pcibr_force_interrupt(sn_irq_info);
	231	}
	232	}
e955d825 MM	233
	234	/*
	235	* Provider entries for PIC/CP
	236	*/
	237
	238	struct sn_pcibus_provider pcibr_provider = {
	239	.dma_map = pcibr_dma_map,
	240	.dma_map_consistent = pcibr_dma_map_consistent,
	241	.dma_unmap = pcibr_dma_unmap,
	242	.bus_fixup = pcibr_bus_fixup,
8409668b MM	243	.force_interrupt = pcibr_force_interrupt,
8409668b MM	244	.target_interrupt = pcibr_target_interrupt
e955d825 MM	245	};
	246
	247	int
	248	pcibr_init_provider(void)
	249	{
	250	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
	251	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
	252
	253	return 0;
	254	}
6f354b01 PB	255
	256	EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
	257	EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);