[deliverable/linux.git] / arch / m32r / platforms / mappi3 / setup.c

/*
 *  linux/arch/m32r/platforms/mappi3/setup.c
 *
 *  Setup routines for Renesas MAPPI-III(M3A-2170) Board
 *
 *  Copyright (c) 2001-2005  Hiroyuki Kondo, Hirokazu Takata,
 *                           Hitoshi Yamamoto, Mamoru Sakugawa
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

icu_data_t icu_data[NR_IRQS];

static void disable_mappi3_irq(unsigned int irq)
{
	unsigned long port, data;

	if ((irq == 0) ||(irq >= NR_IRQS))  {
		printk("bad irq 0x%08x\n", irq);
		return;
	}
	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_mappi3_irq(unsigned int irq)
{
	unsigned long port, data;

	if ((irq == 0) ||(irq >= NR_IRQS))  {
		printk("bad irq 0x%08x\n", irq);
		return;
	}
	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_and_ack_mappi3(unsigned int irq)
{
	disable_mappi3_irq(irq);
}

static void end_mappi3_irq(unsigned int irq)
{
	enable_mappi3_irq(irq);
}

static unsigned int startup_mappi3_irq(unsigned int irq)
{
	enable_mappi3_irq(irq);
	return (0);
}

static void shutdown_mappi3_irq(unsigned int irq)
{
	unsigned long port;

	port = irq2port(irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct irq_chip mappi3_irq_type =
{
	.typename = "MAPPI3-IRQ",
	.startup = startup_mappi3_irq,
	.shutdown = shutdown_mappi3_irq,
	.enable = enable_mappi3_irq,
	.disable = disable_mappi3_irq,
	.ack = mask_and_ack_mappi3,
	.end = end_mappi3_irq
};

void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
	/* INT0 : LAN controller (SMC91111) */
	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_INT0].action = 0;
	irq_desc[M32R_IRQ_INT0].depth = 1;
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_mappi3_irq(M32R_IRQ_INT0);
#endif  /* CONFIG_SMC91X */

	/* MFT2 : system timer */
	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_MFT2].action = 0;
	irq_desc[M32R_IRQ_MFT2].depth = 1;
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_mappi3_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
	/* SIO0_R : uart receive data */
	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_mappi3_irq(M32R_IRQ_SIO0_R);

	/* SIO0_S : uart send data */
	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_mappi3_irq(M32R_IRQ_SIO0_S);
	/* SIO1_R : uart receive data */
	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_mappi3_irq(M32R_IRQ_SIO1_R);

	/* SIO1_S : uart send data */
	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_mappi3_irq(M32R_IRQ_SIO1_S);
#endif  /* CONFIG_M32R_USE_DBG_CONSOLE */

#if defined(CONFIG_USB)
	/* INT1 : USB Host controller interrupt */
	irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
	irq_desc[M32R_IRQ_INT1].action = 0;
	irq_desc[M32R_IRQ_INT1].depth = 1;
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
	disable_mappi3_irq(M32R_IRQ_INT1);
#endif /* CONFIG_USB */

	/* CFC IREQ */
	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type;
	irq_desc[PLD_IRQ_CFIREQ].action = 0;
	irq_desc[PLD_IRQ_CFIREQ].depth = 1;	/* disable nested irq */
	icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
	disable_mappi3_irq(PLD_IRQ_CFIREQ);

#if defined(CONFIG_M32R_CFC)
	/* ICUCR41: CFC Insert & eject */
	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type;
	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1;	/* disable nested irq */
	icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
	disable_mappi3_irq(PLD_IRQ_CFC_INSERT);

#endif /* CONFIG_M32R_CFC */

	/* IDE IREQ */
	irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type;
	irq_desc[PLD_IRQ_IDEIREQ].action = 0;
	irq_desc[PLD_IRQ_IDEIREQ].depth = 1;	/* disable nested irq */
	icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_mappi3_irq(PLD_IRQ_IDEIREQ);

}

#if defined(CONFIG_SMC91X)

#define LAN_IOSTART     0x300
#define LAN_IOEND       0x320
static struct resource smc91x_resources[] = {
	[0] = {
		.start  = (LAN_IOSTART),
		.end    = (LAN_IOEND),
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = M32R_IRQ_INT0,
		.end    = M32R_IRQ_INT0,
		.flags  = IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

#endif

#if defined(CONFIG_FB_S1D13XXX)

#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>

static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	.initregs		= s1d13xxxfb_initregs,
	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
	.platform_init_video	= NULL,
#ifdef CONFIG_PM
	.platform_suspend_video	= NULL,
	.platform_resume_video	= NULL,
#endif
};

static struct resource s1d13xxxfb_resources[] = {
	[0] = {
		.start  = 0x1d600000UL,
		.end    = 0x1d73FFFFUL,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 0x1d400000UL,
		.end    = 0x1d4001FFUL,
		.flags  = IORESOURCE_MEM,
	}
};

static struct platform_device s1d13xxxfb_device = {
	.name		= S1D_DEVICENAME,
	.id		= 0,
	.dev            = {
		.platform_data  = &s1d13xxxfb_data,
	},
	.num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
	.resource       = s1d13xxxfb_resources,
};
#endif

static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
	platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
	platform_device_register(&s1d13xxxfb_device);
#endif
	return 0;
}
arch_initcall(platform_init);
Commit	Line	Data
23680863	1	/*
3264f976	2	* linux/arch/m32r/platforms/mappi3/setup.c
23680863 HT	3	*
	4	* Setup routines for Renesas MAPPI-III(M3A-2170) Board
	5	*
316240f6 HT	6	* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
316240f6 HT	7	* Hitoshi Yamamoto, Mamoru Sakugawa
23680863 HT	8	*/
23680863 HT	9
23680863 HT	10	#include <linux/irq.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
d052d1be	13	#include <linux/platform_device.h>
23680863 HT	14
	15	#include <asm/system.h>
	16	#include <asm/m32r.h>
	17	#include <asm/io.h>
	18
	19	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	20
23680863 HT	21	icu_data_t icu_data[NR_IRQS];
	22
	23	static void disable_mappi3_irq(unsigned int irq)
	24	{
	25	unsigned long port, data;
	26
	27	if ((irq == 0) \|\|(irq >= NR_IRQS)) {
	28	printk("bad irq 0x%08x\n", irq);
	29	return;
	30	}
	31	port = irq2port(irq);
	32	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	33	outl(data, port);
	34	}
	35
	36	static void enable_mappi3_irq(unsigned int irq)
	37	{
	38	unsigned long port, data;
	39
	40	if ((irq == 0) \|\|(irq >= NR_IRQS)) {
	41	printk("bad irq 0x%08x\n", irq);
	42	return;
	43	}
	44	port = irq2port(irq);
	45	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	46	outl(data, port);
	47	}
	48
	49	static void mask_and_ack_mappi3(unsigned int irq)
	50	{
	51	disable_mappi3_irq(irq);
	52	}
	53
	54	static void end_mappi3_irq(unsigned int irq)
	55	{
	56	enable_mappi3_irq(irq);
	57	}
	58
	59	static unsigned int startup_mappi3_irq(unsigned int irq)
	60	{
	61	enable_mappi3_irq(irq);
	62	return (0);
	63	}
	64
	65	static void shutdown_mappi3_irq(unsigned int irq)
	66	{
	67	unsigned long port;
	68
	69	port = irq2port(irq);
	70	outl(M32R_ICUCR_ILEVEL7, port);
	71	}
	72
189e91f5	73	static struct irq_chip mappi3_irq_type =
23680863	74	{
6f973b00 HT	75	.typename = "MAPPI3-IRQ",
	76	.startup = startup_mappi3_irq,
	77	.shutdown = shutdown_mappi3_irq,
	78	.enable = enable_mappi3_irq,
	79	.disable = disable_mappi3_irq,
	80	.ack = mask_and_ack_mappi3,
	81	.end = end_mappi3_irq
23680863 HT	82	};
	83
	84	void __init init_IRQ(void)
	85	{
	86	#if defined(CONFIG_SMC91X)
	87	/* INT0 : LAN controller (SMC91111) */
	88	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
d1bef4ed	89	irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type;
23680863 HT	90	irq_desc[M32R_IRQ_INT0].action = 0;
	91	irq_desc[M32R_IRQ_INT0].depth = 1;
	92	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	93	disable_mappi3_irq(M32R_IRQ_INT0);
	94	#endif /* CONFIG_SMC91X */
	95
	96	/* MFT2 : system timer */
	97	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
d1bef4ed	98	irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type;
23680863 HT	99	irq_desc[M32R_IRQ_MFT2].action = 0;
	100	irq_desc[M32R_IRQ_MFT2].depth = 1;
	101	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	102	disable_mappi3_irq(M32R_IRQ_MFT2);
	103
	104	#ifdef CONFIG_SERIAL_M32R_SIO
	105	/* SIO0_R : uart receive data */
	106	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
d1bef4ed	107	irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type;
23680863 HT	108	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	109	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	110	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	111	disable_mappi3_irq(M32R_IRQ_SIO0_R);
	112
	113	/* SIO0_S : uart send data */
	114	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
d1bef4ed	115	irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type;
23680863 HT	116	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	117	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	118	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	119	disable_mappi3_irq(M32R_IRQ_SIO0_S);
	120	/* SIO1_R : uart receive data */
	121	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
d1bef4ed	122	irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type;
23680863 HT	123	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	124	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	125	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	126	disable_mappi3_irq(M32R_IRQ_SIO1_R);
	127
	128	/* SIO1_S : uart send data */
	129	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
d1bef4ed	130	irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type;
23680863 HT	131	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	132	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	133	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	134	disable_mappi3_irq(M32R_IRQ_SIO1_S);
	135	#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
	136
	137	#if defined(CONFIG_USB)
	138	/* INT1 : USB Host controller interrupt */
	139	irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
d1bef4ed	140	irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
23680863 HT	141	irq_desc[M32R_IRQ_INT1].action = 0;
	142	irq_desc[M32R_IRQ_INT1].depth = 1;
	143	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
	144	disable_mappi3_irq(M32R_IRQ_INT1);
	145	#endif /* CONFIG_USB */
	146
ad09d583	147	/* CFC IREQ */
23680863	148	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
d1bef4ed	149	irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type;
23680863 HT	150	irq_desc[PLD_IRQ_CFIREQ].action = 0;
	151	irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
	152	icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
	153	disable_mappi3_irq(PLD_IRQ_CFIREQ);
	154
	155	#if defined(CONFIG_M32R_CFC)
ad09d583	156	/* ICUCR41: CFC Insert & eject */
23680863	157	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
d1bef4ed	158	irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type;
23680863 HT	159	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
	160	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
	161	icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD00;
	162	disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
	163
23680863	164	#endif /* CONFIG_M32R_CFC */
ad09d583 HT	165
	166	/* IDE IREQ */
	167	irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED;
d1bef4ed	168	irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type;
ad09d583 HT	169	irq_desc[PLD_IRQ_IDEIREQ].action = 0;
	170	irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
	171	icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	172	disable_mappi3_irq(PLD_IRQ_IDEIREQ);
	173
23680863 HT	174	}
23680863 HT	175
316240f6 HT	176	#if defined(CONFIG_SMC91X)
316240f6 HT	177
23680863 HT	178	#define LAN_IOSTART 0x300
	179	#define LAN_IOEND 0x320
	180	static struct resource smc91x_resources[] = {
	181	[0] = {
	182	.start = (LAN_IOSTART),
	183	.end = (LAN_IOEND),
	184	.flags = IORESOURCE_MEM,
	185	},
	186	[1] = {
	187	.start = M32R_IRQ_INT0,
	188	.end = M32R_IRQ_INT0,
	189	.flags = IORESOURCE_IRQ,
	190	}
	191	};
	192
	193	static struct platform_device smc91x_device = {
	194	.name = "smc91x",
	195	.id = 0,
	196	.num_resources = ARRAY_SIZE(smc91x_resources),
	197	.resource = smc91x_resources,
	198	};
	199
316240f6 HT	200	#endif
	201
	202	#if defined(CONFIG_FB_S1D13XXX)
	203
	204	#include <video/s1d13xxxfb.h>
	205	#include <asm/s1d13806.h>
	206
	207	static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	208	.initregs = s1d13xxxfb_initregs,
	209	.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
	210	.platform_init_video = NULL,
	211	#ifdef CONFIG_PM
	212	.platform_suspend_video = NULL,
	213	.platform_resume_video = NULL,
	214	#endif
	215	};
	216
	217	static struct resource s1d13xxxfb_resources[] = {
	218	[0] = {
	219	.start = 0x1d600000UL,
	220	.end = 0x1d73FFFFUL,
	221	.flags = IORESOURCE_MEM,
	222	},
	223	[1] = {
	224	.start = 0x1d400000UL,
	225	.end = 0x1d4001FFUL,
	226	.flags = IORESOURCE_MEM,
	227	}
	228	};
	229
	230	static struct platform_device s1d13xxxfb_device = {
	231	.name = S1D_DEVICENAME,
	232	.id = 0,
	233	.dev = {
	234	.platform_data = &s1d13xxxfb_data,
	235	},
	236	.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
	237	.resource = s1d13xxxfb_resources,
	238	};
	239	#endif
	240
23680863 HT	241	static int __init platform_init(void)
23680863 HT	242	{
316240f6	243	#if defined(CONFIG_SMC91X)
23680863	244	platform_device_register(&smc91x_device);
316240f6 HT	245	#endif
	246	#if defined(CONFIG_FB_S1D13XXX)
	247	platform_device_register(&s1d13xxxfb_device);
	248	#endif
23680863 HT	249	return 0;
	250	}
	251	arch_initcall(platform_init);