[deliverable/linux.git] / arch / m32r / platforms / oaks32r / setup.c

/*
 *  linux/arch/m32r/platforms/oaks32r/setup.c
 *
 *  Setup routines for OAKS32R Board
 *
 *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
 *                           Hitoshi Yamamoto, Mamoru Sakugawa
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

icu_data_t icu_data[NR_IRQS];

static void disable_oaks32r_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_oaks32r_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_and_ack_mappi(unsigned int irq)
{
	disable_oaks32r_irq(irq);
}

static void end_oaks32r_irq(unsigned int irq)
{
	enable_oaks32r_irq(irq);
}

static unsigned int startup_oaks32r_irq(unsigned int irq)
{
	enable_oaks32r_irq(irq);
	return (0);
}

static void shutdown_oaks32r_irq(unsigned int irq)
{
	unsigned long port;

	port = irq2port(irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct irq_chip oaks32r_irq_type =
{
	.typename = "OAKS32R-IRQ",
	.startup = startup_oaks32r_irq,
	.shutdown = shutdown_oaks32r_irq,
	.enable = enable_oaks32r_irq,
	.disable = disable_oaks32r_irq,
	.ack = mask_and_ack_mappi,
	.end = end_oaks32r_irq
};

void __init init_IRQ(void)
{
	static int once = 0;

	if (once)
		return;
	else
		once++;

#ifdef CONFIG_NE2000
	/* INT3 : LAN controller (RTL8019AS) */
	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
	irq_desc[M32R_IRQ_INT3].action = 0;
	irq_desc[M32R_IRQ_INT3].depth = 1;
	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_oaks32r_irq(M32R_IRQ_INT3);
#endif /* CONFIG_M32R_NE2000 */

	/* MFT2 : system timer */
	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
	irq_desc[M32R_IRQ_MFT2].action = 0;
	irq_desc[M32R_IRQ_MFT2].depth = 1;
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_oaks32r_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
	/* SIO0_R : uart receive data */
	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO0_R);

	/* SIO0_S : uart send data */
	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO0_S);

	/* SIO1_R : uart receive data */
	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO1_R);

	/* SIO1_S : uart send data */
	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */
}
Commit	Line	Data
1da177e4	1	/*
3264f976	2	* linux/arch/m32r/platforms/oaks32r/setup.c
1da177e4 LT	3	*
	4	* Setup routines for OAKS32R Board
	5	*
316240f6 HT	6	* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
316240f6 HT	7	* Hitoshi Yamamoto, Mamoru Sakugawa
1da177e4 LT	8	*/
1da177e4 LT	9
1da177e4 LT	10	#include <linux/irq.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13
	14	#include <asm/system.h>
	15	#include <asm/m32r.h>
	16	#include <asm/io.h>
	17
	18	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	19
1da177e4 LT	20	icu_data_t icu_data[NR_IRQS];
	21
	22	static void disable_oaks32r_irq(unsigned int irq)
	23	{
	24	unsigned long port, data;
	25
	26	port = irq2port(irq);
	27	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	28	outl(data, port);
	29	}
	30
	31	static void enable_oaks32r_irq(unsigned int irq)
	32	{
	33	unsigned long port, data;
	34
	35	port = irq2port(irq);
	36	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	37	outl(data, port);
	38	}
	39
	40	static void mask_and_ack_mappi(unsigned int irq)
	41	{
	42	disable_oaks32r_irq(irq);
	43	}
	44
	45	static void end_oaks32r_irq(unsigned int irq)
	46	{
	47	enable_oaks32r_irq(irq);
	48	}
	49
	50	static unsigned int startup_oaks32r_irq(unsigned int irq)
	51	{
	52	enable_oaks32r_irq(irq);
	53	return (0);
	54	}
	55
	56	static void shutdown_oaks32r_irq(unsigned int irq)
	57	{
	58	unsigned long port;
	59
	60	port = irq2port(irq);
	61	outl(M32R_ICUCR_ILEVEL7, port);
	62	}
	63
189e91f5	64	static struct irq_chip oaks32r_irq_type =
1da177e4	65	{
6f973b00 HT	66	.typename = "OAKS32R-IRQ",
	67	.startup = startup_oaks32r_irq,
	68	.shutdown = shutdown_oaks32r_irq,
	69	.enable = enable_oaks32r_irq,
	70	.disable = disable_oaks32r_irq,
	71	.ack = mask_and_ack_mappi,
	72	.end = end_oaks32r_irq
1da177e4 LT	73	};
	74
	75	void __init init_IRQ(void)
	76	{
	77	static int once = 0;
	78
	79	if (once)
	80	return;
	81	else
	82	once++;
	83
	84	#ifdef CONFIG_NE2000
	85	/* INT3 : LAN controller (RTL8019AS) */
	86	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
d1bef4ed	87	irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
1da177e4 LT	88	irq_desc[M32R_IRQ_INT3].action = 0;
	89	irq_desc[M32R_IRQ_INT3].depth = 1;
	90	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	91	disable_oaks32r_irq(M32R_IRQ_INT3);
	92	#endif /* CONFIG_M32R_NE2000 */
	93
	94	/* MFT2 : system timer */
	95	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
d1bef4ed	96	irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
1da177e4 LT	97	irq_desc[M32R_IRQ_MFT2].action = 0;
	98	irq_desc[M32R_IRQ_MFT2].depth = 1;
	99	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	100	disable_oaks32r_irq(M32R_IRQ_MFT2);
	101
	102	#ifdef CONFIG_SERIAL_M32R_SIO
	103	/* SIO0_R : uart receive data */
	104	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
d1bef4ed	105	irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
1da177e4 LT	106	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	107	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	108	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	109	disable_oaks32r_irq(M32R_IRQ_SIO0_R);
	110
	111	/* SIO0_S : uart send data */
	112	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
d1bef4ed	113	irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
1da177e4 LT	114	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	115	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	116	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	117	disable_oaks32r_irq(M32R_IRQ_SIO0_S);
	118
	119	/* SIO1_R : uart receive data */
	120	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
d1bef4ed	121	irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
1da177e4 LT	122	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	123	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	124	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	125	disable_oaks32r_irq(M32R_IRQ_SIO1_R);
	126
	127	/* SIO1_S : uart send data */
	128	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
d1bef4ed	129	irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
1da177e4 LT	130	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	131	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	132	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	133	disable_oaks32r_irq(M32R_IRQ_SIO1_S);
	134	#endif /* CONFIG_SERIAL_M32R_SIO */
1da177e4	135	}