projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b5aaf3f7 GU |
1 | /***************************************************************************/ |
| 2 | ||
| 3 | /* | |
| ece9ae65 | 4 | * m523x.c -- platform support for ColdFire 523x based boards |
| b5aaf3f7 | 5 | * |
| 25985edc | 6 | * Sub-architcture dependent initialization code for the Freescale |
| b5aaf3f7 GU |
7 | * 523x CPUs. |
| 8 | * | |
| 9 | * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com) | |
| 10 | * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) | |
| 11 | */ | |
| 12 | ||
| 13 | /***************************************************************************/ | |
| 14 | ||
| b5aaf3f7 | 15 | #include <linux/kernel.h> |
| b5aaf3f7 GU |
16 | #include <linux/param.h> |
| 17 | #include <linux/init.h> | |
| 4b61a353 | 18 | #include <linux/io.h> |
| b5aaf3f7 GU |
19 | #include <asm/machdep.h> |
| 20 | #include <asm/coldfire.h> | |
| 21 | #include <asm/mcfsim.h> | |
| a0f8f8c8 GU |
22 | #include <asm/mcfclk.h> |
| 23 | ||
| 24 | /***************************************************************************/ | |
| 25 | ||
| 26 | DEFINE_CLK(pll, "pll.0", MCF_CLK); | |
| 27 | DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); | |
| 28 | DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); | |
| 29 | DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); | |
| 30 | DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); | |
| 31 | DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); | |
| 32 | DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); | |
| 33 | DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); | |
| 34 | DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); | |
| 74859523 | 35 | DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); |
| a0f8f8c8 GU |
36 | DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); |
| 37 | ||
| 38 | struct clk *mcf_clks[] = { | |
| 39 | &clk_pll, | |
| 40 | &clk_sys, | |
| 41 | &clk_mcfpit0, | |
| 42 | &clk_mcfpit1, | |
| 43 | &clk_mcfpit2, | |
| 44 | &clk_mcfpit3, | |
| 45 | &clk_mcfuart0, | |
| 46 | &clk_mcfuart1, | |
| 47 | &clk_mcfuart2, | |
| 74859523 | 48 | &clk_mcfqspi0, |
| a0f8f8c8 GU |
49 | &clk_fec0, |
| 50 | NULL | |
| 51 | }; | |
| b5aaf3f7 GU |
52 | |
| 53 | /***************************************************************************/ | |
| 54 | ||
| 91d60417 SK |
55 | static void __init m523x_qspi_init(void) |
| 56 | { | |
| 151d14f4 | 57 | #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) |
| 91d60417 SK |
58 | u16 par; |
| 59 | ||
| 60 | /* setup QSPS pins for QSPI with gpio CS control */ | |
| 61 | writeb(0x1f, MCFGPIO_PAR_QSPI); | |
| 62 | /* and CS2 & CS3 as gpio */ | |
| 63 | par = readw(MCFGPIO_PAR_TIMER); | |
| 64 | par &= 0x3f3f; | |
| 65 | writew(par, MCFGPIO_PAR_TIMER); | |
| 83ca6009 | 66 | #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ |
| 151d14f4 | 67 | } |
| b5aaf3f7 | 68 | |
| 4b61a353 GU |
69 | /***************************************************************************/ |
| 70 | ||
| 14c16db3 GU |
71 | static void __init m523x_fec_init(void) |
| 72 | { | |
| 14c16db3 | 73 | /* Set multi-function pins to ethernet use */ |
| 98d9696b | 74 | writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C); |
| 14c16db3 GU |
75 | } |
| 76 | ||
| 77 | /***************************************************************************/ | |
| 78 | ||
| 4b61a353 | 79 | void __init config_BSP(char *commandp, int size) |
| b5aaf3f7 | 80 | { |
| 35aefb26 | 81 | mach_sched_init = hw_timer_init; |
| 2ba168a9 | 82 | m523x_fec_init(); |
| 91d60417 | 83 | m523x_qspi_init(); |
| 4b61a353 GU |
84 | } |
| 85 | ||
| 4b61a353 | 86 | /***************************************************************************/ |