[deliverable/linux.git] / arch / m68k / coldfire / pit.c

/***************************************************************************/

/*
 *	pit.c -- Freescale ColdFire PIT timer. Currently this type of
 *	         hardware timer only exists in the Freescale ColdFire
 *		 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
 *		 family members will probably use it too.
 *
 *	Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/coldfire.h>
#include <asm/mcfpit.h>
#include <asm/mcfsim.h>

/***************************************************************************/

/*
 *	By default use timer1 as the system clock timer.
 */
#define	FREQ	((MCF_CLK / 2) / 64)
#define	TA(a)	(MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)

static u32 pit_cnt;

/*
 * Initialize the PIT timer.
 *
 * This is also called after resume to bring the PIT into operation again.
 */

static int cf_pit_set_periodic(struct clock_event_device *evt)
{
	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
	__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
		     MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
		     MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	return 0;
}

static int cf_pit_set_oneshot(struct clock_event_device *evt)
{
	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
		     MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	return 0;
}

static int cf_pit_shutdown(struct clock_event_device *evt)
{
	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	return 0;
}

/*
 * Program the next event in oneshot mode
 *
 * Delta is given in PIT ticks
 */
static int cf_pit_next_event(unsigned long delta,
		struct clock_event_device *evt)
{
	__raw_writew(delta, TA(MCFPIT_PMR));
	return 0;
}

struct clock_event_device cf_pit_clockevent = {
	.name			= "pit",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= cf_pit_shutdown,
	.set_state_periodic	= cf_pit_set_periodic,
	.set_state_oneshot	= cf_pit_set_oneshot,
	.set_next_event		= cf_pit_next_event,
	.shift			= 32,
	.irq			= MCF_IRQ_PIT1,
};


/***************************************************************************/

static irqreturn_t pit_tick(int irq, void *dummy)
{
	struct clock_event_device *evt = &cf_pit_clockevent;
	u16 pcsr;

	/* Reset the ColdFire timer */
	pcsr = __raw_readw(TA(MCFPIT_PCSR));
	__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));

	pit_cnt += PIT_CYCLES_PER_JIFFY;
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

/***************************************************************************/

static struct irqaction pit_irq = {
	.name	 = "timer",
	.flags	 = IRQF_TIMER,
	.handler = pit_tick,
};

/***************************************************************************/

static cycle_t pit_read_clk(struct clocksource *cs)
{
	unsigned long flags;
	u32 cycles;
	u16 pcntr;

	local_irq_save(flags);
	pcntr = __raw_readw(TA(MCFPIT_PCNTR));
	cycles = pit_cnt;
	local_irq_restore(flags);

	return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
}

/***************************************************************************/

static struct clocksource pit_clk = {
	.name	= "pit",
	.rating	= 100,
	.read	= pit_read_clk,
	.mask	= CLOCKSOURCE_MASK(32),
};

/***************************************************************************/

void hw_timer_init(irq_handler_t handler)
{
	cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
	cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
	cf_pit_clockevent.max_delta_ns =
		clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
	cf_pit_clockevent.min_delta_ns =
		clockevent_delta2ns(0x3f, &cf_pit_clockevent);
	clockevents_register_device(&cf_pit_clockevent);

	setup_irq(MCF_IRQ_PIT1, &pit_irq);

	clocksource_register_hz(&pit_clk, FREQ);
}

/***************************************************************************/
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************/
	2
	3	/*
b671b653 GU	4	* pit.c -- Freescale ColdFire PIT timer. Currently this type of
b671b653 GU	5	* hardware timer only exists in the Freescale ColdFire
8d80c5ee GU	6	* 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
8d80c5ee GU	7	* family members will probably use it too.
1da177e4	8	*
8d80c5ee	9	* Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
1da177e4	10	* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
1da177e4 LT	11	*/
	12
	13	/***************************************************************************/
	14
1da177e4 LT	15	#include <linux/kernel.h>
	16	#include <linux/sched.h>
	17	#include <linux/param.h>
	18	#include <linux/init.h>
	19	#include <linux/interrupt.h>
5c4525da	20	#include <linux/irq.h>
2b9a6986	21	#include <linux/clockchips.h>
2f2c2679	22	#include <asm/machdep.h>
b671b653	23	#include <asm/io.h>
1da177e4 LT	24	#include <asm/coldfire.h>
	25	#include <asm/mcfpit.h>
	26	#include <asm/mcfsim.h>
	27
	28	/***************************************************************************/
	29
b671b653 GU	30	/*
	31	* By default use timer1 as the system clock timer.
	32	*/
8d80c5ee	33	#define FREQ ((MCF_CLK / 2) / 64)
f317c71a	34	#define TA(a) (MCFPIT_BASE1 + (a))
2b9a6986	35	#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
8d80c5ee	36
8d80c5ee	37	static u32 pit_cnt;
b671b653	38
2b9a6986 SS	39	/*
	40	* Initialize the PIT timer.
	41	*
	42	* This is also called after resume to bring the PIT into operation again.
	43	*/
	44
5bbc08fb	45	static int cf_pit_set_periodic(struct clock_event_device *evt)
2b9a6986	46	{
5bbc08fb VK	47	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	48	__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
	49	__raw_writew(MCFPIT_PCSR_EN \| MCFPIT_PCSR_PIE \|
	50	MCFPIT_PCSR_OVW \| MCFPIT_PCSR_RLD \|
	51	MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	52	return 0;
	53	}
	54
	55	static int cf_pit_set_oneshot(struct clock_event_device *evt)
	56	{
	57	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	58	__raw_writew(MCFPIT_PCSR_EN \| MCFPIT_PCSR_PIE \|
	59	MCFPIT_PCSR_OVW \| MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	60	return 0;
	61	}
	62
	63	static int cf_pit_shutdown(struct clock_event_device *evt)
	64	{
	65	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	66	return 0;
2b9a6986 SS	67	}
	68
	69	/*
	70	* Program the next event in oneshot mode
	71	*
	72	* Delta is given in PIT ticks
	73	*/
	74	static int cf_pit_next_event(unsigned long delta,
	75	struct clock_event_device *evt)
	76	{
	77	__raw_writew(delta, TA(MCFPIT_PMR));
	78	return 0;
	79	}
	80
	81	struct clock_event_device cf_pit_clockevent = {
5bbc08fb VK	82	.name = "pit",
	83	.features = CLOCK_EVT_FEAT_PERIODIC \|
	84	CLOCK_EVT_FEAT_ONESHOT,
	85	.set_state_shutdown = cf_pit_shutdown,
	86	.set_state_periodic = cf_pit_set_periodic,
	87	.set_state_oneshot = cf_pit_set_oneshot,
	88	.set_next_event = cf_pit_next_event,
	89	.shift = 32,
	90	.irq = MCF_IRQ_PIT1,
2b9a6986 SS	91	};
	92
	93
	94
b671b653 GU	95	/***************************************************************************/
b671b653 GU	96
8d80c5ee	97	static irqreturn_t pit_tick(int irq, void *dummy)
1da177e4	98	{
2b9a6986	99	struct clock_event_device *evt = &cf_pit_clockevent;
8d80c5ee	100	u16 pcsr;
1da177e4 LT	101
1da177e4 LT	102	/* Reset the ColdFire timer */
b671b653 GU	103	pcsr = __raw_readw(TA(MCFPIT_PCSR));
b671b653 GU	104	__raw_writew(pcsr \| MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
2f2c2679	105
2b9a6986 SS	106	pit_cnt += PIT_CYCLES_PER_JIFFY;
	107	evt->event_handler(evt);
	108	return IRQ_HANDLED;
1da177e4 LT	109	}
	110
	111	/***************************************************************************/
	112
8d80c5ee	113	static struct irqaction pit_irq = {
2f2c2679	114	.name = "timer",
77a42796	115	.flags = IRQF_TIMER,
8d80c5ee	116	.handler = pit_tick,
5c4525da GU	117	};
5c4525da GU	118
8d80c5ee GU	119	/***************************************************************************/
8d80c5ee GU	120
8e19608e	121	static cycle_t pit_read_clk(struct clocksource *cs)
1da177e4	122	{
8d80c5ee GU	123	unsigned long flags;
	124	u32 cycles;
	125	u16 pcntr;
1da177e4	126
8d80c5ee GU	127	local_irq_save(flags);
	128	pcntr = __raw_readw(TA(MCFPIT_PCNTR));
	129	cycles = pit_cnt;
	130	local_irq_restore(flags);
1da177e4	131
2b9a6986	132	return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
8d80c5ee	133	}
1da177e4	134
8d80c5ee	135	/***************************************************************************/
1da177e4	136
8d80c5ee GU	137	static struct clocksource pit_clk = {
8d80c5ee GU	138	.name = "pit",
2b9a6986	139	.rating = 100,
8d80c5ee	140	.read = pit_read_clk,
8d80c5ee	141	.mask = CLOCKSOURCE_MASK(32),
8d80c5ee	142	};
1da177e4 LT	143
	144	/***************************************************************************/
	145
35aefb26	146	void hw_timer_init(irq_handler_t handler)
1da177e4	147	{
320ab2b0	148	cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
2b9a6986 SS	149	cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
	150	cf_pit_clockevent.max_delta_ns =
	151	clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
	152	cf_pit_clockevent.min_delta_ns =
	153	clockevent_delta2ns(0x3f, &cf_pit_clockevent);
	154	clockevents_register_device(&cf_pit_clockevent);
	155
bdee4e26	156	setup_irq(MCF_IRQ_PIT1, &pit_irq);
1da177e4	157
010f3f16	158	clocksource_register_hz(&pit_clk, FREQ);
1da177e4 LT	159	}
	160
	161	/***************************************************************************/