projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /****************************************************************************/ |
| 2 | ||
| 3 | /* | |
| 4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. | |
| 5 | * | |
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) | |
| 7 | */ | |
| 8 | ||
| 9 | /****************************************************************************/ | |
| 10 | #ifndef m527xsim_h | |
| 11 | #define m527xsim_h | |
| 12 | /****************************************************************************/ | |
| 13 | ||
| 733f31b7 GU |
14 | #define CPU_NAME "COLDFIRE(m527x)" |
| 15 | #define CPU_INSTR_PER_JIFFY 3 | |
| ce3de78a | 16 | #define MCF_BUSCLK (MCF_CLK / 2) |
| 7fc82b65 | 17 | |
| a12cf0a8 | 18 | #include <asm/m52xxacr.h> |
| 1da177e4 LT |
19 | |
| 20 | /* | |
| 21 | * Define the 5270/5271 SIM register set addresses. | |
| 22 | */ | |
| 254eef74 GU |
23 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
| 24 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ | |
| 25 | ||
| 1da177e4 LT |
26 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 27 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
| 28 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
| 29 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
| 30 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
| 31 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
| 32 | #define MCFINTC_IRLR 0x18 /* */ | |
| 33 | #define MCFINTC_IACKL 0x19 /* */ | |
| 34 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
| 35 | ||
| 36 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
| 37 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
| 38 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ | |
| 39 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | |
| 91d60417 | 40 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| 308bfc12 GU |
41 | #define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ |
| 42 | #define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ | |
| 43 | #define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ | |
| 1da177e4 LT |
44 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| 45 | ||
| 308bfc12 GU |
46 | #define MCFINT2_VECBASE 128 /* Vector base number 2 */ |
| 47 | #define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ | |
| 48 | #define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ | |
| 49 | #define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ | |
| 50 | ||
| 20e681fd GU |
51 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| 52 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) | |
| 53 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) | |
| 54 | ||
| 308bfc12 GU |
55 | #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| 56 | #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) | |
| 57 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | |
| 58 | #define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) | |
| 59 | #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) | |
| 60 | #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) | |
| 61 | ||
| 6c84a60e | 62 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| bdee4e26 | 63 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
| 6c84a60e | 64 | |
| 1da177e4 LT |
65 | /* |
| 66 | * SDRAM configuration registers. | |
| 67 | */ | |
| d871629b | 68 | #ifdef CONFIG_M5271 |
| 6a92e198 GU |
69 | #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ |
| 70 | #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ | |
| 71 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ | |
| 72 | #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ | |
| 73 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ | |
| d871629b GU |
74 | #endif |
| 75 | #ifdef CONFIG_M5275 | |
| 6a92e198 GU |
76 | #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ |
| 77 | #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ | |
| 78 | #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ | |
| 79 | #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ | |
| 80 | #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ | |
| 81 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ | |
| 82 | #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ | |
| 83 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ | |
| 1da177e4 LT |
84 | #endif |
| 85 | ||
| babc08b7 GU |
86 | /* |
| 87 | * DMA unit base addresses. | |
| 88 | */ | |
| 89 | #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) | |
| 90 | #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) | |
| 91 | #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) | |
| 92 | #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) | |
| 93 | ||
| 57015421 GU |
94 | /* |
| 95 | * UART module. | |
| 96 | */ | |
| 20e681fd GU |
97 | #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
| 98 | #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) | |
| 99 | #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) | |
| 9a6b0c73 GU |
100 | |
| 101 | /* | |
| 102 | * FEC ethernet module. | |
| 103 | */ | |
| 104 | #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) | |
| 105 | #define MCFFEC_SIZE0 0x800 | |
| 106 | #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) | |
| 107 | #define MCFFEC_SIZE1 0x800 | |
| f1554da3 | 108 | |
| 6c84a60e GU |
109 | /* |
| 110 | * QSPI module. | |
| 111 | */ | |
| 112 | #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) | |
| 113 | #define MCFQSPI_SIZE 0x40 | |
| 114 | ||
| 115 | #ifdef CONFIG_M5271 | |
| 116 | #define MCFQSPI_CS0 91 | |
| 117 | #define MCFQSPI_CS1 92 | |
| 118 | #define MCFQSPI_CS2 99 | |
| 119 | #define MCFQSPI_CS3 103 | |
| 120 | #endif | |
| 121 | #ifdef CONFIG_M5275 | |
| 122 | #define MCFQSPI_CS0 59 | |
| 123 | #define MCFQSPI_CS1 60 | |
| 124 | #define MCFQSPI_CS2 61 | |
| 125 | #define MCFQSPI_CS3 62 | |
| 126 | #endif | |
| 127 | ||
| 128 | /* | |
| 129 | * GPIO module. | |
| 130 | */ | |
| f1554da3 | 131 | #ifdef CONFIG_M5271 |
| 132 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) | |
| 133 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) | |
| 134 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) | |
| 135 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) | |
| 136 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) | |
| 137 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) | |
| 138 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) | |
| 139 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) | |
| 140 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) | |
| 141 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) | |
| 142 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) | |
| 143 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) | |
| 144 | ||
| 145 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) | |
| 146 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) | |
| 147 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) | |
| 148 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) | |
| 149 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) | |
| 150 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) | |
| 151 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) | |
| 152 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) | |
| 153 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) | |
| 154 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) | |
| 155 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) | |
| 156 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) | |
| 157 | ||
| 158 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) | |
| 159 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) | |
| 160 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) | |
| 161 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) | |
| 162 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) | |
| 163 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) | |
| 164 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) | |
| 165 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) | |
| 166 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) | |
| 167 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) | |
| 168 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) | |
| 169 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) | |
| 170 | ||
| 171 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) | |
| 172 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) | |
| 173 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) | |
| 174 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) | |
| 175 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) | |
| 176 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) | |
| 177 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) | |
| 178 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) | |
| 179 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) | |
| 180 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) | |
| 181 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) | |
| 182 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) | |
| 183 | ||
| 184 | /* | |
| 185 | * Generic GPIO support | |
| 186 | */ | |
| 187 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR | |
| 188 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR | |
| 189 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR | |
| 190 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR | |
| 191 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR | |
| 192 | ||
| 193 | #define MCFGPIO_PIN_MAX 100 | |
| 194 | #define MCFGPIO_IRQ_MAX 8 | |
| 195 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
| 91d60417 | 196 | |
| f821e349 GU |
197 | /* |
| 198 | * Port Pin Assignment registers. | |
| 199 | */ | |
| 200 | #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) | |
| 201 | #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) | |
| 202 | #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) | |
| 203 | #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) | |
| 204 | #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) | |
| 205 | #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) | |
| 206 | #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) | |
| 91d60417 SK |
207 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) |
| 208 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) | |
| f821e349 GU |
209 | |
| 210 | #define UART0_ENABLE_MASK 0x000f | |
| 211 | #define UART1_ENABLE_MASK 0x0ff0 | |
| 212 | #define UART2_ENABLE_MASK 0x3000 | |
| 213 | #endif /* CONFIG_M5271 */ | |
| f1554da3 | 214 | |
| 215 | #ifdef CONFIG_M5275 | |
| 216 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) | |
| 217 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) | |
| 218 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) | |
| 219 | #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) | |
| 220 | #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) | |
| 221 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) | |
| 222 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) | |
| 223 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) | |
| 224 | #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) | |
| 225 | #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) | |
| 226 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) | |
| 227 | #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) | |
| 228 | #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) | |
| 229 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) | |
| 230 | #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) | |
| 231 | #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) | |
| 232 | #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) | |
| 233 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) | |
| 234 | ||
| 235 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) | |
| 236 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) | |
| 237 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) | |
| 238 | #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) | |
| 239 | #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) | |
| 240 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) | |
| 241 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) | |
| 242 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) | |
| 243 | #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) | |
| 244 | #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) | |
| 245 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) | |
| 246 | #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) | |
| 247 | #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) | |
| 248 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) | |
| 249 | #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) | |
| 250 | #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) | |
| 251 | #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) | |
| 252 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) | |
| 253 | ||
| 254 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) | |
| 255 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) | |
| 256 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) | |
| 257 | #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) | |
| 258 | #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) | |
| 259 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) | |
| 260 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) | |
| 261 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) | |
| 262 | #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) | |
| 263 | #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) | |
| 264 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) | |
| 265 | #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) | |
| 266 | #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) | |
| 267 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) | |
| 268 | #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) | |
| 269 | #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) | |
| 270 | #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) | |
| 271 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) | |
| 272 | ||
| 273 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) | |
| 274 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) | |
| 275 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) | |
| 276 | #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) | |
| 277 | #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) | |
| 278 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) | |
| 279 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) | |
| 280 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) | |
| 281 | #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) | |
| 282 | #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) | |
| 283 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) | |
| 284 | #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) | |
| 285 | #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) | |
| 286 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) | |
| 287 | #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) | |
| 288 | #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) | |
| 289 | #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) | |
| 290 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) | |
| 291 | ||
| 292 | ||
| 293 | /* | |
| 294 | * Generic GPIO support | |
| 295 | */ | |
| 296 | #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL | |
| 297 | #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL | |
| 298 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL | |
| 299 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL | |
| 300 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL | |
| 301 | ||
| 302 | #define MCFGPIO_PIN_MAX 148 | |
| 303 | #define MCFGPIO_IRQ_MAX 8 | |
| 304 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
| 91d60417 | 305 | |
| f821e349 GU |
306 | /* |
| 307 | * Port Pin Assignment registers. | |
| 308 | */ | |
| 309 | #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070) | |
| 310 | #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071) | |
| 311 | #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072) | |
| 312 | #define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076) | |
| 313 | #define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078) | |
| 314 | #define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079) | |
| 315 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A) | |
| 316 | #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C) | |
| 91d60417 | 317 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) |
| f821e349 GU |
318 | #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080) |
| 319 | #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082) | |
| 320 | #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084) | |
| 321 | ||
| 322 | #define UART0_ENABLE_MASK 0x000f | |
| 323 | #define UART1_ENABLE_MASK 0x00f0 | |
| 324 | #define UART2_ENABLE_MASK 0x3f00 | |
| 325 | #endif /* CONFIG_M5275 */ | |
| f1554da3 | 326 | |
| 327 | /* | |
| f317c71a | 328 | * PIT timer base addresses. |
| f1554da3 | 329 | */ |
| f317c71a GU |
330 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
| 331 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) | |
| 332 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) | |
| 333 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) | |
| f1554da3 | 334 | |
| f317c71a GU |
335 | /* |
| 336 | * EPort | |
| 337 | */ | |
| 57b48143 | 338 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
| f1554da3 | 339 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| 57b48143 | 340 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
| f1554da3 | 341 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
| 342 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) | |
| 57b48143 | 343 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
| f1554da3 | 344 | |
| 4c0b008d | 345 | /* |
| 25985edc | 346 | * Reset Control Unit (relative to IPSBAR). |
| 4c0b008d | 347 | */ |
| 0b2a2139 GU |
348 | #define MCF_RCR (MCF_IPSBAR + 0x110000) |
| 349 | #define MCF_RSR (MCF_IPSBAR + 0x110001) | |
| 4c0b008d GU |
350 | |
| 351 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
| 352 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
| 353 | ||
| 1da177e4 LT |
354 | /****************************************************************************/ |
| 355 | #endif /* m527xsim_h */ |