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1da177e4 LT |
1 | /****************************************************************************/ |
2 | ||
3 | /* | |
4 | * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. | |
5 | * | |
6 | * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) | |
7 | */ | |
8 | ||
9 | /****************************************************************************/ | |
10 | #ifndef m528xsim_h | |
11 | #define m528xsim_h | |
12 | /****************************************************************************/ | |
13 | ||
733f31b7 GU |
14 | #define CPU_NAME "COLDFIRE(m528x)" |
15 | #define CPU_INSTR_PER_JIFFY 3 | |
ce3de78a | 16 | #define MCF_BUSCLK MCF_CLK |
1da177e4 | 17 | |
a12cf0a8 GU |
18 | #include <asm/m52xxacr.h> |
19 | ||
1da177e4 LT |
20 | /* |
21 | * Define the 5280/5282 SIM register set addresses. | |
22 | */ | |
254eef74 GU |
23 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
24 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ | |
25 | ||
1da177e4 LT |
26 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
27 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
28 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
29 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
30 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
31 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
32 | #define MCFINTC_IRLR 0x18 /* */ | |
33 | #define MCFINTC_IACKL 0x19 /* */ | |
34 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
35 | ||
36 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
37 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
f8bb5327 GU |
38 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ |
39 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | |
91d60417 | 40 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
4f8f9fb8 GU |
41 | #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ |
42 | #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ | |
43 | #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ | |
1da177e4 LT |
44 | #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ |
45 | ||
f8bb5327 GU |
46 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
47 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) | |
48 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) | |
49 | ||
4f8f9fb8 GU |
50 | #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
51 | #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) | |
52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | |
53 | ||
3b2039b2 GU |
54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
55 | ||
1da177e4 LT |
56 | /* |
57 | * SDRAM configuration registers. | |
58 | */ | |
6a92e198 GU |
59 | #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ |
60 | #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ | |
61 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */ | |
62 | #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */ | |
63 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */ | |
1da177e4 | 64 | |
babc08b7 GU |
65 | /* |
66 | * DMA unit base addresses. | |
67 | */ | |
68 | #define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100) | |
69 | #define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140) | |
70 | #define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180) | |
71 | #define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0) | |
72 | ||
57015421 GU |
73 | /* |
74 | * UART module. | |
75 | */ | |
f8bb5327 GU |
76 | #define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200) |
77 | #define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240) | |
78 | #define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280) | |
a0ba4332 GU |
79 | |
80 | /* | |
81 | * FEC ethernet module. | |
82 | */ | |
4f8f9fb8 GU |
83 | #define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) |
84 | #define MCFFEC_SIZE0 0x800 | |
57015421 | 85 | |
3b2039b2 GU |
86 | /* |
87 | * QSPI module. | |
88 | */ | |
f75b0d07 | 89 | #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
3b2039b2 GU |
90 | #define MCFQSPI_SIZE 0x40 |
91 | ||
92 | #define MCFQSPI_CS0 147 | |
93 | #define MCFQSPI_CS1 148 | |
94 | #define MCFQSPI_CS2 149 | |
95 | #define MCFQSPI_CS3 150 | |
96 | ||
6da6e63c | 97 | /* |
98 | * GPIO registers | |
99 | */ | |
c222f5f4 GU |
100 | #define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) |
101 | #define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) | |
102 | #define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) | |
103 | #define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) | |
104 | #define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) | |
105 | #define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) | |
106 | #define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) | |
107 | #define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) | |
108 | #define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) | |
109 | #define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) | |
110 | #define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) | |
111 | #define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) | |
112 | #define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) | |
113 | #define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) | |
114 | #define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) | |
115 | #define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) | |
116 | #define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) | |
117 | #define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) | |
118 | ||
119 | #define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) | |
120 | #define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) | |
121 | #define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) | |
122 | #define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) | |
123 | #define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) | |
124 | #define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) | |
125 | #define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) | |
126 | #define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) | |
127 | #define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) | |
128 | #define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) | |
129 | #define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) | |
130 | #define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) | |
131 | #define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) | |
132 | #define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) | |
133 | #define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) | |
134 | #define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) | |
135 | #define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) | |
136 | #define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) | |
137 | ||
138 | #define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) | |
139 | #define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) | |
140 | #define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) | |
141 | #define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) | |
142 | #define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) | |
143 | #define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) | |
144 | #define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) | |
145 | #define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) | |
146 | #define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) | |
147 | #define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) | |
148 | #define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) | |
149 | #define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) | |
150 | #define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) | |
151 | #define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) | |
152 | #define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) | |
153 | #define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) | |
154 | #define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) | |
155 | #define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) | |
156 | ||
157 | #define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) | |
158 | #define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) | |
159 | #define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) | |
160 | #define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) | |
161 | #define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) | |
162 | #define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) | |
163 | #define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) | |
164 | #define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) | |
165 | #define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) | |
166 | #define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) | |
167 | #define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) | |
168 | #define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) | |
169 | #define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) | |
170 | #define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) | |
171 | #define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) | |
172 | #define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) | |
173 | #define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) | |
174 | #define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) | |
6da6e63c | 175 | |
176 | #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) | |
177 | #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) | |
178 | #define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052) | |
179 | #define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054) | |
180 | #define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055) | |
181 | #define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056) | |
182 | #define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058) | |
183 | #define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059) | |
184 | #define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A) | |
185 | #define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B) | |
186 | #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) | |
187 | ||
f317c71a GU |
188 | /* |
189 | * PIT timer base addresses. | |
190 | */ | |
191 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000) | |
192 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000) | |
193 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000) | |
194 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000) | |
195 | ||
6da6e63c | 196 | /* |
197 | * Edge Port registers | |
198 | */ | |
199 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) | |
200 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002) | |
201 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003) | |
202 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004) | |
203 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005) | |
204 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006) | |
205 | ||
206 | /* | |
207 | * Queued ADC registers | |
208 | */ | |
209 | #define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006) | |
210 | #define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007) | |
211 | #define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008) | |
212 | #define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009) | |
213 | ||
214 | /* | |
215 | * General Purpose Timers registers | |
216 | */ | |
217 | #define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D) | |
218 | #define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E) | |
219 | #define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D) | |
220 | #define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E) | |
221 | /* | |
222 | * | |
223 | * definitions for generic gpio support | |
224 | * | |
225 | */ | |
c222f5f4 GU |
226 | #define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ |
227 | #define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ | |
228 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ | |
229 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ | |
230 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ | |
6da6e63c | 231 | |
232 | #define MCFGPIO_IRQ_MAX 8 | |
233 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
234 | #define MCFGPIO_PIN_MAX 180 | |
235 | ||
236 | ||
7ce4d425 GU |
237 | /* |
238 | * Derek Cheung - 6 Feb 2005 | |
239 | * add I2C and QSPI register definition using Freescale's MCF5282 | |
240 | */ | |
241 | /* set Port AS pin for I2C or UART */ | |
242 | #define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056) | |
243 | ||
8bb25184 GU |
244 | /* Port UA Pin Assignment Register (8 Bit) */ |
245 | #define MCF5282_GPIO_PUAPAR 0x10005C | |
246 | ||
7ce4d425 GU |
247 | /* Interrupt Mask Register Register Low */ |
248 | #define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C) | |
249 | /* Interrupt Control Register 7 */ | |
250 | #define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) | |
251 | ||
252 | ||
dd65b1de GU |
253 | /* |
254 | * Reset Control Unit (relative to IPSBAR). | |
255 | */ | |
645e5333 GU |
256 | #define MCF_RCR (MCF_IPSBAR + 0x110000) |
257 | #define MCF_RSR (MCF_IPSBAR + 0x110001) | |
dd65b1de GU |
258 | |
259 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
260 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
7ce4d425 GU |
261 | |
262 | /********************************************************************* | |
263 | * | |
264 | * Inter-IC (I2C) Module | |
265 | * | |
266 | *********************************************************************/ | |
267 | /* Read/Write access macros for general use */ | |
268 | #define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address | |
269 | #define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider | |
270 | #define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control | |
271 | #define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status | |
272 | #define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O | |
273 | ||
274 | /* Bit level definitions and macros */ | |
275 | #define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) | |
276 | ||
277 | #define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) | |
278 | ||
279 | #define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable | |
280 | #define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable | |
281 | #define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode | |
282 | #define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode | |
283 | #define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable | |
284 | #define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start | |
285 | ||
286 | #define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit | |
287 | #define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave | |
288 | #define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy | |
289 | #define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost | |
290 | #define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write | |
291 | #define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt | |
292 | #define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge | |
293 | ||
294 | ||
1da177e4 | 295 | #endif /* m528xsim_h */ |