projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ea49f8ff | 1 | /* |
| 5b2e6555 | 2 | * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. |
| ea49f8ff PDM |
3 | */ |
| 4 | ||
| 5b2e6555 GU |
5 | #ifndef m54xxsim_h |
| 6 | #define m54xxsim_h | |
| ea49f8ff | 7 | |
| 733f31b7 GU |
8 | #define CPU_NAME "COLDFIRE(m54xx)" |
| 9 | #define CPU_INSTR_PER_JIFFY 2 | |
| ce3de78a | 10 | #define MCF_BUSCLK (MCF_CLK / 2) |
| 657ae75f | 11 | #define MACHINE MACH_M54XX |
| 00c3532b | 12 | #define FPUTYPE FPU_COLDFIRE |
| c78b8d32 GU |
13 | #define IOMEMBASE MCF_MBAR |
| 14 | #define IOMEMSIZE 0x01000000 | |
| 7fc82b65 | 15 | |
| 3d461401 GU |
16 | #include <asm/m54xxacr.h> |
| 17 | ||
| 733f31b7 | 18 | #define MCFINT_VECBASE 64 |
| ea49f8ff PDM |
19 | |
| 20 | /* | |
| 21 | * Interrupt Controller Registers | |
| 22 | */ | |
| 254eef74 GU |
23 | #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ |
| 24 | ||
| ea49f8ff PDM |
25 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 26 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
| 27 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
| 28 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
| 29 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
| 30 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
| 31 | #define MCFINTC_IRLR 0x18 /* */ | |
| 32 | #define MCFINTC_IACKL 0x19 /* */ | |
| 33 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
| 34 | ||
| 57015421 GU |
35 | /* |
| 36 | * UART module. | |
| 37 | */ | |
| bbbeeaf2 GU |
38 | #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ |
| 39 | #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ | |
| 40 | #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ | |
| 41 | #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ | |
| 57015421 | 42 | |
| ea49f8ff PDM |
43 | /* |
| 44 | * Define system peripheral IRQ usage. | |
| 45 | */ | |
| bbbeeaf2 GU |
46 | #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ |
| 47 | #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ | |
| 48 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) | |
| 49 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) | |
| 50 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) | |
| 51 | #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) | |
| ea49f8ff | 52 | |
| f2f41c68 GU |
53 | /* |
| 54 | * Slice Timer support. | |
| 55 | */ | |
| 56 | #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */ | |
| 57 | #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */ | |
| 58 | ||
| ea49f8ff PDM |
59 | /* |
| 60 | * Generic GPIO support | |
| 61 | */ | |
| 83c6bdb8 SK |
62 | #define MCFGPIO_PODR (MCF_MBAR + 0xA00) |
| 63 | #define MCFGPIO_PDDR (MCF_MBAR + 0xA10) | |
| 64 | #define MCFGPIO_PPDR (MCF_MBAR + 0xA20) | |
| 65 | #define MCFGPIO_SETR (MCF_MBAR + 0xA20) | |
| 66 | #define MCFGPIO_CLRR (MCF_MBAR + 0xA30) | |
| 67 | ||
| 68 | #define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */ | |
| 69 | #define MCFGPIO_IRQ_MAX 8 | |
| 70 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
| ea49f8ff | 71 | |
| 57b48143 GU |
72 | /* |
| 73 | * EDGE Port support. | |
| 74 | */ | |
| 75 | #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ | |
| 76 | #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ | |
| 77 | #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ | |
| 78 | #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ | |
| 79 | #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ | |
| 80 | #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ | |
| 81 | ||
| ea49f8ff | 82 | /* |
| 632306f2 | 83 | * Pin Assignment register definitions |
| ea49f8ff | 84 | */ |
| 632306f2 GU |
85 | #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) |
| 86 | #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42) | |
| 87 | #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43) | |
| 88 | #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44) | |
| 89 | #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */ | |
| 90 | #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */ | |
| 91 | #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F) | |
| 92 | #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E) | |
| 93 | #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D) | |
| 94 | #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C) | |
| 95 | #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50) | |
| 96 | #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52) | |
| 97 | ||
| ea49f8ff PDM |
98 | #define MCF_PAR_SDA (0x0008) |
| 99 | #define MCF_PAR_SCL (0x0004) | |
| 100 | #define MCF_PAR_PSC_TXD (0x04) | |
| 101 | #define MCF_PAR_PSC_RXD (0x08) | |
| ea49f8ff PDM |
102 | #define MCF_PAR_PSC_CTS_GPIO (0x00) |
| 103 | #define MCF_PAR_PSC_CTS_BCLK (0x80) | |
| 104 | #define MCF_PAR_PSC_CTS_CTS (0xC0) | |
| 105 | #define MCF_PAR_PSC_RTS_GPIO (0x00) | |
| 106 | #define MCF_PAR_PSC_RTS_FSYNC (0x20) | |
| 107 | #define MCF_PAR_PSC_RTS_RTS (0x30) | |
| 108 | #define MCF_PAR_PSC_CANRX (0x40) | |
| 109 | ||
| 5b2e6555 | 110 | #endif /* m54xxsim_h */ |