projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /***************************************************************************/ |
| 2 | ||
| 3 | /* | |
| 4 | * linux/arch/m68knommu/platform/527x/config.c | |
| 5 | * | |
| 25985edc | 6 | * Sub-architcture dependent initialization code for the Freescale |
| 1da177e4 LT |
7 | * 5270/5271 CPUs. |
| 8 | * | |
| 9 | * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) | |
| 10 | * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) | |
| 11 | */ | |
| 12 | ||
| 13 | /***************************************************************************/ | |
| 14 | ||
| 1da177e4 | 15 | #include <linux/kernel.h> |
| 1da177e4 LT |
16 | #include <linux/param.h> |
| 17 | #include <linux/init.h> | |
| e206da0b | 18 | #include <linux/io.h> |
| 1da177e4 LT |
19 | #include <asm/machdep.h> |
| 20 | #include <asm/coldfire.h> | |
| 21 | #include <asm/mcfsim.h> | |
| e206da0b | 22 | #include <asm/mcfuart.h> |
| 1da177e4 LT |
23 | |
| 24 | /***************************************************************************/ | |
| 25 | ||
| 83ca6009 | 26 | #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) |
| 91d60417 SK |
27 | |
| 28 | static void __init m527x_qspi_init(void) | |
| 29 | { | |
| 30 | #if defined(CONFIG_M5271) | |
| 31 | u16 par; | |
| 32 | ||
| 33 | /* setup QSPS pins for QSPI with gpio CS control */ | |
| 34 | writeb(0x1f, MCFGPIO_PAR_QSPI); | |
| 35 | /* and CS2 & CS3 as gpio */ | |
| 36 | par = readw(MCFGPIO_PAR_TIMER); | |
| 37 | par &= 0x3f3f; | |
| 38 | writew(par, MCFGPIO_PAR_TIMER); | |
| 39 | #elif defined(CONFIG_M5275) | |
| 40 | /* setup QSPS pins for QSPI with gpio CS control */ | |
| 41 | writew(0x003e, MCFGPIO_PAR_QSPI); | |
| 42 | #endif | |
| 43 | } | |
| 91d60417 | 44 | |
| 83ca6009 | 45 | #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ |
| e206da0b GU |
46 | |
| 47 | /***************************************************************************/ | |
| 48 | ||
| 1eb13916 | 49 | static void __init m527x_uarts_init(void) |
| e206da0b GU |
50 | { |
| 51 | u16 sepmask; | |
| e206da0b | 52 | |
| e206da0b GU |
53 | /* |
| 54 | * External Pin Mask Setting & Enable External Pin for Interface | |
| 55 | */ | |
| 56 | sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); | |
| 1eb13916 | 57 | sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; |
| e206da0b GU |
58 | writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); |
| 59 | } | |
| 60 | ||
| 1da177e4 LT |
61 | /***************************************************************************/ |
| 62 | ||
| ffba3f48 GU |
63 | static void __init m527x_fec_init(void) |
| 64 | { | |
| 65 | u16 par; | |
| 66 | u8 v; | |
| 67 | ||
| ffba3f48 | 68 | /* Set multi-function pins to ethernet mode for fec0 */ |
| 592578a1 RR |
69 | #if defined(CONFIG_M5271) |
| 70 | v = readb(MCF_IPSBAR + 0x100047); | |
| 71 | writeb(v | 0xf0, MCF_IPSBAR + 0x100047); | |
| 72 | #else | |
| ffba3f48 GU |
73 | par = readw(MCF_IPSBAR + 0x100082); |
| 74 | writew(par | 0xf00, MCF_IPSBAR + 0x100082); | |
| 75 | v = readb(MCF_IPSBAR + 0x100078); | |
| 76 | writeb(v | 0xc0, MCF_IPSBAR + 0x100078); | |
| 77 | ||
| ffba3f48 GU |
78 | /* Set multi-function pins to ethernet mode for fec1 */ |
| 79 | par = readw(MCF_IPSBAR + 0x100082); | |
| 80 | writew(par | 0xa0, MCF_IPSBAR + 0x100082); | |
| 81 | v = readb(MCF_IPSBAR + 0x100079); | |
| 82 | writeb(v | 0xc0, MCF_IPSBAR + 0x100079); | |
| 83 | #endif | |
| 84 | } | |
| 85 | ||
| 86 | /***************************************************************************/ | |
| 87 | ||
| e206da0b | 88 | void __init config_BSP(char *commandp, int size) |
| 1da177e4 | 89 | { |
| 35aefb26 | 90 | mach_sched_init = hw_timer_init; |
| ffba3f48 GU |
91 | m527x_uarts_init(); |
| 92 | m527x_fec_init(); | |
| 83ca6009 | 93 | #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) |
| 91d60417 SK |
94 | m527x_qspi_init(); |
| 95 | #endif | |
| 1da177e4 LT |
96 | } |
| 97 | ||
| 98 | /***************************************************************************/ |