[deliverable/linux.git] / arch / m68k / platform / 54xx / config.c

/***************************************************************************/

/*
 *	linux/arch/m68knommu/platform/54xx/config.c
 *
 *	Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/pgalloc.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/m54xxsim.h>
#include <asm/mcfuart.h>
#include <asm/m54xxgpt.h>
#ifdef CONFIG_MMU
#include <asm/mmu_context.h>
#endif

/***************************************************************************/

static struct mcf_platform_uart m54xx_uart_platform[] = {
	{
		.mapbase	= MCFUART_BASE0,
		.irq		= MCF_IRQ_UART0,
	},
	{
		.mapbase	= MCFUART_BASE1,
		.irq		= MCF_IRQ_UART1,
	},
	{
		.mapbase	= MCFUART_BASE2,
		.irq		= MCF_IRQ_UART2,
	},
	{
		.mapbase	= MCFUART_BASE3,
		.irq		= MCF_IRQ_UART3,
	},
};

static struct platform_device m54xx_uart = {
	.name			= "mcfuart",
	.id			= 0,
	.dev.platform_data	= m54xx_uart_platform,
};

static struct platform_device *m54xx_devices[] __initdata = {
	&m54xx_uart,
};


/***************************************************************************/

static void __init m54xx_uart_init_line(int line, int irq)
{
	int rts_cts;

	/* enable io pins */
	switch (line) {
	case 0:
		rts_cts = 0; break;
	case 1:
		rts_cts = MCF_PAR_PSC_RTS_RTS; break;
	case 2:
		rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
	case 3:
		rts_cts = 0; break;
	}
	__raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
						MCF_MBAR + MCF_PAR_PSC(line));
}

static void __init m54xx_uarts_init(void)
{
	const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
	int line;

	for (line = 0; (line < nrlines); line++)
		m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
}

/***************************************************************************/

static void mcf54xx_reset(void)
{
	/* disable interrupts and enable the watchdog */
	asm("movew #0x2700, %sr\n");
	__raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
	__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
	__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
						MCF_MBAR + MCF_GPT_GMS0);
}

/***************************************************************************/

#ifdef CONFIG_MMU

unsigned long num_pages;

static void __init mcf54xx_bootmem_alloc(void)
{
	unsigned long start_pfn;
	unsigned long memstart;

	/* _rambase and _ramend will be naturally page aligned */
	m68k_memory[0].addr = _rambase;
	m68k_memory[0].size = _ramend - _rambase;

	/* compute total pages in system */
	num_pages = (_ramend - _rambase) >> PAGE_SHIFT;

	/* page numbers */
	memstart = PAGE_ALIGN(_ramstart);
	min_low_pfn = _rambase >> PAGE_SHIFT;
	start_pfn = memstart >> PAGE_SHIFT;
	max_low_pfn = _ramend >> PAGE_SHIFT;
	high_memory = (void *)_ramend;

	m68k_virt_to_node_shift = fls(_ramend - _rambase - 1) - 6;
	module_fixup(NULL, __start_fixup, __stop_fixup);

	/* setup bootmem data */
	m68k_setup_node(0);
	memstart += init_bootmem_node(NODE_DATA(0), start_pfn,
		min_low_pfn, max_low_pfn);
	free_bootmem_node(NODE_DATA(0), memstart, _ramend - memstart);
}

#endif /* CONFIG_MMU */

/***************************************************************************/

void __init config_BSP(char *commandp, int size)
{
#ifdef CONFIG_MMU
	mcf54xx_bootmem_alloc();
	mmu_context_init();
#endif
	mach_reset = mcf54xx_reset;
	mach_sched_init = hw_timer_init;
	m54xx_uarts_init();
}

/***************************************************************************/

static int __init init_BSP(void)
{

	platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
	return 0;
}

arch_initcall(init_BSP);

/***************************************************************************/
Commit	Line	Data
ea49f8ff PDM	1	/***************************************************************************/
	2
	3	/*
5b2e6555	4	* linux/arch/m68knommu/platform/54xx/config.c
ea49f8ff PDM	5	*
	6	* Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
	7	*/
	8
	9	/***************************************************************************/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/param.h>
	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
88be3515 GU	16	#include <linux/mm.h>
	17	#include <linux/bootmem.h>
	18	#include <asm/pgalloc.h>
ea49f8ff PDM	19	#include <asm/machdep.h>
ea49f8ff PDM	20	#include <asm/coldfire.h>
5b2e6555	21	#include <asm/m54xxsim.h>
ea49f8ff	22	#include <asm/mcfuart.h>
5b2e6555	23	#include <asm/m54xxgpt.h>
88be3515 GU	24	#ifdef CONFIG_MMU
	25	#include <asm/mmu_context.h>
	26	#endif
ea49f8ff PDM	27
	28	/***************************************************************************/
	29
5b2e6555	30	static struct mcf_platform_uart m54xx_uart_platform[] = {
ea49f8ff	31	{
bbbeeaf2 GU	32	.mapbase = MCFUART_BASE0,
bbbeeaf2 GU	33	.irq = MCF_IRQ_UART0,
ea49f8ff PDM	34	},
ea49f8ff PDM	35	{
bbbeeaf2 GU	36	.mapbase = MCFUART_BASE1,
bbbeeaf2 GU	37	.irq = MCF_IRQ_UART1,
ea49f8ff PDM	38	},
ea49f8ff PDM	39	{
bbbeeaf2 GU	40	.mapbase = MCFUART_BASE2,
bbbeeaf2 GU	41	.irq = MCF_IRQ_UART2,
ea49f8ff PDM	42	},
ea49f8ff PDM	43	{
bbbeeaf2 GU	44	.mapbase = MCFUART_BASE3,
bbbeeaf2 GU	45	.irq = MCF_IRQ_UART3,
ea49f8ff PDM	46	},
	47	};
	48
5b2e6555	49	static struct platform_device m54xx_uart = {
ea49f8ff PDM	50	.name = "mcfuart",
ea49f8ff PDM	51	.id = 0,
5b2e6555	52	.dev.platform_data = m54xx_uart_platform,
ea49f8ff PDM	53	};
ea49f8ff PDM	54
5b2e6555 GU	55	static struct platform_device *m54xx_devices[] __initdata = {
5b2e6555 GU	56	&m54xx_uart,
ea49f8ff PDM	57	};
	58
	59
	60	/***************************************************************************/
	61
5b2e6555	62	static void __init m54xx_uart_init_line(int line, int irq)
ea49f8ff PDM	63	{
	64	int rts_cts;
	65
	66	/* enable io pins */
	67	switch (line) {
	68	case 0:
	69	rts_cts = 0; break;
	70	case 1:
	71	rts_cts = MCF_PAR_PSC_RTS_RTS; break;
	72	case 2:
	73	rts_cts = MCF_PAR_PSC_RTS_RTS \| MCF_PAR_PSC_CTS_CTS; break;
	74	case 3:
	75	rts_cts = 0; break;
	76	}
	77	__raw_writeb(MCF_PAR_PSC_TXD \| rts_cts \| MCF_PAR_PSC_RXD,
	78	MCF_MBAR + MCF_PAR_PSC(line));
	79	}
	80
5b2e6555	81	static void __init m54xx_uarts_init(void)
ea49f8ff	82	{
5b2e6555	83	const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
ea49f8ff PDM	84	int line;
	85
	86	for (line = 0; (line < nrlines); line++)
5b2e6555	87	m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
ea49f8ff PDM	88	}
	89
	90	/***************************************************************************/
	91
5b2e6555	92	static void mcf54xx_reset(void)
ea49f8ff PDM	93	{
	94	/* disable interrupts and enable the watchdog */
	95	asm("movew #0x2700, %sr\n");
	96	__raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
	97	__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
	98	__raw_writel(MCF_GPT_GMS_WDEN \| MCF_GPT_GMS_CE \| MCF_GPT_GMS_TMS(4),
	99	MCF_MBAR + MCF_GPT_GMS0);
	100	}
	101
	102	/***************************************************************************/
	103
88be3515 GU	104	#ifdef CONFIG_MMU
	105
	106	unsigned long num_pages;
	107
	108	static void __init mcf54xx_bootmem_alloc(void)
	109	{
	110	unsigned long start_pfn;
	111	unsigned long memstart;
	112
	113	/* _rambase and _ramend will be naturally page aligned */
	114	m68k_memory[0].addr = _rambase;
	115	m68k_memory[0].size = _ramend - _rambase;
	116
	117	/* compute total pages in system */
	118	num_pages = (_ramend - _rambase) >> PAGE_SHIFT;
	119
	120	/* page numbers */
	121	memstart = PAGE_ALIGN(_ramstart);
	122	min_low_pfn = _rambase >> PAGE_SHIFT;
	123	start_pfn = memstart >> PAGE_SHIFT;
	124	max_low_pfn = _ramend >> PAGE_SHIFT;
	125	high_memory = (void *)_ramend;
	126
	127	m68k_virt_to_node_shift = fls(_ramend - _rambase - 1) - 6;
	128	module_fixup(NULL, __start_fixup, __stop_fixup);
	129
	130	/* setup bootmem data */
	131	m68k_setup_node(0);
	132	memstart += init_bootmem_node(NODE_DATA(0), start_pfn,
	133	min_low_pfn, max_low_pfn);
	134	free_bootmem_node(NODE_DATA(0), memstart, _ramend - memstart);
	135	}
	136
	137	#endif /* CONFIG_MMU */
	138
	139	/***************************************************************************/
	140
ea49f8ff PDM	141	void __init config_BSP(char *commandp, int size)
ea49f8ff PDM	142	{
88be3515 GU	143	#ifdef CONFIG_MMU
	144	mcf54xx_bootmem_alloc();
	145	mmu_context_init();
	146	#endif
5b2e6555	147	mach_reset = mcf54xx_reset;
35aefb26	148	mach_sched_init = hw_timer_init;
5b2e6555	149	m54xx_uarts_init();
ea49f8ff PDM	150	}
	151
	152	/***************************************************************************/
	153
	154	static int __init init_BSP(void)
	155	{
	156
5b2e6555	157	platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
ea49f8ff PDM	158	return 0;
	159	}
	160
	161	arch_initcall(init_BSP);
	162
	163	/***************************************************************************/