m68knommu: clean up ColdFire 532x CPU timer setup
[deliverable/linux.git] / arch / m68knommu / platform / 5206 / config.c
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1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5206/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com)
8 */
9
10/***************************************************************************/
11
1da177e4 12#include <linux/kernel.h>
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13#include <linux/param.h>
14#include <linux/init.h>
9685c43e 15#include <linux/io.h>
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16#include <asm/machdep.h>
17#include <asm/coldfire.h>
1da177e4 18#include <asm/mcfsim.h>
9685c43e 19#include <asm/mcfuart.h>
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20
21/***************************************************************************/
22
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23static struct mcf_platform_uart m5206_uart_platform[] = {
24 {
25 .mapbase = MCF_MBAR + MCFUART_BASE1,
26 .irq = 73,
27 },
28 {
29 .mapbase = MCF_MBAR + MCFUART_BASE2,
30 .irq = 74,
31 },
32 { },
33};
34
35static struct platform_device m5206_uart = {
36 .name = "mcfuart",
37 .id = 0,
38 .dev.platform_data = m5206_uart_platform,
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39};
40
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41static struct platform_device *m5206_devices[] __initdata = {
42 &m5206_uart,
43};
44
45/***************************************************************************/
46
47static void __init m5206_uart_init_line(int line, int irq)
48{
49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
f2154bef 52 mcf_clrimr(MCFINTC_UART0);
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53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
f2154bef 56 mcf_clrimr(MCFINTC_UART1);
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57 }
58}
59
60static void __init m5206_uarts_init(void)
61{
62 const int nrlines = ARRAY_SIZE(m5206_uart_platform);
63 int line;
64
65 for (line = 0; (line < nrlines); line++)
66 m5206_uart_init_line(line, m5206_uart_platform[line].irq);
67}
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68
69/***************************************************************************/
70
04b75b10 71static void __init m5206_timers_init(void)
1da177e4 72{
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73 /* Timer1 is always used as system timer */
74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 MCF_MBAR + MCFSIM_TIMER1ICR);
76
77#ifdef CONFIG_HIGHPROFILE
78 /* Timer2 is to be used as a high speed profile timer */
79 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
80 MCF_MBAR + MCFSIM_TIMER2ICR);
81#endif
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82}
83
84/***************************************************************************/
85
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86void m5206_cpu_reset(void)
87{
88 local_irq_disable();
89 /* Set watchdog to soft reset, and enabled */
90 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
91 for (;;)
92 /* wait for watchdog to timeout */;
93}
94
95/***************************************************************************/
96
9685c43e 97void __init config_BSP(char *commandp, int size)
1da177e4 98{
851377bc 99 mach_reset = m5206_cpu_reset;
04b75b10 100 m5206_timers_init();
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101}
102
103/***************************************************************************/
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104
105static int __init init_BSP(void)
106{
107 m5206_uarts_init();
108 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
109 return 0;
110}
111
112arch_initcall(init_BSP);
113
114/***************************************************************************/
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