[deliverable/linux.git] / arch / m68knommu / platform / 5272 / config.c

/***************************************************************************/

/*
 *	linux/arch/m68knommu/platform/5272/config.c
 *
 *	Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>

/***************************************************************************/

/*
 *	Some platforms need software versions of the GPIO data registers.
 */
unsigned short ppdata;
unsigned char ledbank = 0xff;

/***************************************************************************/

static struct mcf_platform_uart m5272_uart_platform[] = {
	{
		.mapbase	= MCF_MBAR + MCFUART_BASE1,
		.irq		= 73,
	},
	{
		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
		.irq		= 74,
	},
	{ },
};

static struct platform_device m5272_uart = {
	.name			= "mcfuart",
	.id			= 0,
	.dev.platform_data	= m5272_uart_platform,
};

static struct resource m5272_fec_resources[] = {
	{
		.start		= MCF_MBAR + 0x840,
		.end		= MCF_MBAR + 0x840 + 0x1cf,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= 86,
		.end		= 86,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 87,
		.end		= 87,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 88,
		.end		= 88,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device m5272_fec = {
	.name			= "fec",
	.id			= 0,
	.num_resources		= ARRAY_SIZE(m5272_fec_resources),
	.resource		= m5272_fec_resources,
};

static struct platform_device *m5272_devices[] __initdata = {
	&m5272_uart,
	&m5272_fec,
};

/***************************************************************************/

static void __init m5272_uart_init_line(int line, int irq)
{
	u32 v;

	if ((line >= 0) && (line < 2)) {
		v = (line) ? 0x0e000000 : 0xe0000000;
		writel(v, MCF_MBAR + MCFSIM_ICR2);

		/* Enable the output lines for the serial ports */
		v = readl(MCF_MBAR + MCFSIM_PBCNT);
		v = (v & ~0x000000ff) | 0x00000055;
		writel(v, MCF_MBAR + MCFSIM_PBCNT);

		v = readl(MCF_MBAR + MCFSIM_PDCNT);
		v = (v & ~0x000003fc) | 0x000002a8;
		writel(v, MCF_MBAR + MCFSIM_PDCNT);
	}
}

static void __init m5272_uarts_init(void)
{
	const int nrlines = ARRAY_SIZE(m5272_uart_platform);
	int line;

	for (line = 0; (line < nrlines); line++)
		m5272_uart_init_line(line, m5272_uart_platform[line].irq);
}

/***************************************************************************/

static void __init m5272_fec_init(void)
{
	u32 imr;

	/* Unmask FEC interrupts at ColdFire interrupt controller */
	imr = readl(MCF_MBAR + MCFSIM_ICR3);
	imr = (imr & ~0x00000fff) | 0x00000ddd;
	writel(imr, MCF_MBAR + MCFSIM_ICR3);

	imr = readl(MCF_MBAR + MCFSIM_ICR1);
	imr = (imr & ~0x0f000000) | 0x0d000000;
	writel(imr, MCF_MBAR + MCFSIM_ICR1);
}

/***************************************************************************/

void mcf_disableall(void)
{
	volatile unsigned long	*icrp;

	icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
	icrp[0] = 0x88888888;
	icrp[1] = 0x88888888;
	icrp[2] = 0x88888888;
	icrp[3] = 0x88888888;
}

/***************************************************************************/

static void __init m5272_timers_init(void)
{
	/* Timer1 @ level6 is always used as system timer */
	writel((0x8 | 0x6) << ((4 - 1) * 4), MCF_MBAR + MCFSIM_ICR1);

#ifdef CONFIG_HIGHPROFILE
	/* Timer2 @ level7 is to be used as a high speed profile timer  */
	writel((0x8 | 0x7) << ((4 - 2) * 4), MCF_MBAR + MCFSIM_ICR1);
#endif
}

/***************************************************************************/

static void m5272_cpu_reset(void)
{
	local_irq_disable();
	/* Set watchdog to reset, and enabled */
	__raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
	__raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
	__raw_writew(0, MCF_MBAR + MCFSIM_WCR);
	for (;;)
		/* wait for watchdog to timeout */;
}

/***************************************************************************/

void __init config_BSP(char *commandp, int size)
{
#if defined (CONFIG_MOD5272)
	volatile unsigned char	*pivrp;

	/* Set base of device vectors to be 64 */
	pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
	*pivrp = 0x40;
#endif

	mcf_disableall();

#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
	/* Copy command line from FLASH to local buffer... */
	memcpy(commandp, (char *) 0xf0004000, size);
	commandp[size-1] = 0;
#elif defined(CONFIG_CANCam)
	/* Copy command line from FLASH to local buffer... */
	memcpy(commandp, (char *) 0xf0010000, size);
	commandp[size-1] = 0;
#endif

	mach_reset = m5272_cpu_reset;
	m5272_timers_init();
}

/***************************************************************************/

static int __init init_BSP(void)
{
	m5272_uarts_init();
	m5272_fec_init();
	platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
	return 0;
}

arch_initcall(init_BSP);

/***************************************************************************/
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************/
	2
	3	/*
	4	* linux/arch/m68knommu/platform/5272/config.c
	5	*
	6	* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
	7	* Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
	8	*/
	9
	10	/***************************************************************************/
	11
1da177e4	12	#include <linux/kernel.h>
1da177e4 LT	13	#include <linux/param.h>
1da177e4 LT	14	#include <linux/init.h>
84e6defa	15	#include <linux/io.h>
1da177e4 LT	16	#include <asm/machdep.h>
1da177e4 LT	17	#include <asm/coldfire.h>
1da177e4	18	#include <asm/mcfsim.h>
84e6defa	19	#include <asm/mcfuart.h>
1da177e4 LT	20
	21	/***************************************************************************/
	22
1da177e4 LT	23	/*
	24	* Some platforms need software versions of the GPIO data registers.
	25	*/
	26	unsigned short ppdata;
	27	unsigned char ledbank = 0xff;
	28
	29	/***************************************************************************/
	30
84e6defa GU	31	static struct mcf_platform_uart m5272_uart_platform[] = {
	32	{
	33	.mapbase = MCF_MBAR + MCFUART_BASE1,
	34	.irq = 73,
	35	},
	36	{
	37	.mapbase = MCF_MBAR + MCFUART_BASE2,
	38	.irq = 74,
	39	},
	40	{ },
1da177e4 LT	41	};
1da177e4 LT	42
84e6defa GU	43	static struct platform_device m5272_uart = {
	44	.name = "mcfuart",
	45	.id = 0,
	46	.dev.platform_data = m5272_uart_platform,
	47	};
	48
ffba3f48 GU	49	static struct resource m5272_fec_resources[] = {
	50	{
	51	.start = MCF_MBAR + 0x840,
	52	.end = MCF_MBAR + 0x840 + 0x1cf,
	53	.flags = IORESOURCE_MEM,
	54	},
	55	{
	56	.start = 86,
	57	.end = 86,
	58	.flags = IORESOURCE_IRQ,
	59	},
	60	{
	61	.start = 87,
	62	.end = 87,
	63	.flags = IORESOURCE_IRQ,
	64	},
	65	{
	66	.start = 88,
	67	.end = 88,
	68	.flags = IORESOURCE_IRQ,
	69	},
	70	};
	71
	72	static struct platform_device m5272_fec = {
	73	.name = "fec",
	74	.id = 0,
	75	.num_resources = ARRAY_SIZE(m5272_fec_resources),
	76	.resource = m5272_fec_resources,
	77	};
	78
84e6defa GU	79	static struct platform_device *m5272_devices[] __initdata = {
84e6defa GU	80	&m5272_uart,
ffba3f48	81	&m5272_fec,
84e6defa GU	82	};
	83
	84	/***************************************************************************/
	85
	86	static void __init m5272_uart_init_line(int line, int irq)
	87	{
	88	u32 v;
	89
	90	if ((line >= 0) && (line < 2)) {
	91	v = (line) ? 0x0e000000 : 0xe0000000;
	92	writel(v, MCF_MBAR + MCFSIM_ICR2);
	93
	94	/* Enable the output lines for the serial ports */
	95	v = readl(MCF_MBAR + MCFSIM_PBCNT);
	96	v = (v & ~0x000000ff) \| 0x00000055;
	97	writel(v, MCF_MBAR + MCFSIM_PBCNT);
	98
	99	v = readl(MCF_MBAR + MCFSIM_PDCNT);
	100	v = (v & ~0x000003fc) \| 0x000002a8;
	101	writel(v, MCF_MBAR + MCFSIM_PDCNT);
	102	}
	103	}
	104
	105	static void __init m5272_uarts_init(void)
	106	{
	107	const int nrlines = ARRAY_SIZE(m5272_uart_platform);
	108	int line;
	109
	110	for (line = 0; (line < nrlines); line++)
	111	m5272_uart_init_line(line, m5272_uart_platform[line].irq);
	112	}
1da177e4 LT	113
	114	/***************************************************************************/
	115
ffba3f48 GU	116	static void __init m5272_fec_init(void)
	117	{
	118	u32 imr;
	119
	120	/* Unmask FEC interrupts at ColdFire interrupt controller */
	121	imr = readl(MCF_MBAR + MCFSIM_ICR3);
	122	imr = (imr & ~0x00000fff) \| 0x00000ddd;
	123	writel(imr, MCF_MBAR + MCFSIM_ICR3);
	124
	125	imr = readl(MCF_MBAR + MCFSIM_ICR1);
	126	imr = (imr & ~0x0f000000) \| 0x0d000000;
	127	writel(imr, MCF_MBAR + MCFSIM_ICR1);
	128	}
	129
	130	/***************************************************************************/
	131
1da177e4 LT	132	void mcf_disableall(void)
	133	{
	134	volatile unsigned long *icrp;
	135
	136	icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
	137	icrp[0] = 0x88888888;
	138	icrp[1] = 0x88888888;
	139	icrp[2] = 0x88888888;
	140	icrp[3] = 0x88888888;
	141	}
	142
	143	/***************************************************************************/
	144
04b75b10	145	static void __init m5272_timers_init(void)
1da177e4	146	{
04b75b10 GU	147	/* Timer1 @ level6 is always used as system timer */
04b75b10 GU	148	writel((0x8 \| 0x6) << ((4 - 1) * 4), MCF_MBAR + MCFSIM_ICR1);
1da177e4	149
04b75b10 GU	150	#ifdef CONFIG_HIGHPROFILE
	151	/* Timer2 @ level7 is to be used as a high speed profile timer */
	152	writel((0x8 \| 0x7) << ((4 - 2) * 4), MCF_MBAR + MCFSIM_ICR1);
	153	#endif
1da177e4 LT	154	}
	155
	156	/***************************************************************************/
	157
05728aec GU	158	static void m5272_cpu_reset(void)
	159	{
	160	local_irq_disable();
	161	/* Set watchdog to reset, and enabled */
	162	__raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
	163	__raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
	164	__raw_writew(0, MCF_MBAR + MCFSIM_WCR);
	165	for (;;)
	166	/* wait for watchdog to timeout */;
	167	}
	168
	169	/***************************************************************************/
	170
84e6defa	171	void __init config_BSP(char *commandp, int size)
1da177e4	172	{
a7962660 GU	173	#if defined (CONFIG_MOD5272)
a7962660 GU	174	volatile unsigned char *pivrp;
1da177e4 LT	175
1da177e4 LT	176	/* Set base of device vectors to be 64 */
a7962660	177	pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
1da177e4 LT	178	*pivrp = 0x40;
	179	#endif
	180
	181	mcf_disableall();
	182
bc72450a	183	#if defined(CONFIG_NETtel) \|\| defined(CONFIG_SCALES)
1da177e4 LT	184	/* Copy command line from FLASH to local buffer... */
	185	memcpy(commandp, (char *) 0xf0004000, size);
	186	commandp[size-1] = 0;
1da177e4 LT	187	#elif defined(CONFIG_CANCam)
	188	/* Copy command line from FLASH to local buffer... */
	189	memcpy(commandp, (char *) 0xf0010000, size);
	190	commandp[size-1] = 0;
1da177e4 LT	191	#endif
1da177e4 LT	192
05728aec	193	mach_reset = m5272_cpu_reset;
04b75b10	194	m5272_timers_init();
1da177e4 LT	195	}
	196
	197	/***************************************************************************/
84e6defa GU	198
	199	static int __init init_BSP(void)
	200	{
	201	m5272_uarts_init();
ffba3f48	202	m5272_fec_init();
84e6defa GU	203	platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
	204	return 0;
	205	}
	206
	207	arch_initcall(init_BSP);
	208
	209	/***************************************************************************/