[deliverable/linux.git] / arch / m68knommu / platform / 527x / config.c

/***************************************************************************/

/*
 *	linux/arch/m68knommu/platform/527x/config.c
 *
 *	Sub-architcture dependant initialization code for the Freescale
 *	5270/5271 CPUs.
 *
 *	Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>

/***************************************************************************/

static struct mcf_platform_uart m527x_uart_platform[] = {
	{
		.mapbase	= MCF_MBAR + MCFUART_BASE1,
		.irq		= MCFINT_VECBASE + MCFINT_UART0,
	},
	{
		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
		.irq		= MCFINT_VECBASE + MCFINT_UART1,
	},
	{
		.mapbase 	= MCF_MBAR + MCFUART_BASE3,
		.irq		= MCFINT_VECBASE + MCFINT_UART2,
	},
	{ },
};

static struct platform_device m527x_uart = {
	.name			= "mcfuart",
	.id			= 0,
	.dev.platform_data	= m527x_uart_platform,
};

static struct resource m527x_fec0_resources[] = {
	{
		.start		= MCF_MBAR + 0x1000,
		.end		= MCF_MBAR + 0x1000 + 0x7ff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= 64 + 23,
		.end		= 64 + 23,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 64 + 27,
		.end		= 64 + 27,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 64 + 29,
		.end		= 64 + 29,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct resource m527x_fec1_resources[] = {
	{
		.start		= MCF_MBAR + 0x1800,
		.end		= MCF_MBAR + 0x1800 + 0x7ff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= 128 + 23,
		.end		= 128 + 23,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 128 + 27,
		.end		= 128 + 27,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 128 + 29,
		.end		= 128 + 29,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device m527x_fec[] = {
	{
		.name		= "fec",
		.id		= 0,
		.num_resources	= ARRAY_SIZE(m527x_fec0_resources),
		.resource	= m527x_fec0_resources,
	},
	{
		.name		= "fec",
		.id		= 1,
		.num_resources	= ARRAY_SIZE(m527x_fec1_resources),
		.resource	= m527x_fec1_resources,
	},
};

static struct platform_device *m527x_devices[] __initdata = {
	&m527x_uart,
	&m527x_fec[0],
#ifdef CONFIG_FEC2
	&m527x_fec[1],
#endif
};

/***************************************************************************/

static void __init m527x_uart_init_line(int line, int irq)
{
	u16 sepmask;

	if ((line < 0) || (line > 2))
		return;

	/*
	 * External Pin Mask Setting & Enable External Pin for Interface
	 */
	sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
	if (line == 0)
		sepmask |= UART0_ENABLE_MASK;
	else if (line == 1)
		sepmask |= UART1_ENABLE_MASK;
	else if (line == 2)
		sepmask |= UART2_ENABLE_MASK;
	writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
}

static void __init m527x_uarts_init(void)
{
	const int nrlines = ARRAY_SIZE(m527x_uart_platform);
	int line;

	for (line = 0; (line < nrlines); line++)
		m527x_uart_init_line(line, m527x_uart_platform[line].irq);
}

/***************************************************************************/

static void __init m527x_fec_init(void)
{
	u16 par;
	u8 v;

	/* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271)
	v = readb(MCF_IPSBAR + 0x100047);
	writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
#else
	par = readw(MCF_IPSBAR + 0x100082);
	writew(par | 0xf00, MCF_IPSBAR + 0x100082);
	v = readb(MCF_IPSBAR + 0x100078);
	writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
#endif

#ifdef CONFIG_FEC2
	/* Set multi-function pins to ethernet mode for fec1 */
	par = readw(MCF_IPSBAR + 0x100082);
	writew(par | 0xa0, MCF_IPSBAR + 0x100082);
	v = readb(MCF_IPSBAR + 0x100079);
	writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
#endif
}

/***************************************************************************/

static void m527x_cpu_reset(void)
{
	local_irq_disable();
	__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
}

/***************************************************************************/

void __init config_BSP(char *commandp, int size)
{
	mach_reset = m527x_cpu_reset;
	m527x_uarts_init();
	m527x_fec_init();
}

/***************************************************************************/

static int __init init_BSP(void)
{
	platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
	return 0;
}

arch_initcall(init_BSP);

/***************************************************************************/
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************/
	2
	3	/*
	4	* linux/arch/m68knommu/platform/527x/config.c
	5	*
	6	* Sub-architcture dependant initialization code for the Freescale
	7	* 5270/5271 CPUs.
	8	*
	9	* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
	10	* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
	11	*/
	12
	13	/***************************************************************************/
	14
1da177e4	15	#include <linux/kernel.h>
1da177e4 LT	16	#include <linux/param.h>
1da177e4 LT	17	#include <linux/init.h>
e206da0b	18	#include <linux/io.h>
1da177e4 LT	19	#include <asm/machdep.h>
	20	#include <asm/coldfire.h>
	21	#include <asm/mcfsim.h>
e206da0b	22	#include <asm/mcfuart.h>
1da177e4 LT	23
	24	/***************************************************************************/
	25
e206da0b GU	26	static struct mcf_platform_uart m527x_uart_platform[] = {
	27	{
	28	.mapbase = MCF_MBAR + MCFUART_BASE1,
	29	.irq = MCFINT_VECBASE + MCFINT_UART0,
	30	},
	31	{
	32	.mapbase = MCF_MBAR + MCFUART_BASE2,
	33	.irq = MCFINT_VECBASE + MCFINT_UART1,
	34	},
	35	{
	36	.mapbase = MCF_MBAR + MCFUART_BASE3,
	37	.irq = MCFINT_VECBASE + MCFINT_UART2,
	38	},
	39	{ },
1da177e4 LT	40	};
1da177e4 LT	41
e206da0b GU	42	static struct platform_device m527x_uart = {
	43	.name = "mcfuart",
	44	.id = 0,
	45	.dev.platform_data = m527x_uart_platform,
	46	};
	47
ffba3f48 GU	48	static struct resource m527x_fec0_resources[] = {
	49	{
	50	.start = MCF_MBAR + 0x1000,
	51	.end = MCF_MBAR + 0x1000 + 0x7ff,
	52	.flags = IORESOURCE_MEM,
	53	},
	54	{
	55	.start = 64 + 23,
	56	.end = 64 + 23,
	57	.flags = IORESOURCE_IRQ,
	58	},
	59	{
	60	.start = 64 + 27,
	61	.end = 64 + 27,
	62	.flags = IORESOURCE_IRQ,
	63	},
	64	{
	65	.start = 64 + 29,
	66	.end = 64 + 29,
	67	.flags = IORESOURCE_IRQ,
	68	},
	69	};
	70
	71	static struct resource m527x_fec1_resources[] = {
	72	{
	73	.start = MCF_MBAR + 0x1800,
	74	.end = MCF_MBAR + 0x1800 + 0x7ff,
	75	.flags = IORESOURCE_MEM,
	76	},
	77	{
	78	.start = 128 + 23,
	79	.end = 128 + 23,
	80	.flags = IORESOURCE_IRQ,
	81	},
	82	{
	83	.start = 128 + 27,
	84	.end = 128 + 27,
	85	.flags = IORESOURCE_IRQ,
	86	},
	87	{
	88	.start = 128 + 29,
	89	.end = 128 + 29,
	90	.flags = IORESOURCE_IRQ,
	91	},
	92	};
	93
	94	static struct platform_device m527x_fec[] = {
	95	{
	96	.name = "fec",
	97	.id = 0,
	98	.num_resources = ARRAY_SIZE(m527x_fec0_resources),
	99	.resource = m527x_fec0_resources,
	100	},
	101	{
	102	.name = "fec",
	103	.id = 1,
	104	.num_resources = ARRAY_SIZE(m527x_fec1_resources),
	105	.resource = m527x_fec1_resources,
	106	},
	107	};
	108
e206da0b GU	109	static struct platform_device *m527x_devices[] __initdata = {
e206da0b GU	110	&m527x_uart,
ffba3f48 GU	111	&m527x_fec[0],
	112	#ifdef CONFIG_FEC2
	113	&m527x_fec[1],
	114	#endif
e206da0b GU	115	};
	116
	117	/***************************************************************************/
	118
e206da0b GU	119	static void __init m527x_uart_init_line(int line, int irq)
	120	{
	121	u16 sepmask;
e206da0b GU	122
	123	if ((line < 0) \|\| (line > 2))
	124	return;
	125
e206da0b GU	126	/*
	127	* External Pin Mask Setting & Enable External Pin for Interface
	128	*/
	129	sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
	130	if (line == 0)
	131	sepmask \|= UART0_ENABLE_MASK;
	132	else if (line == 1)
	133	sepmask \|= UART1_ENABLE_MASK;
	134	else if (line == 2)
	135	sepmask \|= UART2_ENABLE_MASK;
	136	writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
	137	}
	138
	139	static void __init m527x_uarts_init(void)
	140	{
	141	const int nrlines = ARRAY_SIZE(m527x_uart_platform);
	142	int line;
	143
	144	for (line = 0; (line < nrlines); line++)
	145	m527x_uart_init_line(line, m527x_uart_platform[line].irq);
	146	}
1da177e4 LT	147
	148	/***************************************************************************/
	149
ffba3f48 GU	150	static void __init m527x_fec_init(void)
	151	{
	152	u16 par;
	153	u8 v;
	154
ffba3f48	155	/* Set multi-function pins to ethernet mode for fec0 */
592578a1 RR	156	#if defined(CONFIG_M5271)
	157	v = readb(MCF_IPSBAR + 0x100047);
	158	writeb(v \| 0xf0, MCF_IPSBAR + 0x100047);
	159	#else
ffba3f48 GU	160	par = readw(MCF_IPSBAR + 0x100082);
	161	writew(par \| 0xf00, MCF_IPSBAR + 0x100082);
	162	v = readb(MCF_IPSBAR + 0x100078);
	163	writeb(v \| 0xc0, MCF_IPSBAR + 0x100078);
592578a1	164	#endif
ffba3f48 GU	165
ffba3f48 GU	166	#ifdef CONFIG_FEC2
ffba3f48 GU	167	/* Set multi-function pins to ethernet mode for fec1 */
	168	par = readw(MCF_IPSBAR + 0x100082);
	169	writew(par \| 0xa0, MCF_IPSBAR + 0x100082);
	170	v = readb(MCF_IPSBAR + 0x100079);
	171	writeb(v \| 0xc0, MCF_IPSBAR + 0x100079);
	172	#endif
	173	}
	174
	175	/***************************************************************************/
	176
4c0b008d GU	177	static void m527x_cpu_reset(void)
	178	{
	179	local_irq_disable();
	180	__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
	181	}
	182
	183	/***************************************************************************/
	184
e206da0b	185	void __init config_BSP(char *commandp, int size)
1da177e4	186	{
4c0b008d	187	mach_reset = m527x_cpu_reset;
ffba3f48 GU	188	m527x_uarts_init();
ffba3f48 GU	189	m527x_fec_init();
1da177e4 LT	190	}
	191
	192	/***************************************************************************/
e206da0b GU	193
	194	static int __init init_BSP(void)
	195	{
e206da0b GU	196	platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
	197	return 0;
	198	}
	199
	200	arch_initcall(init_BSP);
	201
	202	/***************************************************************************/