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42682c6c JH |
1 | /* |
2 | * Copyright (C) 2009,2010,2011 Imagination Technologies Ltd. | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/atomic.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
17 | #include <linux/profile.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/bootmem.h> | |
26 | ||
27 | #include <asm/cacheflush.h> | |
28 | #include <asm/cachepart.h> | |
29 | #include <asm/core_reg.h> | |
30 | #include <asm/cpu.h> | |
31 | #include <asm/mmu_context.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/processor.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/tlbflush.h> | |
37 | #include <asm/hwthread.h> | |
38 | #include <asm/traps.h> | |
39 | ||
40 | DECLARE_PER_CPU(PTBI, pTBI); | |
41 | ||
42 | void *secondary_data_stack; | |
43 | ||
44 | /* | |
45 | * structures for inter-processor calls | |
46 | * - A collection of single bit ipi messages. | |
47 | */ | |
48 | struct ipi_data { | |
49 | spinlock_t lock; | |
50 | unsigned long ipi_count; | |
51 | unsigned long bits; | |
52 | }; | |
53 | ||
54 | static DEFINE_PER_CPU(struct ipi_data, ipi_data) = { | |
55 | .lock = __SPIN_LOCK_UNLOCKED(ipi_data.lock), | |
56 | }; | |
57 | ||
58 | static DEFINE_SPINLOCK(boot_lock); | |
59 | ||
60 | /* | |
61 | * "thread" is assumed to be a valid Meta hardware thread ID. | |
62 | */ | |
63 | int __cpuinit boot_secondary(unsigned int thread, struct task_struct *idle) | |
64 | { | |
65 | u32 val; | |
66 | ||
67 | /* | |
68 | * set synchronisation state between this boot processor | |
69 | * and the secondary one | |
70 | */ | |
71 | spin_lock(&boot_lock); | |
72 | ||
73 | core_reg_write(TXUPC_ID, 0, thread, (unsigned int)secondary_startup); | |
74 | core_reg_write(TXUPC_ID, 1, thread, 0); | |
75 | ||
76 | /* | |
77 | * Give the thread privilege (PSTAT) and clear potentially problematic | |
78 | * bits in the process (namely ISTAT, CBMarker, CBMarkerI, LSM_STEP). | |
79 | */ | |
80 | core_reg_write(TXUCT_ID, TXSTATUS_REGNUM, thread, TXSTATUS_PSTAT_BIT); | |
81 | ||
82 | /* Clear the minim enable bit. */ | |
83 | val = core_reg_read(TXUCT_ID, TXPRIVEXT_REGNUM, thread); | |
84 | core_reg_write(TXUCT_ID, TXPRIVEXT_REGNUM, thread, val & ~0x80); | |
85 | ||
86 | /* | |
87 | * set the ThreadEnable bit (0x1) in the TXENABLE register | |
88 | * for the specified thread - off it goes! | |
89 | */ | |
90 | val = core_reg_read(TXUCT_ID, TXENABLE_REGNUM, thread); | |
91 | core_reg_write(TXUCT_ID, TXENABLE_REGNUM, thread, val | 0x1); | |
92 | ||
93 | /* | |
94 | * now the secondary core is starting up let it run its | |
95 | * calibrations, then wait for it to finish | |
96 | */ | |
97 | spin_unlock(&boot_lock); | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
102 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) | |
103 | { | |
104 | unsigned int thread = cpu_2_hwthread_id[cpu]; | |
105 | int ret; | |
106 | ||
107 | load_pgd(swapper_pg_dir, thread); | |
108 | ||
109 | flush_tlb_all(); | |
110 | ||
111 | /* | |
112 | * Tell the secondary CPU where to find its idle thread's stack. | |
113 | */ | |
114 | secondary_data_stack = task_stack_page(idle); | |
115 | ||
116 | wmb(); | |
117 | ||
118 | /* | |
119 | * Now bring the CPU into our world. | |
120 | */ | |
121 | ret = boot_secondary(thread, idle); | |
122 | if (ret == 0) { | |
123 | unsigned long timeout; | |
124 | ||
125 | /* | |
126 | * CPU was successfully started, wait for it | |
127 | * to come online or time out. | |
128 | */ | |
129 | timeout = jiffies + HZ; | |
130 | while (time_before(jiffies, timeout)) { | |
131 | if (cpu_online(cpu)) | |
132 | break; | |
133 | ||
134 | udelay(10); | |
135 | barrier(); | |
136 | } | |
137 | ||
138 | if (!cpu_online(cpu)) | |
139 | ret = -EIO; | |
140 | } | |
141 | ||
142 | secondary_data_stack = NULL; | |
143 | ||
144 | if (ret) { | |
145 | pr_crit("CPU%u: processor failed to boot\n", cpu); | |
146 | ||
147 | /* | |
148 | * FIXME: We need to clean up the new idle thread. --rmk | |
149 | */ | |
150 | } | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
155 | #ifdef CONFIG_HOTPLUG_CPU | |
156 | static DECLARE_COMPLETION(cpu_killed); | |
157 | ||
158 | /* | |
159 | * __cpu_disable runs on the processor to be shutdown. | |
160 | */ | |
161 | int __cpuexit __cpu_disable(void) | |
162 | { | |
163 | unsigned int cpu = smp_processor_id(); | |
164 | struct task_struct *p; | |
165 | ||
166 | /* | |
167 | * Take this CPU offline. Once we clear this, we can't return, | |
168 | * and we must not schedule until we're ready to give up the cpu. | |
169 | */ | |
170 | set_cpu_online(cpu, false); | |
171 | ||
172 | /* | |
173 | * OK - migrate IRQs away from this CPU | |
174 | */ | |
175 | migrate_irqs(); | |
176 | ||
177 | /* | |
178 | * Flush user cache and TLB mappings, and then remove this CPU | |
179 | * from the vm mask set of all processes. | |
180 | */ | |
181 | flush_cache_all(); | |
182 | local_flush_tlb_all(); | |
183 | ||
184 | read_lock(&tasklist_lock); | |
185 | for_each_process(p) { | |
186 | if (p->mm) | |
187 | cpumask_clear_cpu(cpu, mm_cpumask(p->mm)); | |
188 | } | |
189 | read_unlock(&tasklist_lock); | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | /* | |
195 | * called on the thread which is asking for a CPU to be shutdown - | |
196 | * waits until shutdown has completed, or it is timed out. | |
197 | */ | |
198 | void __cpuexit __cpu_die(unsigned int cpu) | |
199 | { | |
200 | if (!wait_for_completion_timeout(&cpu_killed, msecs_to_jiffies(1))) | |
201 | pr_err("CPU%u: unable to kill\n", cpu); | |
202 | } | |
203 | ||
204 | /* | |
205 | * Called from the idle thread for the CPU which has been shutdown. | |
206 | * | |
207 | * Note that we do not return from this function. If this cpu is | |
208 | * brought online again it will need to run secondary_startup(). | |
209 | */ | |
210 | void __cpuexit cpu_die(void) | |
211 | { | |
212 | local_irq_disable(); | |
213 | idle_task_exit(); | |
214 | ||
215 | complete(&cpu_killed); | |
216 | ||
217 | asm ("XOR TXENABLE, D0Re0,D0Re0\n"); | |
218 | } | |
219 | #endif /* CONFIG_HOTPLUG_CPU */ | |
220 | ||
221 | /* | |
222 | * Called by both boot and secondaries to move global data into | |
223 | * per-processor storage. | |
224 | */ | |
225 | void __cpuinit smp_store_cpu_info(unsigned int cpuid) | |
226 | { | |
227 | struct cpuinfo_metag *cpu_info = &per_cpu(cpu_data, cpuid); | |
228 | ||
229 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
230 | } | |
231 | ||
232 | /* | |
233 | * This is the secondary CPU boot entry. We're using this CPUs | |
234 | * idle thread stack and the global page tables. | |
235 | */ | |
236 | asmlinkage void secondary_start_kernel(void) | |
237 | { | |
238 | struct mm_struct *mm = &init_mm; | |
239 | unsigned int cpu = smp_processor_id(); | |
240 | ||
241 | /* | |
242 | * All kernel threads share the same mm context; grab a | |
243 | * reference and switch to it. | |
244 | */ | |
245 | atomic_inc(&mm->mm_users); | |
246 | atomic_inc(&mm->mm_count); | |
247 | current->active_mm = mm; | |
248 | cpumask_set_cpu(cpu, mm_cpumask(mm)); | |
249 | enter_lazy_tlb(mm, current); | |
250 | local_flush_tlb_all(); | |
251 | ||
252 | /* | |
253 | * TODO: Some day it might be useful for each Linux CPU to | |
254 | * have its own TBI structure. That would allow each Linux CPU | |
255 | * to run different interrupt handlers for the same IRQ | |
256 | * number. | |
257 | * | |
258 | * For now, simply copying the pointer to the boot CPU's TBI | |
259 | * structure is sufficient because we always want to run the | |
260 | * same interrupt handler whatever CPU takes the interrupt. | |
261 | */ | |
262 | per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT); | |
263 | ||
264 | if (!per_cpu(pTBI, cpu)) | |
265 | panic("No TBI found!"); | |
266 | ||
267 | per_cpu_trap_init(cpu); | |
268 | ||
269 | preempt_disable(); | |
270 | ||
271 | setup_txprivext(); | |
272 | ||
273 | /* | |
274 | * Enable local interrupts. | |
275 | */ | |
276 | tbi_startup_interrupt(TBID_SIGNUM_TRT); | |
277 | notify_cpu_starting(cpu); | |
278 | local_irq_enable(); | |
279 | ||
280 | pr_info("CPU%u (thread %u): Booted secondary processor\n", | |
281 | cpu, cpu_2_hwthread_id[cpu]); | |
282 | ||
283 | calibrate_delay(); | |
284 | smp_store_cpu_info(cpu); | |
285 | ||
286 | /* | |
287 | * OK, now it's safe to let the boot CPU continue | |
288 | */ | |
289 | set_cpu_online(cpu, true); | |
290 | ||
291 | /* | |
292 | * Check for cache aliasing. | |
293 | * Preemption is disabled | |
294 | */ | |
295 | check_for_cache_aliasing(cpu); | |
296 | ||
297 | /* | |
298 | * OK, it's off to the idle thread for us | |
299 | */ | |
300 | cpu_idle(); | |
301 | } | |
302 | ||
303 | void __init smp_cpus_done(unsigned int max_cpus) | |
304 | { | |
305 | int cpu; | |
306 | unsigned long bogosum = 0; | |
307 | ||
308 | for_each_online_cpu(cpu) | |
309 | bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; | |
310 | ||
311 | pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
312 | num_online_cpus(), | |
313 | bogosum / (500000/HZ), | |
314 | (bogosum / (5000/HZ)) % 100); | |
315 | } | |
316 | ||
317 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
318 | { | |
319 | unsigned int cpu = smp_processor_id(); | |
320 | ||
321 | init_new_context(current, &init_mm); | |
322 | current_thread_info()->cpu = cpu; | |
323 | ||
324 | smp_store_cpu_info(cpu); | |
325 | init_cpu_present(cpu_possible_mask); | |
326 | } | |
327 | ||
328 | void __init smp_prepare_boot_cpu(void) | |
329 | { | |
330 | unsigned int cpu = smp_processor_id(); | |
331 | ||
332 | per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT); | |
333 | ||
334 | if (!per_cpu(pTBI, cpu)) | |
335 | panic("No TBI found!"); | |
336 | } | |
337 | ||
338 | static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg); | |
339 | ||
340 | static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg) | |
341 | { | |
342 | unsigned long flags; | |
343 | unsigned int cpu; | |
344 | cpumask_t map; | |
345 | ||
346 | cpumask_clear(&map); | |
347 | local_irq_save(flags); | |
348 | ||
349 | for_each_cpu(cpu, mask) { | |
350 | struct ipi_data *ipi = &per_cpu(ipi_data, cpu); | |
351 | ||
352 | spin_lock(&ipi->lock); | |
353 | ||
354 | /* | |
355 | * KICK interrupts are queued in hardware so we'll get | |
356 | * multiple interrupts if we call smp_cross_call() | |
357 | * multiple times for one msg. The problem is that we | |
358 | * only have one bit for each message - we can't queue | |
359 | * them in software. | |
360 | * | |
361 | * The first time through ipi_handler() we'll clear | |
362 | * the msg bit, having done all the work. But when we | |
363 | * return we'll get _another_ interrupt (and another, | |
364 | * and another until we've handled all the queued | |
365 | * KICKs). Running ipi_handler() when there's no work | |
366 | * to do is bad because that's how kick handler | |
367 | * chaining detects who the KICK was intended for. | |
368 | * See arch/metag/kernel/kick.c for more details. | |
369 | * | |
370 | * So only add 'cpu' to 'map' if we haven't already | |
371 | * queued a KICK interrupt for 'msg'. | |
372 | */ | |
373 | if (!(ipi->bits & (1 << msg))) { | |
374 | ipi->bits |= 1 << msg; | |
375 | cpumask_set_cpu(cpu, &map); | |
376 | } | |
377 | ||
378 | spin_unlock(&ipi->lock); | |
379 | } | |
380 | ||
381 | /* | |
382 | * Call the platform specific cross-CPU call function. | |
383 | */ | |
384 | smp_cross_call(map, msg); | |
385 | ||
386 | local_irq_restore(flags); | |
387 | } | |
388 | ||
389 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
390 | { | |
391 | send_ipi_message(mask, IPI_CALL_FUNC); | |
392 | } | |
393 | ||
394 | void arch_send_call_function_single_ipi(int cpu) | |
395 | { | |
396 | send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); | |
397 | } | |
398 | ||
399 | void show_ipi_list(struct seq_file *p) | |
400 | { | |
401 | unsigned int cpu; | |
402 | ||
403 | seq_puts(p, "IPI:"); | |
404 | ||
405 | for_each_present_cpu(cpu) | |
406 | seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count); | |
407 | ||
408 | seq_putc(p, '\n'); | |
409 | } | |
410 | ||
411 | static DEFINE_SPINLOCK(stop_lock); | |
412 | ||
413 | /* | |
414 | * Main handler for inter-processor interrupts | |
415 | * | |
416 | * For Meta, the ipimask now only identifies a single | |
417 | * category of IPI (Bit 1 IPIs have been replaced by a | |
418 | * different mechanism): | |
419 | * | |
420 | * Bit 0 - Inter-processor function call | |
421 | */ | |
422 | static int do_IPI(struct pt_regs *regs) | |
423 | { | |
424 | unsigned int cpu = smp_processor_id(); | |
425 | struct ipi_data *ipi = &per_cpu(ipi_data, cpu); | |
426 | struct pt_regs *old_regs = set_irq_regs(regs); | |
427 | unsigned long msgs, nextmsg; | |
428 | int handled = 0; | |
429 | ||
430 | ipi->ipi_count++; | |
431 | ||
432 | spin_lock(&ipi->lock); | |
433 | msgs = ipi->bits; | |
434 | nextmsg = msgs & -msgs; | |
435 | ipi->bits &= ~nextmsg; | |
436 | spin_unlock(&ipi->lock); | |
437 | ||
438 | if (nextmsg) { | |
439 | handled = 1; | |
440 | ||
441 | nextmsg = ffz(~nextmsg); | |
442 | switch (nextmsg) { | |
443 | case IPI_RESCHEDULE: | |
444 | scheduler_ipi(); | |
445 | break; | |
446 | ||
447 | case IPI_CALL_FUNC: | |
448 | generic_smp_call_function_interrupt(); | |
449 | break; | |
450 | ||
451 | case IPI_CALL_FUNC_SINGLE: | |
452 | generic_smp_call_function_single_interrupt(); | |
453 | break; | |
454 | ||
455 | default: | |
456 | pr_crit("CPU%u: Unknown IPI message 0x%lx\n", | |
457 | cpu, nextmsg); | |
458 | break; | |
459 | } | |
460 | } | |
461 | ||
462 | set_irq_regs(old_regs); | |
463 | ||
464 | return handled; | |
465 | } | |
466 | ||
467 | void smp_send_reschedule(int cpu) | |
468 | { | |
469 | send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); | |
470 | } | |
471 | ||
472 | static void stop_this_cpu(void *data) | |
473 | { | |
474 | unsigned int cpu = smp_processor_id(); | |
475 | ||
476 | if (system_state == SYSTEM_BOOTING || | |
477 | system_state == SYSTEM_RUNNING) { | |
478 | spin_lock(&stop_lock); | |
479 | pr_crit("CPU%u: stopping\n", cpu); | |
480 | dump_stack(); | |
481 | spin_unlock(&stop_lock); | |
482 | } | |
483 | ||
484 | set_cpu_online(cpu, false); | |
485 | ||
486 | local_irq_disable(); | |
487 | ||
488 | hard_processor_halt(HALT_OK); | |
489 | } | |
490 | ||
491 | void smp_send_stop(void) | |
492 | { | |
493 | smp_call_function(stop_this_cpu, NULL, 0); | |
494 | } | |
495 | ||
496 | /* | |
497 | * not supported here | |
498 | */ | |
499 | int setup_profiling_timer(unsigned int multiplier) | |
500 | { | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | /* | |
505 | * We use KICKs for inter-processor interrupts. | |
506 | * | |
507 | * For every CPU in "callmap" the IPI data must already have been | |
508 | * stored in that CPU's "ipi_data" member prior to calling this | |
509 | * function. | |
510 | */ | |
511 | static void kick_raise_softirq(cpumask_t callmap, unsigned int irq) | |
512 | { | |
513 | int cpu; | |
514 | ||
515 | for_each_cpu(cpu, &callmap) { | |
516 | unsigned int thread; | |
517 | ||
518 | thread = cpu_2_hwthread_id[cpu]; | |
519 | ||
520 | BUG_ON(thread == BAD_HWTHREAD_ID); | |
521 | ||
522 | metag_out32(1, T0KICKI + (thread * TnXKICK_STRIDE)); | |
523 | } | |
524 | } | |
525 | ||
526 | static TBIRES ipi_handler(TBIRES State, int SigNum, int Triggers, | |
527 | int Inst, PTBI pTBI, int *handled) | |
528 | { | |
529 | *handled = do_IPI((struct pt_regs *)State.Sig.pCtx); | |
530 | ||
531 | return State; | |
532 | } | |
533 | ||
534 | static struct kick_irq_handler ipi_irq = { | |
535 | .func = ipi_handler, | |
536 | }; | |
537 | ||
538 | static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg) | |
539 | { | |
540 | kick_raise_softirq(callmap, 1); | |
541 | } | |
542 | ||
543 | static inline unsigned int get_core_count(void) | |
544 | { | |
545 | int i; | |
546 | unsigned int ret = 0; | |
547 | ||
548 | for (i = 0; i < CONFIG_NR_CPUS; i++) { | |
549 | if (core_reg_read(TXUCT_ID, TXENABLE_REGNUM, i)) | |
550 | ret++; | |
551 | } | |
552 | ||
553 | return ret; | |
554 | } | |
555 | ||
556 | /* | |
557 | * Initialise the CPU possible map early - this describes the CPUs | |
558 | * which may be present or become present in the system. | |
559 | */ | |
560 | void __init smp_init_cpus(void) | |
561 | { | |
562 | unsigned int i, ncores = get_core_count(); | |
563 | ||
564 | /* If no hwthread_map early param was set use default mapping */ | |
565 | for (i = 0; i < NR_CPUS; i++) | |
566 | if (cpu_2_hwthread_id[i] == BAD_HWTHREAD_ID) { | |
567 | cpu_2_hwthread_id[i] = i; | |
568 | hwthread_id_2_cpu[i] = i; | |
569 | } | |
570 | ||
571 | for (i = 0; i < ncores; i++) | |
572 | set_cpu_possible(i, true); | |
573 | ||
574 | kick_register_func(&ipi_irq); | |
575 | } |