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830980a0 MS |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version | |
5 | * 2 of the License, or (at your option) any later version. | |
6 | * | |
7 | * Based on powerpc version | |
8 | */ | |
9 | ||
10 | #ifndef __ASM_MICROBLAZE_PCI_H | |
11 | #define __ASM_MICROBLAZE_PCI_H | |
12 | #ifdef __KERNEL__ | |
13 | ||
14 | #include <linux/types.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/pci.h> | |
19 | ||
20 | #include <asm/scatterlist.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/pci-bridge.h> | |
24 | ||
c74c8b1d JL |
25 | #include <asm-generic/pci-dma-compat.h> |
26 | ||
830980a0 MS |
27 | #define PCIBIOS_MIN_IO 0x1000 |
28 | #define PCIBIOS_MIN_MEM 0x10000000 | |
29 | ||
30 | struct pci_dev; | |
31 | ||
32 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ | |
33 | #define IOBASE_BRIDGE_NUMBER 0 | |
34 | #define IOBASE_MEMORY 1 | |
35 | #define IOBASE_IO 2 | |
36 | #define IOBASE_ISA_IO 3 | |
37 | #define IOBASE_ISA_MEM 4 | |
38 | ||
39 | #define pcibios_scan_all_fns(a, b) 0 | |
40 | ||
41 | /* | |
42 | * Set this to 1 if you want the kernel to re-assign all PCI | |
43 | * bus numbers (don't do that on ppc64 yet !) | |
44 | */ | |
72bdee79 | 45 | #define pcibios_assign_all_busses() 0 |
830980a0 | 46 | |
830980a0 MS |
47 | #ifdef CONFIG_PCI |
48 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | |
49 | enum pci_dma_burst_strategy *strat, | |
50 | unsigned long *strategy_parameter) | |
51 | { | |
52 | *strat = PCI_DMA_BURST_INFINITY; | |
53 | *strategy_parameter = ~0UL; | |
54 | } | |
55 | #endif | |
56 | ||
57 | extern int pci_domain_nr(struct pci_bus *bus); | |
58 | ||
59 | /* Decide whether to display the domain number in /proc */ | |
60 | extern int pci_proc_domain(struct pci_bus *bus); | |
61 | ||
62 | struct vm_area_struct; | |
63 | /* Map a range of PCI memory or I/O space for a device into user space */ | |
64 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | |
65 | enum pci_mmap_state mmap_state, int write_combine); | |
66 | ||
67 | /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ | |
68 | #define HAVE_PCI_MMAP 1 | |
69 | ||
70 | extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, | |
71 | size_t count); | |
72 | extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, | |
73 | size_t count); | |
74 | extern int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
75 | struct vm_area_struct *vma, | |
76 | enum pci_mmap_state mmap_state); | |
77 | ||
78 | #define HAVE_PCI_LEGACY 1 | |
79 | ||
830980a0 MS |
80 | /* The PCI address space does equal the physical memory |
81 | * address space (no IOMMU). The IDE and SCSI device layers use | |
82 | * this boolean for bounce buffer decisions. | |
83 | */ | |
84 | #define PCI_DMA_BUS_IS_PHYS (1) | |
85 | ||
830980a0 MS |
86 | static inline struct resource *pcibios_select_root(struct pci_dev *pdev, |
87 | struct resource *res) | |
88 | { | |
89 | struct resource *root = NULL; | |
90 | ||
91 | if (res->flags & IORESOURCE_IO) | |
92 | root = &ioport_resource; | |
93 | if (res->flags & IORESOURCE_MEM) | |
94 | root = &iomem_resource; | |
95 | ||
96 | return root; | |
97 | } | |
98 | ||
99 | extern void pcibios_claim_one_bus(struct pci_bus *b); | |
100 | ||
101 | extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); | |
102 | ||
103 | extern void pcibios_resource_survey(void); | |
104 | ||
105 | extern struct pci_controller *init_phb_dynamic(struct device_node *dn); | |
106 | extern int remove_phb_dynamic(struct pci_controller *phb); | |
107 | ||
108 | extern struct pci_dev *of_create_pci_dev(struct device_node *node, | |
109 | struct pci_bus *bus, int devfn); | |
110 | ||
111 | extern void of_scan_pci_bridge(struct device_node *node, | |
112 | struct pci_dev *dev); | |
113 | ||
114 | extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); | |
115 | extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); | |
116 | ||
830980a0 MS |
117 | extern int pci_bus_find_capability(struct pci_bus *bus, |
118 | unsigned int devfn, int cap); | |
119 | ||
120 | struct file; | |
121 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | |
122 | unsigned long pfn, | |
123 | unsigned long size, | |
124 | pgprot_t prot); | |
125 | ||
126 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER | |
127 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
128 | const struct resource *rsrc, | |
129 | resource_size_t *start, resource_size_t *end); | |
130 | ||
131 | extern void pcibios_setup_bus_devices(struct pci_bus *bus); | |
132 | extern void pcibios_setup_bus_self(struct pci_bus *bus); | |
133 | ||
25985edc | 134 | /* This part of code was originally in xilinx-pci.h */ |
733cc218 MS |
135 | #ifdef CONFIG_PCI_XILINX |
136 | extern void __init xilinx_pci_init(void); | |
137 | #else | |
138 | static inline void __init xilinx_pci_init(void) { return; } | |
139 | #endif | |
140 | ||
830980a0 MS |
141 | #endif /* __KERNEL__ */ |
142 | #endif /* __ASM_MICROBLAZE_PCI_H */ |