[deliverable/linux.git] / arch / microblaze / kernel / entry-nommu.S

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <linux/errno.h>
#include <asm/entry.h>
#include <asm/asm-offsets.h>
#include <asm/registers.h>
#include <asm/unistd.h>
#include <asm/percpu.h>
#include <asm/signal.h>

#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
	.macro	disable_irq
	msrclr r0, MSR_IE
	.endm

	.macro	enable_irq
	msrset r0, MSR_IE
	.endm

	.macro	clear_bip
	msrclr r0, MSR_BIP
	.endm
#else
	.macro	disable_irq
	mfs r11, rmsr
	andi r11, r11, ~MSR_IE
	mts rmsr, r11
	.endm

	.macro	enable_irq
	mfs r11, rmsr
	ori r11, r11, MSR_IE
	mts rmsr, r11
	.endm

	.macro	clear_bip
	mfs r11, rmsr
	andi r11, r11, ~MSR_BIP
	mts rmsr, r11
	.endm
#endif

ENTRY(_interrupt)
	swi	r1, r0, PER_CPU(ENTRY_SP)	/* save the current sp */
	swi	r11, r0, PER_CPU(R11_SAVE)	/* temporarily save r11 */
	lwi	r11, r0, PER_CPU(KM)		/* load mode indicator */
	beqid	r11, 1f
	nop
	brid	2f				/* jump over */
	addik	r1, r1, (-PT_SIZE)	/* room for pt_regs (delay slot) */
1:						/* switch to kernel stack */
	lwi	r1, r0, PER_CPU(CURRENT_SAVE)	/* get the saved current */
	lwi	r1, r1, TS_THREAD_INFO		/* get the thread info */
	/* calculate kernel stack pointer */
	addik	r1, r1, THREAD_SIZE - PT_SIZE
2:
	swi	r11, r1, PT_MODE		/* store the mode */
	lwi	r11, r0, PER_CPU(R11_SAVE)	/* reload r11 */
	swi	r2, r1, PT_R2
	swi	r3, r1, PT_R3
	swi	r4, r1, PT_R4
	swi	r5, r1, PT_R5
	swi	r6, r1, PT_R6
	swi	r7, r1, PT_R7
	swi	r8, r1, PT_R8
	swi	r9, r1, PT_R9
	swi	r10, r1, PT_R10
	swi	r11, r1, PT_R11
	swi	r12, r1, PT_R12
	swi	r13, r1, PT_R13
	swi	r14, r1, PT_R14
	swi	r14, r1, PT_PC
	swi	r15, r1, PT_R15
	swi	r16, r1, PT_R16
	swi	r17, r1, PT_R17
	swi	r18, r1, PT_R18
	swi	r19, r1, PT_R19
	swi	r20, r1, PT_R20
	swi	r21, r1, PT_R21
	swi	r22, r1, PT_R22
	swi	r23, r1, PT_R23
	swi	r24, r1, PT_R24
	swi	r25, r1, PT_R25
	swi	r26, r1, PT_R26
	swi	r27, r1, PT_R27
	swi	r28, r1, PT_R28
	swi	r29, r1, PT_R29
	swi	r30, r1, PT_R30
	swi	r31, r1, PT_R31
	/* special purpose registers */
	mfs	r11, rmsr
	swi	r11, r1, PT_MSR
	mfs	r11, rear
	swi	r11, r1, PT_EAR
	mfs	r11, resr
	swi	r11, r1, PT_ESR
	mfs	r11, rfsr
	swi	r11, r1, PT_FSR
	/* reload original stack pointer and save it */
	lwi	r11, r0, PER_CPU(ENTRY_SP)
	swi	r11, r1, PT_R1
	/* update mode indicator we are in kernel mode */
	addik	r11, r0, 1
	swi	r11, r0, PER_CPU(KM)
	/* restore r31 */
	lwi	r31, r0, PER_CPU(CURRENT_SAVE)
	/* prepare the link register, the argument and jump */
	addik	r15, r0, ret_from_intr - 8
	addk	r6, r0, r15
	braid	do_IRQ
	add	r5, r0, r1

ret_from_intr:
	lwi	r11, r1, PT_MODE
	bneid	r11, no_intr_resched

	lwi	r6, r31, TS_THREAD_INFO	/* get thread info */
	lwi	r19, r6, TI_FLAGS	/* get flags in thread info */
				/* do an extra work if any bits are set */

	andi	r11, r19, _TIF_NEED_RESCHED
	beqi	r11, 1f
	bralid	r15, schedule
	nop
1:	andi	r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
	beqid	r11, no_intr_resched
	addk	r5, r1, r0
	bralid	r15, do_notify_resume
	addk	r6, r0, r0

no_intr_resched:
	/* Disable interrupts, we are now committed to the state restore */
	disable_irq

	/* save mode indicator */
	lwi	r11, r1, PT_MODE
	swi	r11, r0, PER_CPU(KM)

	/* save r31 */
	swi	r31, r0, PER_CPU(CURRENT_SAVE)
restore_context:
	/* special purpose registers */
	lwi	r11, r1, PT_FSR
	mts	rfsr, r11
	lwi	r11, r1, PT_ESR
	mts	resr, r11
	lwi	r11, r1, PT_EAR
	mts	rear, r11
	lwi	r11, r1, PT_MSR
	mts	rmsr, r11

	lwi	r31, r1, PT_R31
	lwi	r30, r1, PT_R30
	lwi	r29, r1, PT_R29
	lwi	r28, r1, PT_R28
	lwi	r27, r1, PT_R27
	lwi	r26, r1, PT_R26
	lwi	r25, r1, PT_R25
	lwi	r24, r1, PT_R24
	lwi	r23, r1, PT_R23
	lwi	r22, r1, PT_R22
	lwi	r21, r1, PT_R21
	lwi	r20, r1, PT_R20
	lwi	r19, r1, PT_R19
	lwi	r18, r1, PT_R18
	lwi	r17, r1, PT_R17
	lwi	r16, r1, PT_R16
	lwi	r15, r1, PT_R15
	lwi	r14, r1, PT_PC
	lwi	r13, r1, PT_R13
	lwi	r12, r1, PT_R12
	lwi	r11, r1, PT_R11
	lwi	r10, r1, PT_R10
	lwi	r9, r1, PT_R9
	lwi	r8, r1, PT_R8
	lwi	r7, r1, PT_R7
	lwi	r6, r1, PT_R6
	lwi	r5, r1, PT_R5
	lwi	r4, r1, PT_R4
	lwi	r3, r1, PT_R3
	lwi	r2, r1, PT_R2
	lwi	r1, r1, PT_R1
	rtid	r14, 0
	nop

ENTRY(_reset)
	brai	0;

ENTRY(_user_exception)
	swi	r1, r0, PER_CPU(ENTRY_SP)	/* save the current sp */
	swi	r11, r0, PER_CPU(R11_SAVE)	/* temporarily save r11 */
	lwi	r11, r0, PER_CPU(KM)		/* load mode indicator */
	beqid	r11, 1f				/* Already in kernel mode? */
	nop
	brid	2f				/* jump over */
	addik	r1, r1, (-PT_SIZE)	/* Room for pt_regs (delay slot) */
1:						/* Switch to kernel stack */
	lwi	r1, r0, PER_CPU(CURRENT_SAVE)	/* get the saved current */
	lwi	r1, r1, TS_THREAD_INFO		/* get the thread info */
	/* calculate kernel stack pointer */
	addik	r1, r1, THREAD_SIZE - PT_SIZE
2:
	swi	r11, r1, PT_MODE		/* store the mode */
	lwi	r11, r0, PER_CPU(R11_SAVE)	/* reload r11 */
	/* save them on stack */
	swi	r2, r1, PT_R2
	swi	r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
	swi	r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
	swi	r5, r1, PT_R5
	swi	r6, r1, PT_R6
	swi	r7, r1, PT_R7
	swi	r8, r1, PT_R8
	swi	r9, r1, PT_R9
	swi	r10, r1, PT_R10
	swi	r11, r1, PT_R11
	/* r12: _always_ in clobber list; see unistd.h */
	swi	r12, r1, PT_R12
	swi	r13, r1, PT_R13
	/* r14: _always_ in clobber list; see unistd.h */
	swi	r14, r1, PT_R14
	/* but we want to return to the next inst. */
	addik	r14, r14, 0x4
	swi	r14, r1, PT_PC		/* increment by 4 and store in pc */
	swi	r15, r1, PT_R15
	swi	r16, r1, PT_R16
	swi	r17, r1, PT_R17
	swi	r18, r1, PT_R18
	swi	r19, r1, PT_R19
	swi	r20, r1, PT_R20
	swi	r21, r1, PT_R21
	swi	r22, r1, PT_R22
	swi	r23, r1, PT_R23
	swi	r24, r1, PT_R24
	swi	r25, r1, PT_R25
	swi	r26, r1, PT_R26
	swi	r27, r1, PT_R27
	swi	r28, r1, PT_R28
	swi	r29, r1, PT_R29
	swi	r30, r1, PT_R30
	swi	r31, r1, PT_R31

	disable_irq
	nop		/* make sure IE bit is in effect */
	clear_bip	/* once IE is in effect it is safe to clear BIP */
	nop

	/* special purpose registers */
	mfs	r11, rmsr
	swi	r11, r1, PT_MSR
	mfs	r11, rear
	swi	r11, r1, PT_EAR
	mfs	r11, resr
	swi	r11, r1, PT_ESR
	mfs	r11, rfsr
	swi	r11, r1, PT_FSR
	/* reload original stack pointer and save it */
	lwi	r11, r0, PER_CPU(ENTRY_SP)
	swi	r11, r1, PT_R1
	/* update mode indicator we are in kernel mode */
	addik	r11, r0, 1
	swi	r11, r0, PER_CPU(KM)
	/* restore r31 */
	lwi	r31, r0, PER_CPU(CURRENT_SAVE)
	/* re-enable interrupts now we are in kernel mode */
	enable_irq

	/* See if the system call number is valid. */
	addi	r11, r12, -__NR_syscalls
	bgei	r11, 1f			/* return to user if not valid */
	/* Figure out which function to use for this system call. */
	/* Note Microblaze barrel shift is optional, so don't rely on it */
	add	r12, r12, r12			/* convert num -> ptr */
	add	r12, r12, r12
	lwi	r12, r12, sys_call_table	/* Get function pointer */
	addik	r15, r0, ret_to_user-8		/* set return address */
	bra	r12				/* Make the system call. */
	bri	0				/* won't reach here */
1:
	brid	ret_to_user			/* jump to syscall epilogue */
	addi	r3, r0, -ENOSYS			/* set errno in delay slot */

/*
 * Debug traps are like a system call, but entered via brki r14, 0x60
 * All we need to do is send the SIGTRAP signal to current, ptrace and
 * do_notify_resume will handle the rest
 */
ENTRY(_debug_exception)
	swi	r1, r0, PER_CPU(ENTRY_SP)	/* save the current sp */
	lwi	r1, r0, PER_CPU(CURRENT_SAVE)	/* get the saved current */
	lwi	r1, r1, TS_THREAD_INFO		/* get the thread info */
	addik	r1, r1, THREAD_SIZE - PT_SIZE	/* get the kernel stack */
	swi	r11, r0, PER_CPU(R11_SAVE)	/* temporarily save r11 */
	lwi	r11, r0, PER_CPU(KM)		/* load mode indicator */
//save_context:
	swi	r11, r1, PT_MODE	/* store the mode */
	lwi	r11, r0, PER_CPU(R11_SAVE)	/* reload r11 */
	/* save them on stack */
	swi	r2, r1, PT_R2
	swi	r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
	swi	r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
	swi	r5, r1, PT_R5
	swi	r6, r1, PT_R6
	swi	r7, r1, PT_R7
	swi	r8, r1, PT_R8
	swi	r9, r1, PT_R9
	swi	r10, r1, PT_R10
	swi	r11, r1, PT_R11
	/* r12: _always_ in clobber list; see unistd.h */
	swi	r12, r1, PT_R12
	swi	r13, r1, PT_R13
	/* r14: _always_ in clobber list; see unistd.h */
	swi	r14, r1, PT_R14
	swi	r14, r1, PT_PC /* Will return to interrupted instruction */
	swi	r15, r1, PT_R15
	swi	r16, r1, PT_R16
	swi	r17, r1, PT_R17
	swi	r18, r1, PT_R18
	swi	r19, r1, PT_R19
	swi	r20, r1, PT_R20
	swi	r21, r1, PT_R21
	swi	r22, r1, PT_R22
	swi	r23, r1, PT_R23
	swi	r24, r1, PT_R24
	swi	r25, r1, PT_R25
	swi	r26, r1, PT_R26
	swi	r27, r1, PT_R27
	swi	r28, r1, PT_R28
	swi	r29, r1, PT_R29
	swi	r30, r1, PT_R30
	swi	r31, r1, PT_R31

	disable_irq
	nop		/* make sure IE bit is in effect */
	clear_bip	/* once IE is in effect it is safe to clear BIP */
	nop

	/* special purpose registers */
	mfs	r11, rmsr
	swi	r11, r1, PT_MSR
	mfs	r11, rear
	swi	r11, r1, PT_EAR
	mfs	r11, resr
	swi	r11, r1, PT_ESR
	mfs	r11, rfsr
	swi	r11, r1, PT_FSR
	/* reload original stack pointer and save it */
	lwi	r11, r0, PER_CPU(ENTRY_SP)
	swi	r11, r1, PT_R1
	/* update mode indicator we are in kernel mode */
	addik	r11, r0, 1
	swi	r11, r0, PER_CPU(KM)
	/* restore r31 */
	lwi	r31, r0, PER_CPU(CURRENT_SAVE)
	/* re-enable interrupts now we are in kernel mode */
	enable_irq

	addi	r5, r0, SIGTRAP			/* sending the trap signal */
	add	r6, r0, r31			/* to current */
	bralid	r15, send_sig
	add	r7, r0, r0			/* 3rd param zero */

	/* Restore r3/r4 to work around how ret_to_user works */
	lwi	r3, r1, PT_R3
	lwi	r4, r1, PT_R4
	bri	ret_to_user

ENTRY(_break)
	bri	0

/* struct task_struct *_switch_to(struct thread_info *prev,
					struct thread_info *next); */
ENTRY(_switch_to)
	/* prepare return value */
	addk	r3, r0, r31

	/* save registers in cpu_context */
	/* use r11 and r12, volatile registers, as temp register */
	addik	r11, r5, TI_CPU_CONTEXT
	swi	r1, r11, CC_R1
	swi	r2, r11, CC_R2
	/* skip volatile registers.
	 * they are saved on stack when we jumped to _switch_to() */
	/* dedicated registers */
	swi	r13, r11, CC_R13
	swi	r14, r11, CC_R14
	swi	r15, r11, CC_R15
	swi	r16, r11, CC_R16
	swi	r17, r11, CC_R17
	swi	r18, r11, CC_R18
	/* save non-volatile registers */
	swi	r19, r11, CC_R19
	swi	r20, r11, CC_R20
	swi	r21, r11, CC_R21
	swi	r22, r11, CC_R22
	swi	r23, r11, CC_R23
	swi	r24, r11, CC_R24
	swi	r25, r11, CC_R25
	swi	r26, r11, CC_R26
	swi	r27, r11, CC_R27
	swi	r28, r11, CC_R28
	swi	r29, r11, CC_R29
	swi	r30, r11, CC_R30
	/* special purpose registers */
	mfs	r12, rmsr
	swi	r12, r11, CC_MSR
	mfs	r12, rear
	swi	r12, r11, CC_EAR
	mfs	r12, resr
	swi	r12, r11, CC_ESR
	mfs	r12, rfsr
	swi	r12, r11, CC_FSR

	/* update r31, the current */
	lwi	r31, r6, TI_TASK
	swi	r31, r0, PER_CPU(CURRENT_SAVE)

	/* get new process' cpu context and restore */
	addik	r11, r6, TI_CPU_CONTEXT

	/* special purpose registers */
	lwi	r12, r11, CC_FSR
	mts	rfsr, r12
	lwi	r12, r11, CC_ESR
	mts	resr, r12
	lwi	r12, r11, CC_EAR
	mts	rear, r12
	lwi	r12, r11, CC_MSR
	mts	rmsr, r12
	/* non-volatile registers */
	lwi	r30, r11, CC_R30
	lwi	r29, r11, CC_R29
	lwi	r28, r11, CC_R28
	lwi	r27, r11, CC_R27
	lwi	r26, r11, CC_R26
	lwi	r25, r11, CC_R25
	lwi	r24, r11, CC_R24
	lwi	r23, r11, CC_R23
	lwi	r22, r11, CC_R22
	lwi	r21, r11, CC_R21
	lwi	r20, r11, CC_R20
	lwi	r19, r11, CC_R19
	/* dedicated registers */
	lwi	r18, r11, CC_R18
	lwi	r17, r11, CC_R17
	lwi	r16, r11, CC_R16
	lwi	r15, r11, CC_R15
	lwi	r14, r11, CC_R14
	lwi	r13, r11, CC_R13
	/* skip volatile registers */
	lwi	r2, r11, CC_R2
	lwi	r1, r11, CC_R1

	rtsd	r15, 8
	nop

ENTRY(ret_from_fork)
	addk	r5, r0, r3
	addk	r6, r0, r1
	brlid	r15, schedule_tail
	nop
	swi	r31, r1, PT_R31		/* save r31 in user context. */
			/* will soon be restored to r31 in ret_to_user */
	addk	r3, r0, r0
	brid	ret_to_user
	nop

ENTRY(ret_from_kernel_thread)
	brlid	r15, schedule_tail
	addk	r5, r0, r3
	brald	r15, r20
	addk	r5, r0, r19
	brid	ret_to_user
	addk	r3, r0, r0

work_pending:
	enable_irq

	andi	r11, r19, _TIF_NEED_RESCHED
	beqi	r11, 1f
	bralid	r15, schedule
	nop
1:	andi	r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
	beqi	r11, no_work_pending
	addk	r5, r1, r0
	bralid	r15, do_notify_resume
	addik	r6, r0, 1
	bri	no_work_pending

ENTRY(ret_to_user)
	disable_irq

	swi	r4, r1, PT_R4		/* return val */
	swi	r3, r1, PT_R3		/* return val */

	lwi	r6, r31, TS_THREAD_INFO /* get thread info */
	lwi	r19, r6, TI_FLAGS /* get flags in thread info */
	bnei	r19, work_pending /* do an extra work if any bits are set */
no_work_pending:
	disable_irq

	/* save r31 */
	swi	r31, r0, PER_CPU(CURRENT_SAVE)
	/* save mode indicator */
	lwi	r18, r1, PT_MODE
	swi	r18, r0, PER_CPU(KM)
//restore_context:
	/* special purpose registers */
	lwi	r18, r1, PT_FSR
	mts	rfsr, r18
	lwi	r18, r1, PT_ESR
	mts	resr, r18
	lwi	r18, r1, PT_EAR
	mts	rear, r18
	lwi	r18, r1, PT_MSR
	mts	rmsr, r18

	lwi	r31, r1, PT_R31
	lwi	r30, r1, PT_R30
	lwi	r29, r1, PT_R29
	lwi	r28, r1, PT_R28
	lwi	r27, r1, PT_R27
	lwi	r26, r1, PT_R26
	lwi	r25, r1, PT_R25
	lwi	r24, r1, PT_R24
	lwi	r23, r1, PT_R23
	lwi	r22, r1, PT_R22
	lwi	r21, r1, PT_R21
	lwi	r20, r1, PT_R20
	lwi	r19, r1, PT_R19
	lwi	r18, r1, PT_R18
	lwi	r17, r1, PT_R17
	lwi	r16, r1, PT_R16
	lwi	r15, r1, PT_R15
	lwi	r14, r1, PT_PC
	lwi	r13, r1, PT_R13
	lwi	r12, r1, PT_R12
	lwi	r11, r1, PT_R11
	lwi	r10, r1, PT_R10
	lwi	r9, r1, PT_R9
	lwi	r8, r1, PT_R8
	lwi	r7, r1, PT_R7
	lwi	r6, r1, PT_R6
	lwi	r5, r1, PT_R5
	lwi	r4, r1, PT_R4		/* return val */
	lwi	r3, r1, PT_R3		/* return val */
	lwi	r2, r1, PT_R2
	lwi	r1, r1, PT_R1

	rtid	r14, 0
	nop

sys_rt_sigreturn_wrapper:
	brid	sys_rt_sigreturn
	addk	r5, r1, r0

	/* Interrupt vector table */
	.section	.init.ivt, "ax"
	.org 0x0
	brai	_reset
	brai	_user_exception
	brai	_interrupt
	brai	_break
	brai	_hw_exception_handler
	.org 0x60
	brai	_debug_exception

.section .rodata,"a"
#include "syscall_table.S"

syscall_table_size=(.-sys_call_table)

type_SYSCALL:
	.ascii "SYSCALL\0"
type_IRQ:
	.ascii "IRQ\0"
type_IRQ_PREEMPT:
	.ascii "IRQ (PREEMPTED)\0"
type_SYSCALL_PREEMPT:
	.ascii " SYSCALL (PREEMPTED)\0"

	/*
	 * Trap decoding for stack unwinder
	 * Tuples are (start addr, end addr, string)
	 * If return address lies on [start addr, end addr],
	 * unwinder displays 'string'
	 */

	.align 4
.global microblaze_trap_handlers
microblaze_trap_handlers:
	/* Exact matches come first */
	.word ret_to_user  ; .word ret_to_user    ; .word type_SYSCALL
	.word ret_from_intr; .word ret_from_intr  ; .word type_IRQ
	/* Fuzzy matches go here */
	.word ret_from_intr; .word no_intr_resched; .word type_IRQ_PREEMPT
	.word work_pending ; .word no_work_pending; .word type_SYSCALL_PREEMPT
	/* End of table */
	.word 0             ; .word 0               ; .word 0
Commit	Line	Data
6d5af1a3 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/linkage.h>
	12	#include <asm/thread_info.h>
65504a47	13	#include <linux/errno.h>
6d5af1a3 MS	14	#include <asm/entry.h>
	15	#include <asm/asm-offsets.h>
	16	#include <asm/registers.h>
	17	#include <asm/unistd.h>
	18	#include <asm/percpu.h>
	19	#include <asm/signal.h>
	20
	21	#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
	22	.macro disable_irq
	23	msrclr r0, MSR_IE
	24	.endm
	25
	26	.macro enable_irq
	27	msrset r0, MSR_IE
	28	.endm
	29
	30	.macro clear_bip
	31	msrclr r0, MSR_BIP
	32	.endm
	33	#else
	34	.macro disable_irq
	35	mfs r11, rmsr
	36	andi r11, r11, ~MSR_IE
	37	mts rmsr, r11
	38	.endm
	39
	40	.macro enable_irq
	41	mfs r11, rmsr
	42	ori r11, r11, MSR_IE
	43	mts rmsr, r11
	44	.endm
	45
	46	.macro clear_bip
	47	mfs r11, rmsr
	48	andi r11, r11, ~MSR_BIP
	49	mts rmsr, r11
	50	.endm
	51	#endif
	52
	53	ENTRY(_interrupt)
	54	swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
	55	swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
	56	lwi r11, r0, PER_CPU(KM) /* load mode indicator */
	57	beqid r11, 1f
	58	nop
	59	brid 2f /* jump over */
	60	addik r1, r1, (-PT_SIZE) /* room for pt_regs (delay slot) */
	61	1: /* switch to kernel stack */
	62	lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
	63	lwi r1, r1, TS_THREAD_INFO /* get the thread info */
	64	/* calculate kernel stack pointer */
	65	addik r1, r1, THREAD_SIZE - PT_SIZE
	66	2:
	67	swi r11, r1, PT_MODE /* store the mode */
	68	lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
	69	swi r2, r1, PT_R2
	70	swi r3, r1, PT_R3
	71	swi r4, r1, PT_R4
	72	swi r5, r1, PT_R5
	73	swi r6, r1, PT_R6
	74	swi r7, r1, PT_R7
	75	swi r8, r1, PT_R8
	76	swi r9, r1, PT_R9
	77	swi r10, r1, PT_R10
78	swi r11, r1, PT_R11
79	swi r12, r1, PT_R12
80	swi r13, r1, PT_R13
81	swi r14, r1, PT_R14
82	swi r14, r1, PT_PC
83	swi r15, r1, PT_R15
84	swi r16, r1, PT_R16
85	swi r17, r1, PT_R17
86	swi r18, r1, PT_R18
87	swi r19, r1, PT_R19
88	swi r20, r1, PT_R20
89	swi r21, r1, PT_R21
90	swi r22, r1, PT_R22
91	swi r23, r1, PT_R23
92	swi r24, r1, PT_R24
93	swi r25, r1, PT_R25
94	swi r26, r1, PT_R26
95	swi r27, r1, PT_R27
96	swi r28, r1, PT_R28
97	swi r29, r1, PT_R29
98	swi r30, r1, PT_R30
99	swi r31, r1, PT_R31
100	/* special purpose registers */
101	mfs r11, rmsr
102	swi r11, r1, PT_MSR
103	mfs r11, rear
104	swi r11, r1, PT_EAR
105	mfs r11, resr
106	swi r11, r1, PT_ESR
107	mfs r11, rfsr
108	swi r11, r1, PT_FSR
109	/* reload original stack pointer and save it */
110	lwi r11, r0, PER_CPU(ENTRY_SP)
111	swi r11, r1, PT_R1
112	/* update mode indicator we are in kernel mode */
113	addik r11, r0, 1
114	swi r11, r0, PER_CPU(KM)
115	/* restore r31 */
116	lwi r31, r0, PER_CPU(CURRENT_SAVE)
117	/* prepare the link register, the argument and jump */
cd341577	118	addik r15, r0, ret_from_intr - 8
6d5af1a3 MS	119	addk r6, r0, r15
	120	braid do_IRQ
	121	add r5, r0, r1
	122
	123	ret_from_intr:
	124	lwi r11, r1, PT_MODE
58424a49	125	bneid r11, no_intr_resched
6d5af1a3 MS	126
	127	lwi r6, r31, TS_THREAD_INFO /* get thread info */
	128	lwi r19, r6, TI_FLAGS /* get flags in thread info */
	129	/* do an extra work if any bits are set */
	130
	131	andi r11, r19, _TIF_NEED_RESCHED
	132	beqi r11, 1f
	133	bralid r15, schedule
	134	nop
969a9616	135	1: andi r11, r19, _TIF_SIGPENDING \| _TIF_NOTIFY_RESUME
58424a49	136	beqid r11, no_intr_resched
6d5af1a3	137	addk r5, r1, r0
969a9616	138	bralid r15, do_notify_resume
6d5af1a3 MS	139	addk r6, r0, r0
6d5af1a3 MS	140
58424a49 SM	141	no_intr_resched:
	142	/* Disable interrupts, we are now committed to the state restore */
	143	disable_irq
	144
6d5af1a3 MS	145	/* save mode indicator */
6d5af1a3 MS	146	lwi r11, r1, PT_MODE
6d5af1a3 MS	147	swi r11, r0, PER_CPU(KM)
	148
	149	/* save r31 */
	150	swi r31, r0, PER_CPU(CURRENT_SAVE)
	151	restore_context:
	152	/* special purpose registers */
	153	lwi r11, r1, PT_FSR
	154	mts rfsr, r11
	155	lwi r11, r1, PT_ESR
	156	mts resr, r11
	157	lwi r11, r1, PT_EAR
	158	mts rear, r11
	159	lwi r11, r1, PT_MSR
	160	mts rmsr, r11
	161
	162	lwi r31, r1, PT_R31
	163	lwi r30, r1, PT_R30
	164	lwi r29, r1, PT_R29
	165	lwi r28, r1, PT_R28
	166	lwi r27, r1, PT_R27
	167	lwi r26, r1, PT_R26
	168	lwi r25, r1, PT_R25
	169	lwi r24, r1, PT_R24
	170	lwi r23, r1, PT_R23
	171	lwi r22, r1, PT_R22
	172	lwi r21, r1, PT_R21
	173	lwi r20, r1, PT_R20
	174	lwi r19, r1, PT_R19
	175	lwi r18, r1, PT_R18
	176	lwi r17, r1, PT_R17
	177	lwi r16, r1, PT_R16
	178	lwi r15, r1, PT_R15
	179	lwi r14, r1, PT_PC
	180	lwi r13, r1, PT_R13
	181	lwi r12, r1, PT_R12
	182	lwi r11, r1, PT_R11
	183	lwi r10, r1, PT_R10
	184	lwi r9, r1, PT_R9
	185	lwi r8, r1, PT_R8
	186	lwi r7, r1, PT_R7
	187	lwi r6, r1, PT_R6
	188	lwi r5, r1, PT_R5
	189	lwi r4, r1, PT_R4
	190	lwi r3, r1, PT_R3
	191	lwi r2, r1, PT_R2
	192	lwi r1, r1, PT_R1
	193	rtid r14, 0
	194	nop
	195
	196	ENTRY(_reset)
	197	brai 0;
	198
	199	ENTRY(_user_exception)
	200	swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
	201	swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
	202	lwi r11, r0, PER_CPU(KM) /* load mode indicator */
	203	beqid r11, 1f /* Already in kernel mode? */
	204	nop
	205	brid 2f /* jump over */
	206	addik r1, r1, (-PT_SIZE) /* Room for pt_regs (delay slot) */
	207	1: /* Switch to kernel stack */
	208	lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
	209	lwi r1, r1, TS_THREAD_INFO /* get the thread info */
	210	/* calculate kernel stack pointer */
211	addik r1, r1, THREAD_SIZE - PT_SIZE
6d5af1a3 MS	212	2:
	213	swi r11, r1, PT_MODE /* store the mode */
	214	lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
	215	/* save them on stack */
	216	swi r2, r1, PT_R2
	217	swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
	218	swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
	219	swi r5, r1, PT_R5
	220	swi r6, r1, PT_R6
	221	swi r7, r1, PT_R7
	222	swi r8, r1, PT_R8
	223	swi r9, r1, PT_R9
	224	swi r10, r1, PT_R10
	225	swi r11, r1, PT_R11
	226	/* r12: _always_ in clobber list; see unistd.h */
	227	swi r12, r1, PT_R12
	228	swi r13, r1, PT_R13
	229	/* r14: _always_ in clobber list; see unistd.h */
	230	swi r14, r1, PT_R14
	231	/* but we want to return to the next inst. */
	232	addik r14, r14, 0x4
	233	swi r14, r1, PT_PC /* increment by 4 and store in pc */
	234	swi r15, r1, PT_R15
	235	swi r16, r1, PT_R16
	236	swi r17, r1, PT_R17
	237	swi r18, r1, PT_R18
	238	swi r19, r1, PT_R19
	239	swi r20, r1, PT_R20
	240	swi r21, r1, PT_R21
	241	swi r22, r1, PT_R22
	242	swi r23, r1, PT_R23
	243	swi r24, r1, PT_R24
	244	swi r25, r1, PT_R25
	245	swi r26, r1, PT_R26
	246	swi r27, r1, PT_R27
	247	swi r28, r1, PT_R28
	248	swi r29, r1, PT_R29
	249	swi r30, r1, PT_R30
	250	swi r31, r1, PT_R31
	251
	252	disable_irq
	253	nop /* make sure IE bit is in effect */
	254	clear_bip /* once IE is in effect it is safe to clear BIP */
	255	nop
	256
	257	/* special purpose registers */
	258	mfs r11, rmsr
	259	swi r11, r1, PT_MSR
	260	mfs r11, rear
	261	swi r11, r1, PT_EAR
	262	mfs r11, resr
	263	swi r11, r1, PT_ESR
	264	mfs r11, rfsr
	265	swi r11, r1, PT_FSR
	266	/* reload original stack pointer and save it */
	267	lwi r11, r0, PER_CPU(ENTRY_SP)
	268	swi r11, r1, PT_R1
	269	/* update mode indicator we are in kernel mode */
	270	addik r11, r0, 1
	271	swi r11, r0, PER_CPU(KM)
	272	/* restore r31 */
	273	lwi r31, r0, PER_CPU(CURRENT_SAVE)
	274	/* re-enable interrupts now we are in kernel mode */
	275	enable_irq
276
277	/* See if the system call number is valid. */
278	addi r11, r12, -__NR_syscalls
279	bgei r11, 1f /* return to user if not valid */
280	/* Figure out which function to use for this system call. */
281	/* Note Microblaze barrel shift is optional, so don't rely on it */
282	add r12, r12, r12 /* convert num -> ptr */
283	add r12, r12, r12
284	lwi r12, r12, sys_call_table /* Get function pointer */
cd341577	285	addik r15, r0, ret_to_user-8 /* set return address */
6d5af1a3 MS	286	bra r12 /* Make the system call. */
	287	bri 0 /* won't reach here */
	288	1:
	289	brid ret_to_user /* jump to syscall epilogue */
	290	addi r3, r0, -ENOSYS /* set errno in delay slot */
	291
	292	/*
	293	* Debug traps are like a system call, but entered via brki r14, 0x60
969a9616 AV	294	* All we need to do is send the SIGTRAP signal to current, ptrace and
969a9616 AV	295	* do_notify_resume will handle the rest
6d5af1a3 MS	296	*/
	297	ENTRY(_debug_exception)
	298	swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
	299	lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
	300	lwi r1, r1, TS_THREAD_INFO /* get the thread info */
	301	addik r1, r1, THREAD_SIZE - PT_SIZE /* get the kernel stack */
	302	swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
	303	lwi r11, r0, PER_CPU(KM) /* load mode indicator */
	304	//save_context:
	305	swi r11, r1, PT_MODE /* store the mode */
	306	lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
	307	/* save them on stack */
	308	swi r2, r1, PT_R2
	309	swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
	310	swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
	311	swi r5, r1, PT_R5
	312	swi r6, r1, PT_R6
	313	swi r7, r1, PT_R7
	314	swi r8, r1, PT_R8
	315	swi r9, r1, PT_R9
	316	swi r10, r1, PT_R10
	317	swi r11, r1, PT_R11
	318	/* r12: _always_ in clobber list; see unistd.h */
	319	swi r12, r1, PT_R12
	320	swi r13, r1, PT_R13
	321	/* r14: _always_ in clobber list; see unistd.h */
	322	swi r14, r1, PT_R14
	323	swi r14, r1, PT_PC /* Will return to interrupted instruction */
	324	swi r15, r1, PT_R15
	325	swi r16, r1, PT_R16
	326	swi r17, r1, PT_R17
	327	swi r18, r1, PT_R18
	328	swi r19, r1, PT_R19
	329	swi r20, r1, PT_R20
	330	swi r21, r1, PT_R21
	331	swi r22, r1, PT_R22
	332	swi r23, r1, PT_R23
	333	swi r24, r1, PT_R24
	334	swi r25, r1, PT_R25
	335	swi r26, r1, PT_R26
	336	swi r27, r1, PT_R27
	337	swi r28, r1, PT_R28
	338	swi r29, r1, PT_R29
	339	swi r30, r1, PT_R30
	340	swi r31, r1, PT_R31
	341
	342	disable_irq
	343	nop /* make sure IE bit is in effect */
	344	clear_bip /* once IE is in effect it is safe to clear BIP */
	345	nop
	346
	347	/* special purpose registers */
	348	mfs r11, rmsr
	349	swi r11, r1, PT_MSR
	350	mfs r11, rear
	351	swi r11, r1, PT_EAR
	352	mfs r11, resr
	353	swi r11, r1, PT_ESR
	354	mfs r11, rfsr
	355	swi r11, r1, PT_FSR
	356	/* reload original stack pointer and save it */
	357	lwi r11, r0, PER_CPU(ENTRY_SP)
	358	swi r11, r1, PT_R1
	359	/* update mode indicator we are in kernel mode */
360	addik r11, r0, 1
361	swi r11, r0, PER_CPU(KM)
362	/* restore r31 */
363	lwi r31, r0, PER_CPU(CURRENT_SAVE)
364	/* re-enable interrupts now we are in kernel mode */
365	enable_irq
366
367	addi r5, r0, SIGTRAP /* sending the trap signal */
368	add r6, r0, r31 /* to current */
369	bralid r15, send_sig
370	add r7, r0, r0 /* 3rd param zero */
371
372	/* Restore r3/r4 to work around how ret_to_user works */
373	lwi r3, r1, PT_R3
374	lwi r4, r1, PT_R4
375	bri ret_to_user
376
377	ENTRY(_break)
378	bri 0
379
380	/* struct task_struct _switch_to(struct thread_info prev,
381	struct thread_info next); /
382	ENTRY(_switch_to)
383	/* prepare return value */
384	addk r3, r0, r31
385
386	/* save registers in cpu_context */
387	/* use r11 and r12, volatile registers, as temp register */
388	addik r11, r5, TI_CPU_CONTEXT
389	swi r1, r11, CC_R1
390	swi r2, r11, CC_R2
391	/* skip volatile registers.
392	* they are saved on stack when we jumped to _switch_to() */
393	/* dedicated registers */
394	swi r13, r11, CC_R13
395	swi r14, r11, CC_R14
396	swi r15, r11, CC_R15
397	swi r16, r11, CC_R16
398	swi r17, r11, CC_R17
399	swi r18, r11, CC_R18
400	/* save non-volatile registers */
401	swi r19, r11, CC_R19
402	swi r20, r11, CC_R20
403	swi r21, r11, CC_R21
404	swi r22, r11, CC_R22
405	swi r23, r11, CC_R23
406	swi r24, r11, CC_R24
407	swi r25, r11, CC_R25
408	swi r26, r11, CC_R26
409	swi r27, r11, CC_R27
410	swi r28, r11, CC_R28
411	swi r29, r11, CC_R29
412	swi r30, r11, CC_R30
413	/* special purpose registers */
414	mfs r12, rmsr
415	swi r12, r11, CC_MSR
416	mfs r12, rear
417	swi r12, r11, CC_EAR
418	mfs r12, resr
419	swi r12, r11, CC_ESR
420	mfs r12, rfsr
421	swi r12, r11, CC_FSR
422
423	/* update r31, the current */
424	lwi r31, r6, TI_TASK
425	swi r31, r0, PER_CPU(CURRENT_SAVE)
426
427	/* get new process' cpu context and restore */
428	addik r11, r6, TI_CPU_CONTEXT
429
430	/* special purpose registers */
431	lwi r12, r11, CC_FSR
432	mts rfsr, r12
433	lwi r12, r11, CC_ESR
434	mts resr, r12
435	lwi r12, r11, CC_EAR
436	mts rear, r12
437	lwi r12, r11, CC_MSR
438	mts rmsr, r12
439	/* non-volatile registers */
440	lwi r30, r11, CC_R30
441	lwi r29, r11, CC_R29
442	lwi r28, r11, CC_R28
443	lwi r27, r11, CC_R27
444	lwi r26, r11, CC_R26
445	lwi r25, r11, CC_R25
446	lwi r24, r11, CC_R24
447	lwi r23, r11, CC_R23
448	lwi r22, r11, CC_R22
449	lwi r21, r11, CC_R21
450	lwi r20, r11, CC_R20
451	lwi r19, r11, CC_R19
452	/* dedicated registers */
453	lwi r18, r11, CC_R18
454	lwi r17, r11, CC_R17
455	lwi r16, r11, CC_R16
456	lwi r15, r11, CC_R15
457	lwi r14, r11, CC_R14
458	lwi r13, r11, CC_R13
459	/* skip volatile registers */
460	lwi r2, r11, CC_R2
461	lwi r1, r11, CC_R1
462
463	rtsd r15, 8
464	nop
465
466	ENTRY(ret_from_fork)
467	addk r5, r0, r3
468	addk r6, r0, r1
469	brlid r15, schedule_tail
470	nop
471	swi r31, r1, PT_R31 /* save r31 in user context. */
472	/* will soon be restored to r31 in ret_to_user */
473	addk r3, r0, r0
474	brid ret_to_user
475	nop
476
2319295d AV	477	ENTRY(ret_from_kernel_thread)
	478	brlid r15, schedule_tail
	479	addk r5, r0, r3
	480	brald r15, r20
	481	addk r5, r0, r19
99c59f60 AV	482	brid ret_to_user
99c59f60 AV	483	addk r3, r0, r0
2319295d	484
6d5af1a3	485	work_pending:
0d5961b7 SM	486	enable_irq
0d5961b7 SM	487
6d5af1a3 MS	488	andi r11, r19, _TIF_NEED_RESCHED
	489	beqi r11, 1f
	490	bralid r15, schedule
	491	nop
969a9616	492	1: andi r11, r19, _TIF_SIGPENDING \| _TIF_NOTIFY_RESUME
6d5af1a3 MS	493	beqi r11, no_work_pending
6d5af1a3 MS	494	addk r5, r1, r0
969a9616	495	bralid r15, do_notify_resume
83140191	496	addik r6, r0, 1
6d5af1a3 MS	497	bri no_work_pending
	498
	499	ENTRY(ret_to_user)
	500	disable_irq
	501
	502	swi r4, r1, PT_R4 /* return val */
	503	swi r3, r1, PT_R3 /* return val */
	504
	505	lwi r6, r31, TS_THREAD_INFO /* get thread info */
	506	lwi r19, r6, TI_FLAGS /* get flags in thread info */
	507	bnei r19, work_pending /* do an extra work if any bits are set */
	508	no_work_pending:
	509	disable_irq
	510
	511	/* save r31 */
	512	swi r31, r0, PER_CPU(CURRENT_SAVE)
	513	/* save mode indicator */
	514	lwi r18, r1, PT_MODE
	515	swi r18, r0, PER_CPU(KM)
	516	//restore_context:
	517	/* special purpose registers */
	518	lwi r18, r1, PT_FSR
	519	mts rfsr, r18
	520	lwi r18, r1, PT_ESR
	521	mts resr, r18
	522	lwi r18, r1, PT_EAR
	523	mts rear, r18
	524	lwi r18, r1, PT_MSR
	525	mts rmsr, r18
	526
	527	lwi r31, r1, PT_R31
	528	lwi r30, r1, PT_R30
	529	lwi r29, r1, PT_R29
	530	lwi r28, r1, PT_R28
	531	lwi r27, r1, PT_R27
	532	lwi r26, r1, PT_R26
	533	lwi r25, r1, PT_R25
	534	lwi r24, r1, PT_R24
	535	lwi r23, r1, PT_R23
	536	lwi r22, r1, PT_R22
	537	lwi r21, r1, PT_R21
	538	lwi r20, r1, PT_R20
	539	lwi r19, r1, PT_R19
	540	lwi r18, r1, PT_R18
	541	lwi r17, r1, PT_R17
	542	lwi r16, r1, PT_R16
	543	lwi r15, r1, PT_R15
	544	lwi r14, r1, PT_PC
	545	lwi r13, r1, PT_R13
	546	lwi r12, r1, PT_R12
	547	lwi r11, r1, PT_R11
	548	lwi r10, r1, PT_R10
	549	lwi r9, r1, PT_R9
	550	lwi r8, r1, PT_R8
	551	lwi r7, r1, PT_R7
	552	lwi r6, r1, PT_R6
	553	lwi r5, r1, PT_R5
	554	lwi r4, r1, PT_R4 /* return val */
	555	lwi r3, r1, PT_R3 /* return val */
	556	lwi r2, r1, PT_R2
	557	lwi r1, r1, PT_R1
	558
	559	rtid r14, 0
	560	nop
561
6d5af1a3 MS	562	sys_rt_sigreturn_wrapper:
	563	brid sys_rt_sigreturn
	564	addk r5, r1, r0
	565
6d5af1a3 MS	566	/* Interrupt vector table */
	567	.section .init.ivt, "ax"
	568	.org 0x0
	569	brai _reset
	570	brai _user_exception
	571	brai _interrupt
	572	brai _break
	573	brai _hw_exception_handler
	574	.org 0x60
	575	brai _debug_exception
	576
	577	.section .rodata,"a"
	578	#include "syscall_table.S"
	579
	580	syscall_table_size=(.-sys_call_table)
ce3266c0 SM	581
	582	type_SYSCALL:
	583	.ascii "SYSCALL\0"
	584	type_IRQ:
	585	.ascii "IRQ\0"
	586	type_IRQ_PREEMPT:
	587	.ascii "IRQ (PREEMPTED)\0"
	588	type_SYSCALL_PREEMPT:
	589	.ascii " SYSCALL (PREEMPTED)\0"
	590
	591	/*
	592	* Trap decoding for stack unwinder
	593	* Tuples are (start addr, end addr, string)
	594	* If return address lies on [start addr, end addr],
	595	* unwinder displays 'string'
	596	*/
	597
	598	.align 4
	599	.global microblaze_trap_handlers
	600	microblaze_trap_handlers:
	601	/* Exact matches come first */
	602	.word ret_to_user ; .word ret_to_user ; .word type_SYSCALL
	603	.word ret_from_intr; .word ret_from_intr ; .word type_IRQ
	604	/* Fuzzy matches go here */
	605	.word ret_from_intr; .word no_intr_resched; .word type_IRQ_PREEMPT
	606	.word work_pending ; .word no_work_pending; .word type_SYSCALL_PREEMPT
	607	/* End of table */
	608	.word 0 ; .word 0 ; .word 0