Commit | Line | Data |
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c4df4bc1 MS |
1 | /* |
2 | * Exception handling for Microblaze | |
3 | * | |
4 | * Rewriten interrupt handling | |
5 | * | |
6 | * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> | |
7 | * Copyright (C) 2008-2009 PetaLogix | |
8 | * | |
9 | * uClinux customisation (C) 2005 John Williams | |
10 | * | |
11 | * MMU code derived from arch/ppc/kernel/head_4xx.S: | |
12 | * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
13 | * Initial PowerPC version. | |
14 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
15 | * Rewritten for PReP | |
16 | * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au> | |
17 | * Low-level exception handers, MMU support, and rewrite. | |
18 | * Copyright (C) 1997 Dan Malek <dmalek@jlc.net> | |
19 | * PowerPC 8xx modifications. | |
20 | * Copyright (C) 1998-1999 TiVo, Inc. | |
21 | * PowerPC 403GCX modifications. | |
22 | * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu> | |
23 | * PowerPC 403GCX/405GP modifications. | |
24 | * Copyright 2000 MontaVista Software Inc. | |
25 | * PPC405 modifications | |
26 | * PowerPC 403GCX/405GP modifications. | |
27 | * Author: MontaVista Software, Inc. | |
28 | * frank_rowand@mvista.com or source@mvista.com | |
29 | * debbie_chu@mvista.com | |
30 | * | |
31 | * Original code | |
32 | * Copyright (C) 2004 Xilinx, Inc. | |
33 | * | |
34 | * This program is free software; you can redistribute it and/or modify it | |
35 | * under the terms of the GNU General Public License version 2 as published | |
36 | * by the Free Software Foundation. | |
37 | */ | |
38 | ||
39 | /* | |
40 | * Here are the handlers which don't require enabling translation | |
41 | * and calling other kernel code thus we can keep their design very simple | |
42 | * and do all processing in real mode. All what they need is a valid current | |
43 | * (that is an issue for the CONFIG_REGISTER_TASK_PTR case) | |
44 | * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore | |
45 | * these registers are saved/restored | |
46 | * The handlers which require translation are in entry.S --KAA | |
47 | * | |
48 | * Microblaze HW Exception Handler | |
49 | * - Non self-modifying exception handler for the following exception conditions | |
50 | * - Unalignment | |
51 | * - Instruction bus error | |
52 | * - Data bus error | |
53 | * - Illegal instruction opcode | |
54 | * - Divide-by-zero | |
55 | * | |
7db29dde MS |
56 | * - Privileged instruction exception (MMU) |
57 | * - Data storage exception (MMU) | |
58 | * - Instruction storage exception (MMU) | |
59 | * - Data TLB miss exception (MMU) | |
60 | * - Instruction TLB miss exception (MMU) | |
61 | * | |
c4df4bc1 MS |
62 | * Note we disable interrupts during exception handling, otherwise we will |
63 | * possibly get multiple re-entrancy if interrupt handles themselves cause | |
64 | * exceptions. JW | |
65 | */ | |
66 | ||
67 | #include <asm/exceptions.h> | |
68 | #include <asm/unistd.h> | |
69 | #include <asm/page.h> | |
70 | ||
71 | #include <asm/entry.h> | |
72 | #include <asm/current.h> | |
73 | #include <linux/linkage.h> | |
74 | ||
75 | #include <asm/mmu.h> | |
76 | #include <asm/pgtable.h> | |
3863dbce | 77 | #include <asm/signal.h> |
c4df4bc1 MS |
78 | #include <asm/asm-offsets.h> |
79 | ||
80 | /* Helpful Macros */ | |
7db29dde | 81 | #ifndef CONFIG_MMU |
c4df4bc1 | 82 | #define EX_HANDLER_STACK_SIZ (4*19) |
7db29dde | 83 | #endif |
c4df4bc1 MS |
84 | #define NUM_TO_REG(num) r ## num |
85 | ||
7db29dde | 86 | #ifdef CONFIG_MMU |
7db29dde | 87 | #define RESTORE_STATE \ |
ac854ff1 MS |
88 | lwi r5, r1, 0; \ |
89 | mts rmsr, r5; \ | |
90 | nop; \ | |
7db29dde MS |
91 | lwi r3, r1, PT_R3; \ |
92 | lwi r4, r1, PT_R4; \ | |
93 | lwi r5, r1, PT_R5; \ | |
94 | lwi r6, r1, PT_R6; \ | |
95 | lwi r11, r1, PT_R11; \ | |
96 | lwi r31, r1, PT_R31; \ | |
97 | lwi r1, r0, TOPHYS(r0_ram + 0); | |
98 | #endif /* CONFIG_MMU */ | |
99 | ||
c4df4bc1 MS |
100 | #define LWREG_NOP \ |
101 | bri ex_handler_unhandled; \ | |
102 | nop; | |
103 | ||
104 | #define SWREG_NOP \ | |
105 | bri ex_handler_unhandled; \ | |
106 | nop; | |
107 | ||
108 | /* FIXME this is weird - for noMMU kernel is not possible to use brid | |
109 | * instruction which can shorten executed time | |
110 | */ | |
111 | ||
112 | /* r3 is the source */ | |
113 | #define R3_TO_LWREG_V(regnum) \ | |
114 | swi r3, r1, 4 * regnum; \ | |
115 | bri ex_handler_done; | |
116 | ||
117 | /* r3 is the source */ | |
118 | #define R3_TO_LWREG(regnum) \ | |
119 | or NUM_TO_REG (regnum), r0, r3; \ | |
120 | bri ex_handler_done; | |
121 | ||
122 | /* r3 is the target */ | |
123 | #define SWREG_TO_R3_V(regnum) \ | |
124 | lwi r3, r1, 4 * regnum; \ | |
125 | bri ex_sw_tail; | |
126 | ||
127 | /* r3 is the target */ | |
128 | #define SWREG_TO_R3(regnum) \ | |
129 | or r3, r0, NUM_TO_REG (regnum); \ | |
130 | bri ex_sw_tail; | |
131 | ||
7db29dde MS |
132 | #ifdef CONFIG_MMU |
133 | #define R3_TO_LWREG_VM_V(regnum) \ | |
134 | brid ex_lw_end_vm; \ | |
135 | swi r3, r7, 4 * regnum; | |
136 | ||
137 | #define R3_TO_LWREG_VM(regnum) \ | |
138 | brid ex_lw_end_vm; \ | |
139 | or NUM_TO_REG (regnum), r0, r3; | |
140 | ||
141 | #define SWREG_TO_R3_VM_V(regnum) \ | |
142 | brid ex_sw_tail_vm; \ | |
143 | lwi r3, r7, 4 * regnum; | |
144 | ||
145 | #define SWREG_TO_R3_VM(regnum) \ | |
146 | brid ex_sw_tail_vm; \ | |
147 | or r3, r0, NUM_TO_REG (regnum); | |
148 | ||
149 | /* Shift right instruction depending on available configuration */ | |
150 | #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0 | |
151 | #define BSRLI(rD, rA, imm) \ | |
152 | bsrli rD, rA, imm | |
153 | #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0 | |
154 | #define BSRLI(rD, rA, imm) \ | |
155 | ori rD, r0, (1 << imm); \ | |
156 | idivu rD, rD, rA | |
157 | #else | |
158 | #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA) | |
159 | /* Only the used shift constants defined here - add more if needed */ | |
160 | #define BSRLI2(rD, rA) \ | |
161 | srl rD, rA; /* << 1 */ \ | |
162 | srl rD, rD; /* << 2 */ | |
163 | #define BSRLI10(rD, rA) \ | |
164 | srl rD, rA; /* << 1 */ \ | |
165 | srl rD, rD; /* << 2 */ \ | |
166 | srl rD, rD; /* << 3 */ \ | |
167 | srl rD, rD; /* << 4 */ \ | |
168 | srl rD, rD; /* << 5 */ \ | |
169 | srl rD, rD; /* << 6 */ \ | |
170 | srl rD, rD; /* << 7 */ \ | |
171 | srl rD, rD; /* << 8 */ \ | |
172 | srl rD, rD; /* << 9 */ \ | |
173 | srl rD, rD /* << 10 */ | |
174 | #define BSRLI20(rD, rA) \ | |
175 | BSRLI10(rD, rA); \ | |
176 | BSRLI10(rD, rD) | |
177 | #endif | |
178 | #endif /* CONFIG_MMU */ | |
179 | ||
c4df4bc1 MS |
180 | .extern other_exception_handler /* Defined in exception.c */ |
181 | ||
182 | /* | |
183 | * hw_exception_handler - Handler for exceptions | |
184 | * | |
185 | * Exception handler notes: | |
186 | * - Handles all exceptions | |
187 | * - Does not handle unaligned exceptions during load into r17, r1, r0. | |
188 | * - Does not handle unaligned exceptions during store from r17 (cannot be | |
189 | * done) and r1 (slows down common case) | |
190 | * | |
191 | * Relevant register structures | |
192 | * | |
193 | * EAR - |----|----|----|----|----|----|----|----| | |
194 | * - < ## 32 bit faulting address ## > | |
195 | * | |
196 | * ESR - |----|----|----|----|----| - | - |-----|-----| | |
197 | * - W S REG EXC | |
198 | * | |
199 | * | |
200 | * STACK FRAME STRUCTURE (for NO_MMU) | |
201 | * --------------------------------- | |
202 | * | |
203 | * +-------------+ + 0 | |
204 | * | MSR | | |
205 | * +-------------+ + 4 | |
206 | * | r1 | | |
207 | * | . | | |
208 | * | . | | |
209 | * | . | | |
210 | * | . | | |
211 | * | r18 | | |
212 | * +-------------+ + 76 | |
213 | * | . | | |
214 | * | . | | |
215 | * | |
216 | * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S | |
217 | * which is used for storing register values - old style was, that value were | |
218 | * stored in stack but in case of failure you lost information about register. | |
219 | * Currently you can see register value in memory in specific place. | |
220 | * In compare to with previous solution the speed should be the same. | |
221 | * | |
222 | * MMU exception handler has different handling compare to no MMU kernel. | |
223 | * Exception handler use jump table for directing of what happen. For MMU kernel | |
224 | * is this approach better because MMU relate exception are handled by asm code | |
225 | * in this file. In compare to with MMU expect of unaligned exception | |
226 | * is everything handled by C code. | |
227 | */ | |
228 | ||
229 | /* | |
230 | * every of these handlers is entered having R3/4/5/6/11/current saved on stack | |
231 | * and clobbered so care should be taken to restore them if someone is going to | |
232 | * return from exception | |
233 | */ | |
234 | ||
235 | /* wrappers to restore state before coming to entry.S */ | |
236 | ||
7db29dde MS |
237 | #ifdef CONFIG_MMU |
238 | .section .rodata | |
239 | .align 4 | |
240 | _MB_HW_ExceptionVectorTable: | |
241 | /* 0 - Undefined */ | |
242 | .long TOPHYS(ex_handler_unhandled) | |
243 | /* 1 - Unaligned data access exception */ | |
244 | .long TOPHYS(handle_unaligned_ex) | |
245 | /* 2 - Illegal op-code exception */ | |
246 | .long TOPHYS(full_exception_trapw) | |
247 | /* 3 - Instruction bus error exception */ | |
248 | .long TOPHYS(full_exception_trapw) | |
249 | /* 4 - Data bus error exception */ | |
250 | .long TOPHYS(full_exception_trapw) | |
251 | /* 5 - Divide by zero exception */ | |
252 | .long TOPHYS(full_exception_trapw) | |
253 | /* 6 - Floating point unit exception */ | |
254 | .long TOPHYS(full_exception_trapw) | |
255 | /* 7 - Privileged instruction exception */ | |
256 | .long TOPHYS(full_exception_trapw) | |
257 | /* 8 - 15 - Undefined */ | |
258 | .long TOPHYS(ex_handler_unhandled) | |
259 | .long TOPHYS(ex_handler_unhandled) | |
260 | .long TOPHYS(ex_handler_unhandled) | |
261 | .long TOPHYS(ex_handler_unhandled) | |
262 | .long TOPHYS(ex_handler_unhandled) | |
263 | .long TOPHYS(ex_handler_unhandled) | |
264 | .long TOPHYS(ex_handler_unhandled) | |
265 | .long TOPHYS(ex_handler_unhandled) | |
266 | /* 16 - Data storage exception */ | |
267 | .long TOPHYS(handle_data_storage_exception) | |
268 | /* 17 - Instruction storage exception */ | |
269 | .long TOPHYS(handle_instruction_storage_exception) | |
270 | /* 18 - Data TLB miss exception */ | |
271 | .long TOPHYS(handle_data_tlb_miss_exception) | |
272 | /* 19 - Instruction TLB miss exception */ | |
273 | .long TOPHYS(handle_instruction_tlb_miss_exception) | |
274 | /* 20 - 31 - Undefined */ | |
275 | .long TOPHYS(ex_handler_unhandled) | |
276 | .long TOPHYS(ex_handler_unhandled) | |
277 | .long TOPHYS(ex_handler_unhandled) | |
278 | .long TOPHYS(ex_handler_unhandled) | |
279 | .long TOPHYS(ex_handler_unhandled) | |
280 | .long TOPHYS(ex_handler_unhandled) | |
281 | .long TOPHYS(ex_handler_unhandled) | |
282 | .long TOPHYS(ex_handler_unhandled) | |
283 | .long TOPHYS(ex_handler_unhandled) | |
284 | .long TOPHYS(ex_handler_unhandled) | |
285 | .long TOPHYS(ex_handler_unhandled) | |
286 | .long TOPHYS(ex_handler_unhandled) | |
287 | #endif | |
288 | ||
c4df4bc1 MS |
289 | .global _hw_exception_handler |
290 | .section .text | |
291 | .align 4 | |
292 | .ent _hw_exception_handler | |
293 | _hw_exception_handler: | |
7db29dde | 294 | #ifndef CONFIG_MMU |
c4df4bc1 | 295 | addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ |
7db29dde MS |
296 | #else |
297 | swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */ | |
298 | /* Save date to kernel memory. Here is the problem | |
299 | * when you came from user space */ | |
300 | ori r1, r0, TOPHYS(r0_ram + 28); | |
301 | #endif | |
c4df4bc1 MS |
302 | swi r3, r1, PT_R3 |
303 | swi r4, r1, PT_R4 | |
304 | swi r5, r1, PT_R5 | |
305 | swi r6, r1, PT_R6 | |
306 | ||
7db29dde MS |
307 | #ifdef CONFIG_MMU |
308 | swi r11, r1, PT_R11 | |
309 | swi r31, r1, PT_R31 | |
310 | lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */ | |
311 | #endif | |
312 | ||
ac854ff1 MS |
313 | mfs r5, rmsr; |
314 | nop | |
315 | swi r5, r1, 0; | |
b175bcfe | 316 | mfs r4, resr |
c4df4bc1 | 317 | nop |
b175bcfe | 318 | mfs r3, rear; |
7db29dde | 319 | nop |
c4df4bc1 | 320 | |
7db29dde | 321 | #ifndef CONFIG_MMU |
b175bcfe | 322 | andi r5, r4, 0x1000; /* Check ESR[DS] */ |
c4df4bc1 MS |
323 | beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */ |
324 | mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ | |
325 | nop | |
326 | not_in_delay_slot: | |
327 | swi r17, r1, PT_R17 | |
7db29dde | 328 | #endif |
c4df4bc1 | 329 | |
b175bcfe | 330 | andi r5, r4, 0x1F; /* Extract ESR[EXC] */ |
c4df4bc1 | 331 | |
7db29dde MS |
332 | #ifdef CONFIG_MMU |
333 | /* Calculate exception vector offset = r5 << 2 */ | |
334 | addk r6, r5, r5; /* << 1 */ | |
335 | addk r6, r6, r6; /* << 2 */ | |
336 | ||
708e7153 | 337 | #ifdef DEBUG |
7db29dde MS |
338 | /* counting which exception happen */ |
339 | lwi r5, r0, 0x200 + TOPHYS(r0_ram) | |
340 | addi r5, r5, 1 | |
341 | swi r5, r0, 0x200 + TOPHYS(r0_ram) | |
342 | lwi r5, r6, 0x200 + TOPHYS(r0_ram) | |
343 | addi r5, r5, 1 | |
344 | swi r5, r6, 0x200 + TOPHYS(r0_ram) | |
708e7153 | 345 | #endif |
7db29dde MS |
346 | /* end */ |
347 | /* Load the HW Exception vector */ | |
348 | lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable) | |
349 | bra r6 | |
350 | ||
351 | full_exception_trapw: | |
352 | RESTORE_STATE | |
353 | bri full_exception_trap | |
354 | #else | |
c4df4bc1 MS |
355 | /* Exceptions enabled here. This will allow nested exceptions */ |
356 | mfs r6, rmsr; | |
357 | nop | |
358 | swi r6, r1, 0; /* RMSR_OFFSET */ | |
359 | ori r6, r6, 0x100; /* Turn ON the EE bit */ | |
360 | andi r6, r6, ~2; /* Disable interrupts */ | |
361 | mts rmsr, r6; | |
362 | nop | |
363 | ||
364 | xori r6, r5, 1; /* 00001 = Unaligned Exception */ | |
365 | /* Jump to unalignment exception handler */ | |
366 | beqi r6, handle_unaligned_ex; | |
367 | ||
368 | handle_other_ex: /* Handle Other exceptions here */ | |
369 | /* Save other volatiles before we make procedure calls below */ | |
370 | swi r7, r1, PT_R7 | |
371 | swi r8, r1, PT_R8 | |
372 | swi r9, r1, PT_R9 | |
373 | swi r10, r1, PT_R10 | |
374 | swi r11, r1, PT_R11 | |
375 | swi r12, r1, PT_R12 | |
376 | swi r14, r1, PT_R14 | |
377 | swi r15, r1, PT_R15 | |
378 | swi r18, r1, PT_R18 | |
379 | ||
380 | or r5, r1, r0 | |
b175bcfe | 381 | andi r6, r4, 0x1F; /* Load ESR[EC] */ |
c4df4bc1 MS |
382 | lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */ |
383 | swi r7, r1, PT_MODE | |
384 | mfs r7, rfsr | |
385 | nop | |
386 | addk r8, r17, r0; /* Load exception address */ | |
387 | bralid r15, full_exception; /* Branch to the handler */ | |
388 | nop; | |
131e4e97 | 389 | mts rfsr, r0; /* Clear sticky fsr */ |
71b23d54 | 390 | nop |
c4df4bc1 MS |
391 | |
392 | /* | |
393 | * Trigger execution of the signal handler by enabling | |
394 | * interrupts and calling an invalid syscall. | |
395 | */ | |
396 | mfs r5, rmsr; | |
397 | nop | |
398 | ori r5, r5, 2; | |
399 | mts rmsr, r5; /* enable interrupt */ | |
400 | nop | |
401 | addi r12, r0, __NR_syscalls; | |
402 | brki r14, 0x08; | |
403 | mfs r5, rmsr; /* disable interrupt */ | |
404 | nop | |
405 | andi r5, r5, ~2; | |
406 | mts rmsr, r5; | |
407 | nop | |
408 | ||
409 | lwi r7, r1, PT_R7 | |
410 | lwi r8, r1, PT_R8 | |
411 | lwi r9, r1, PT_R9 | |
412 | lwi r10, r1, PT_R10 | |
413 | lwi r11, r1, PT_R11 | |
414 | lwi r12, r1, PT_R12 | |
415 | lwi r14, r1, PT_R14 | |
416 | lwi r15, r1, PT_R15 | |
417 | lwi r18, r1, PT_R18 | |
418 | ||
419 | bri ex_handler_done; /* Complete exception handling */ | |
7db29dde | 420 | #endif |
c4df4bc1 MS |
421 | |
422 | /* 0x01 - Unaligned data access exception | |
423 | * This occurs when a word access is not aligned on a word boundary, | |
424 | * or when a 16-bit access is not aligned on a 16-bit boundary. | |
425 | * This handler perform the access, and returns, except for MMU when | |
426 | * the unaligned address is last on a 4k page or the physical address is | |
427 | * not found in the page table, in which case unaligned_data_trap is called. | |
428 | */ | |
429 | handle_unaligned_ex: | |
430 | /* Working registers already saved: R3, R4, R5, R6 | |
b175bcfe MS |
431 | * R4 = ESR |
432 | * R3 = EAR | |
c4df4bc1 | 433 | */ |
7db29dde | 434 | #ifdef CONFIG_MMU |
b175bcfe | 435 | andi r6, r4, 0x1000 /* Check ESR[DS] */ |
7db29dde MS |
436 | beqi r6, _no_delayslot /* Branch if ESR[DS] not set */ |
437 | mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ | |
c4df4bc1 | 438 | nop |
7db29dde | 439 | _no_delayslot: |
3863dbce MS |
440 | /* jump to high level unaligned handler */ |
441 | RESTORE_STATE; | |
442 | bri unaligned_data_trap | |
7db29dde | 443 | #endif |
b175bcfe | 444 | andi r6, r4, 0x3E0; /* Mask and extract the register operand */ |
c4df4bc1 MS |
445 | srl r6, r6; /* r6 >> 5 */ |
446 | srl r6, r6; | |
447 | srl r6, r6; | |
448 | srl r6, r6; | |
449 | srl r6, r6; | |
450 | /* Store the register operand in a temporary location */ | |
451 | sbi r6, r0, TOPHYS(ex_reg_op); | |
452 | ||
b175bcfe | 453 | andi r6, r4, 0x400; /* Extract ESR[S] */ |
c4df4bc1 MS |
454 | bnei r6, ex_sw; |
455 | ex_lw: | |
b175bcfe | 456 | andi r6, r4, 0x800; /* Extract ESR[W] */ |
c4df4bc1 | 457 | beqi r6, ex_lhw; |
b175bcfe | 458 | lbui r5, r3, 0; /* Exception address in r3 */ |
c4df4bc1 MS |
459 | /* Load a word, byte-by-byte from destination address |
460 | and save it in tmp space */ | |
461 | sbi r5, r0, TOPHYS(ex_tmp_data_loc_0); | |
b175bcfe | 462 | lbui r5, r3, 1; |
c4df4bc1 | 463 | sbi r5, r0, TOPHYS(ex_tmp_data_loc_1); |
b175bcfe | 464 | lbui r5, r3, 2; |
c4df4bc1 | 465 | sbi r5, r0, TOPHYS(ex_tmp_data_loc_2); |
b175bcfe | 466 | lbui r5, r3, 3; |
c4df4bc1 | 467 | sbi r5, r0, TOPHYS(ex_tmp_data_loc_3); |
b175bcfe MS |
468 | /* Get the destination register value into r4 */ |
469 | lwi r4, r0, TOPHYS(ex_tmp_data_loc_0); | |
c4df4bc1 MS |
470 | bri ex_lw_tail; |
471 | ex_lhw: | |
b175bcfe | 472 | lbui r5, r3, 0; /* Exception address in r3 */ |
c4df4bc1 MS |
473 | /* Load a half-word, byte-by-byte from destination |
474 | address and save it in tmp space */ | |
475 | sbi r5, r0, TOPHYS(ex_tmp_data_loc_0); | |
b175bcfe | 476 | lbui r5, r3, 1; |
c4df4bc1 | 477 | sbi r5, r0, TOPHYS(ex_tmp_data_loc_1); |
b175bcfe MS |
478 | /* Get the destination register value into r4 */ |
479 | lhui r4, r0, TOPHYS(ex_tmp_data_loc_0); | |
c4df4bc1 MS |
480 | ex_lw_tail: |
481 | /* Get the destination register number into r5 */ | |
482 | lbui r5, r0, TOPHYS(ex_reg_op); | |
483 | /* Form load_word jump table offset (lw_table + (8 * regnum)) */ | |
484 | la r6, r0, TOPHYS(lw_table); | |
485 | addk r5, r5, r5; | |
486 | addk r5, r5, r5; | |
487 | addk r5, r5, r5; | |
488 | addk r5, r5, r6; | |
489 | bra r5; | |
490 | ex_lw_end: /* Exception handling of load word, ends */ | |
491 | ex_sw: | |
492 | /* Get the destination register number into r5 */ | |
493 | lbui r5, r0, TOPHYS(ex_reg_op); | |
494 | /* Form store_word jump table offset (sw_table + (8 * regnum)) */ | |
495 | la r6, r0, TOPHYS(sw_table); | |
496 | add r5, r5, r5; | |
497 | add r5, r5, r5; | |
498 | add r5, r5, r5; | |
499 | add r5, r5, r6; | |
500 | bra r5; | |
501 | ex_sw_tail: | |
502 | mfs r6, resr; | |
503 | nop | |
504 | andi r6, r6, 0x800; /* Extract ESR[W] */ | |
505 | beqi r6, ex_shw; | |
506 | /* Get the word - delay slot */ | |
b175bcfe | 507 | swi r4, r0, TOPHYS(ex_tmp_data_loc_0); |
c4df4bc1 | 508 | /* Store the word, byte-by-byte into destination address */ |
b175bcfe MS |
509 | lbui r4, r0, TOPHYS(ex_tmp_data_loc_0); |
510 | sbi r4, r3, 0; | |
511 | lbui r4, r0, TOPHYS(ex_tmp_data_loc_1); | |
512 | sbi r4, r3, 1; | |
513 | lbui r4, r0, TOPHYS(ex_tmp_data_loc_2); | |
514 | sbi r4, r3, 2; | |
515 | lbui r4, r0, TOPHYS(ex_tmp_data_loc_3); | |
516 | sbi r4, r3, 3; | |
c4df4bc1 MS |
517 | bri ex_handler_done; |
518 | ||
519 | ex_shw: | |
520 | /* Store the lower half-word, byte-by-byte into destination address */ | |
b175bcfe MS |
521 | swi r4, r0, TOPHYS(ex_tmp_data_loc_0); |
522 | lbui r4, r0, TOPHYS(ex_tmp_data_loc_2); | |
523 | sbi r4, r3, 0; | |
524 | lbui r4, r0, TOPHYS(ex_tmp_data_loc_3); | |
525 | sbi r4, r3, 1; | |
c4df4bc1 MS |
526 | ex_sw_end: /* Exception handling of store word, ends. */ |
527 | ||
528 | ex_handler_done: | |
7db29dde | 529 | #ifndef CONFIG_MMU |
c4df4bc1 MS |
530 | lwi r5, r1, 0 /* RMSR */ |
531 | mts rmsr, r5 | |
532 | nop | |
533 | lwi r3, r1, PT_R3 | |
534 | lwi r4, r1, PT_R4 | |
535 | lwi r5, r1, PT_R5 | |
536 | lwi r6, r1, PT_R6 | |
537 | lwi r17, r1, PT_R17 | |
538 | ||
539 | rted r17, 0 | |
540 | addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ | |
7db29dde MS |
541 | #else |
542 | RESTORE_STATE; | |
543 | rted r17, 0 | |
544 | nop | |
545 | #endif | |
546 | ||
547 | #ifdef CONFIG_MMU | |
548 | /* Exception vector entry code. This code runs with address translation | |
549 | * turned off (i.e. using physical addresses). */ | |
550 | ||
551 | /* Exception vectors. */ | |
552 | ||
553 | /* 0x10 - Data Storage Exception | |
554 | * This happens for just a few reasons. U0 set (but we don't do that), | |
555 | * or zone protection fault (user violation, write to protected page). | |
556 | * If this is just an update of modified status, we do that quickly | |
557 | * and exit. Otherwise, we call heavyweight functions to do the work. | |
558 | */ | |
559 | handle_data_storage_exception: | |
560 | /* Working registers already saved: R3, R4, R5, R6 | |
561 | * R3 = ESR | |
562 | */ | |
563 | mfs r11, rpid | |
564 | nop | |
7db29dde MS |
565 | /* If we are faulting a kernel address, we have to use the |
566 | * kernel page tables. | |
567 | */ | |
bd1637d6 MS |
568 | ori r5, r0, CONFIG_KERNEL_START |
569 | cmpu r5, r3, r5 | |
570 | bgti r5, ex3 | |
7db29dde MS |
571 | /* First, check if it was a zone fault (which means a user |
572 | * tried to access a kernel or read-protected page - always | |
573 | * a SEGV). All other faults here must be stores, so no | |
574 | * need to check ESR_S as well. */ | |
7db29dde MS |
575 | andi r4, r4, 0x800 /* ESR_Z - zone protection */ |
576 | bnei r4, ex2 | |
577 | ||
578 | ori r4, r0, swapper_pg_dir | |
579 | mts rpid, r0 /* TLB will have 0 TID */ | |
580 | nop | |
581 | bri ex4 | |
582 | ||
583 | /* Get the PGD for the current thread. */ | |
584 | ex3: | |
585 | /* First, check if it was a zone fault (which means a user | |
586 | * tried to access a kernel or read-protected page - always | |
587 | * a SEGV). All other faults here must be stores, so no | |
588 | * need to check ESR_S as well. */ | |
7db29dde MS |
589 | andi r4, r4, 0x800 /* ESR_Z */ |
590 | bnei r4, ex2 | |
591 | /* get current task address */ | |
592 | addi r4 ,CURRENT_TASK, TOPHYS(0); | |
593 | lwi r4, r4, TASK_THREAD+PGDIR | |
594 | ex4: | |
595 | tophys(r4,r4) | |
596 | BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ | |
597 | andi r5, r5, 0xffc | |
598 | /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ | |
599 | or r4, r4, r5 | |
600 | lwi r4, r4, 0 /* Get L1 entry */ | |
601 | andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ | |
602 | beqi r5, ex2 /* Bail if no table */ | |
603 | ||
604 | tophys(r5,r5) | |
605 | BSRLI(r6,r3,10) /* Compute PTE address */ | |
606 | andi r6, r6, 0xffc | |
607 | andi r5, r5, 0xfffff003 | |
608 | or r5, r5, r6 | |
609 | lwi r4, r5, 0 /* Get Linux PTE */ | |
610 | ||
611 | andi r6, r4, _PAGE_RW /* Is it writeable? */ | |
612 | beqi r6, ex2 /* Bail if not */ | |
613 | ||
614 | /* Update 'changed' */ | |
615 | ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE | |
616 | swi r4, r5, 0 /* Update Linux page table */ | |
617 | ||
618 | /* Most of the Linux PTE is ready to load into the TLB LO. | |
619 | * We set ZSEL, where only the LS-bit determines user access. | |
620 | * We set execute, because we don't have the granularity to | |
621 | * properly set this at the page level (Linux problem). | |
622 | * If shared is set, we cause a zero PID->TID load. | |
623 | * Many of these bits are software only. Bits we don't set | |
624 | * here we (properly should) assume have the appropriate value. | |
625 | */ | |
626 | andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ | |
627 | ori r4, r4, _PAGE_HWEXEC /* make it executable */ | |
628 | ||
629 | /* find the TLB index that caused the fault. It has to be here*/ | |
630 | mts rtlbsx, r3 | |
631 | nop | |
632 | mfs r5, rtlbx /* DEBUG: TBD */ | |
633 | nop | |
634 | mts rtlblo, r4 /* Load TLB LO */ | |
635 | nop | |
636 | /* Will sync shadow TLBs */ | |
637 | ||
638 | /* Done...restore registers and get out of here. */ | |
639 | mts rpid, r11 | |
640 | nop | |
641 | bri 4 | |
642 | ||
643 | RESTORE_STATE; | |
644 | rted r17, 0 | |
645 | nop | |
646 | ex2: | |
647 | /* The bailout. Restore registers to pre-exception conditions | |
648 | * and call the heavyweights to help us out. */ | |
649 | mts rpid, r11 | |
650 | nop | |
651 | bri 4 | |
652 | RESTORE_STATE; | |
653 | bri page_fault_data_trap | |
654 | ||
655 | ||
656 | /* 0x11 - Instruction Storage Exception | |
657 | * This is caused by a fetch from non-execute or guarded pages. */ | |
658 | handle_instruction_storage_exception: | |
659 | /* Working registers already saved: R3, R4, R5, R6 | |
660 | * R3 = ESR | |
661 | */ | |
662 | ||
7db29dde MS |
663 | RESTORE_STATE; |
664 | bri page_fault_instr_trap | |
665 | ||
666 | /* 0x12 - Data TLB Miss Exception | |
667 | * As the name implies, translation is not in the MMU, so search the | |
668 | * page tables and fix it. The only purpose of this function is to | |
669 | * load TLB entries from the page table if they exist. | |
670 | */ | |
671 | handle_data_tlb_miss_exception: | |
672 | /* Working registers already saved: R3, R4, R5, R6 | |
7a6bbdc9 | 673 | * R3 = EAR, R4 = ESR |
7db29dde MS |
674 | */ |
675 | mfs r11, rpid | |
676 | nop | |
7db29dde MS |
677 | |
678 | /* If we are faulting a kernel address, we have to use the | |
679 | * kernel page tables. */ | |
7a6bbdc9 MS |
680 | ori r6, r0, CONFIG_KERNEL_START |
681 | cmpu r4, r3, r6 | |
7db29dde MS |
682 | bgti r4, ex5 |
683 | ori r4, r0, swapper_pg_dir | |
684 | mts rpid, r0 /* TLB will have 0 TID */ | |
685 | nop | |
686 | bri ex6 | |
c4df4bc1 | 687 | |
7db29dde MS |
688 | /* Get the PGD for the current thread. */ |
689 | ex5: | |
690 | /* get current task address */ | |
691 | addi r4 ,CURRENT_TASK, TOPHYS(0); | |
692 | lwi r4, r4, TASK_THREAD+PGDIR | |
693 | ex6: | |
694 | tophys(r4,r4) | |
695 | BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ | |
696 | andi r5, r5, 0xffc | |
697 | /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ | |
698 | or r4, r4, r5 | |
699 | lwi r4, r4, 0 /* Get L1 entry */ | |
700 | andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ | |
701 | beqi r5, ex7 /* Bail if no table */ | |
702 | ||
703 | tophys(r5,r5) | |
704 | BSRLI(r6,r3,10) /* Compute PTE address */ | |
705 | andi r6, r6, 0xffc | |
706 | andi r5, r5, 0xfffff003 | |
707 | or r5, r5, r6 | |
708 | lwi r4, r5, 0 /* Get Linux PTE */ | |
709 | ||
710 | andi r6, r4, _PAGE_PRESENT | |
711 | beqi r6, ex7 | |
712 | ||
713 | ori r4, r4, _PAGE_ACCESSED | |
714 | swi r4, r5, 0 | |
715 | ||
716 | /* Most of the Linux PTE is ready to load into the TLB LO. | |
717 | * We set ZSEL, where only the LS-bit determines user access. | |
718 | * We set execute, because we don't have the granularity to | |
719 | * properly set this at the page level (Linux problem). | |
720 | * If shared is set, we cause a zero PID->TID load. | |
721 | * Many of these bits are software only. Bits we don't set | |
722 | * here we (properly should) assume have the appropriate value. | |
723 | */ | |
3765d695 | 724 | brid finish_tlb_load |
7db29dde | 725 | andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ |
7db29dde MS |
726 | ex7: |
727 | /* The bailout. Restore registers to pre-exception conditions | |
728 | * and call the heavyweights to help us out. | |
729 | */ | |
730 | mts rpid, r11 | |
731 | nop | |
732 | bri 4 | |
733 | RESTORE_STATE; | |
734 | bri page_fault_data_trap | |
735 | ||
736 | /* 0x13 - Instruction TLB Miss Exception | |
737 | * Nearly the same as above, except we get our information from | |
738 | * different registers and bailout to a different point. | |
739 | */ | |
740 | handle_instruction_tlb_miss_exception: | |
741 | /* Working registers already saved: R3, R4, R5, R6 | |
742 | * R3 = ESR | |
743 | */ | |
744 | mfs r11, rpid | |
745 | nop | |
7db29dde MS |
746 | |
747 | /* If we are faulting a kernel address, we have to use the | |
748 | * kernel page tables. | |
749 | */ | |
750 | ori r4, r0, CONFIG_KERNEL_START | |
751 | cmpu r4, r3, r4 | |
752 | bgti r4, ex8 | |
753 | ori r4, r0, swapper_pg_dir | |
754 | mts rpid, r0 /* TLB will have 0 TID */ | |
755 | nop | |
756 | bri ex9 | |
757 | ||
758 | /* Get the PGD for the current thread. */ | |
759 | ex8: | |
760 | /* get current task address */ | |
761 | addi r4 ,CURRENT_TASK, TOPHYS(0); | |
762 | lwi r4, r4, TASK_THREAD+PGDIR | |
763 | ex9: | |
764 | tophys(r4,r4) | |
765 | BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ | |
766 | andi r5, r5, 0xffc | |
767 | /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ | |
768 | or r4, r4, r5 | |
769 | lwi r4, r4, 0 /* Get L1 entry */ | |
770 | andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ | |
771 | beqi r5, ex10 /* Bail if no table */ | |
772 | ||
773 | tophys(r5,r5) | |
774 | BSRLI(r6,r3,10) /* Compute PTE address */ | |
775 | andi r6, r6, 0xffc | |
776 | andi r5, r5, 0xfffff003 | |
777 | or r5, r5, r6 | |
778 | lwi r4, r5, 0 /* Get Linux PTE */ | |
779 | ||
780 | andi r6, r4, _PAGE_PRESENT | |
3765d695 | 781 | beqi r6, ex10 |
7db29dde MS |
782 | |
783 | ori r4, r4, _PAGE_ACCESSED | |
784 | swi r4, r5, 0 | |
785 | ||
786 | /* Most of the Linux PTE is ready to load into the TLB LO. | |
787 | * We set ZSEL, where only the LS-bit determines user access. | |
788 | * We set execute, because we don't have the granularity to | |
789 | * properly set this at the page level (Linux problem). | |
790 | * If shared is set, we cause a zero PID->TID load. | |
791 | * Many of these bits are software only. Bits we don't set | |
792 | * here we (properly should) assume have the appropriate value. | |
793 | */ | |
3765d695 | 794 | brid finish_tlb_load |
7db29dde | 795 | andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ |
7db29dde MS |
796 | ex10: |
797 | /* The bailout. Restore registers to pre-exception conditions | |
798 | * and call the heavyweights to help us out. | |
799 | */ | |
800 | mts rpid, r11 | |
801 | nop | |
802 | bri 4 | |
803 | RESTORE_STATE; | |
804 | bri page_fault_instr_trap | |
805 | ||
806 | /* Both the instruction and data TLB miss get to this point to load the TLB. | |
807 | * r3 - EA of fault | |
808 | * r4 - TLB LO (info from Linux PTE) | |
809 | * r5, r6 - available to use | |
810 | * PID - loaded with proper value when we get here | |
811 | * Upon exit, we reload everything and RFI. | |
812 | * A common place to load the TLB. | |
813 | */ | |
814 | tlb_index: | |
815 | .long 1 /* MS: storing last used tlb index */ | |
816 | finish_tlb_load: | |
817 | /* MS: load the last used TLB index. */ | |
818 | lwi r5, r0, TOPHYS(tlb_index) | |
819 | addik r5, r5, 1 /* MS: inc tlb_index -> use next one */ | |
820 | ||
821 | /* MS: FIXME this is potential fault, because this is mask not count */ | |
822 | andi r5, r5, (MICROBLAZE_TLB_SIZE-1) | |
823 | ori r6, r0, 1 | |
824 | cmp r31, r5, r6 | |
3765d695 | 825 | blti r31, ex12 |
7db29dde | 826 | addik r5, r6, 1 |
3765d695 | 827 | ex12: |
7db29dde MS |
828 | /* MS: save back current TLB index */ |
829 | swi r5, r0, TOPHYS(tlb_index) | |
830 | ||
831 | ori r4, r4, _PAGE_HWEXEC /* make it executable */ | |
832 | mts rtlbx, r5 /* MS: save current TLB */ | |
833 | nop | |
834 | mts rtlblo, r4 /* MS: save to TLB LO */ | |
835 | nop | |
836 | ||
837 | /* Create EPN. This is the faulting address plus a static | |
838 | * set of bits. These are size, valid, E, U0, and ensure | |
839 | * bits 20 and 21 are zero. | |
840 | */ | |
841 | andi r3, r3, 0xfffff000 | |
842 | ori r3, r3, 0x0c0 | |
843 | mts rtlbhi, r3 /* Load TLB HI */ | |
844 | nop | |
845 | ||
846 | /* Done...restore registers and get out of here. */ | |
7db29dde MS |
847 | mts rpid, r11 |
848 | nop | |
849 | bri 4 | |
850 | RESTORE_STATE; | |
851 | rted r17, 0 | |
852 | nop | |
853 | ||
854 | /* extern void giveup_fpu(struct task_struct *prev) | |
855 | * | |
856 | * The MicroBlaze processor may have an FPU, so this should not just | |
857 | * return: TBD. | |
858 | */ | |
859 | .globl giveup_fpu; | |
860 | .align 4; | |
861 | giveup_fpu: | |
862 | bralid r15,0 /* TBD */ | |
863 | nop | |
864 | ||
865 | /* At present, this routine just hangs. - extern void abort(void) */ | |
866 | .globl abort; | |
867 | .align 4; | |
868 | abort: | |
869 | br r0 | |
870 | ||
871 | .globl set_context; | |
872 | .align 4; | |
873 | set_context: | |
874 | mts rpid, r5 /* Shadow TLBs are automatically */ | |
875 | nop | |
876 | bri 4 /* flushed by changing PID */ | |
877 | rtsd r15,8 | |
878 | nop | |
879 | ||
880 | #endif | |
c4df4bc1 MS |
881 | .end _hw_exception_handler |
882 | ||
7db29dde MS |
883 | #ifdef CONFIG_MMU |
884 | /* Unaligned data access exception last on a 4k page for MMU. | |
885 | * When this is called, we are in virtual mode with exceptions enabled | |
886 | * and registers 1-13,15,17,18 saved. | |
887 | * | |
888 | * R3 = ESR | |
889 | * R4 = EAR | |
890 | * R7 = pointer to saved registers (struct pt_regs *regs) | |
891 | * | |
892 | * This handler perform the access, and returns via ret_from_exc. | |
893 | */ | |
894 | .global _unaligned_data_exception | |
895 | .ent _unaligned_data_exception | |
896 | _unaligned_data_exception: | |
897 | andi r8, r3, 0x3E0; /* Mask and extract the register operand */ | |
898 | BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */ | |
899 | andi r6, r3, 0x400; /* Extract ESR[S] */ | |
900 | bneid r6, ex_sw_vm; | |
901 | andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */ | |
902 | ex_lw_vm: | |
903 | beqid r6, ex_lhw_vm; | |
3863dbce | 904 | load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */ |
7db29dde MS |
905 | /* Load a word, byte-by-byte from destination address and save it in tmp space*/ |
906 | la r6, r0, ex_tmp_data_loc_0; | |
907 | sbi r5, r6, 0; | |
3863dbce | 908 | load2: lbui r5, r4, 1; |
7db29dde | 909 | sbi r5, r6, 1; |
3863dbce | 910 | load3: lbui r5, r4, 2; |
7db29dde | 911 | sbi r5, r6, 2; |
3863dbce | 912 | load4: lbui r5, r4, 3; |
7db29dde MS |
913 | sbi r5, r6, 3; |
914 | brid ex_lw_tail_vm; | |
915 | /* Get the destination register value into r3 - delay slot */ | |
916 | lwi r3, r6, 0; | |
917 | ex_lhw_vm: | |
918 | /* Load a half-word, byte-by-byte from destination address and | |
919 | * save it in tmp space */ | |
920 | la r6, r0, ex_tmp_data_loc_0; | |
921 | sbi r5, r6, 0; | |
3863dbce | 922 | load5: lbui r5, r4, 1; |
7db29dde MS |
923 | sbi r5, r6, 1; |
924 | lhui r3, r6, 0; /* Get the destination register value into r3 */ | |
925 | ex_lw_tail_vm: | |
926 | /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */ | |
927 | addik r5, r8, lw_table_vm; | |
928 | bra r5; | |
929 | ex_lw_end_vm: /* Exception handling of load word, ends */ | |
930 | brai ret_from_exc; | |
931 | ex_sw_vm: | |
932 | /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */ | |
933 | addik r5, r8, sw_table_vm; | |
934 | bra r5; | |
935 | ex_sw_tail_vm: | |
936 | la r5, r0, ex_tmp_data_loc_0; | |
937 | beqid r6, ex_shw_vm; | |
938 | swi r3, r5, 0; /* Get the word - delay slot */ | |
939 | /* Store the word, byte-by-byte into destination address */ | |
940 | lbui r3, r5, 0; | |
3863dbce | 941 | store1: sbi r3, r4, 0; |
7db29dde | 942 | lbui r3, r5, 1; |
3863dbce | 943 | store2: sbi r3, r4, 1; |
7db29dde | 944 | lbui r3, r5, 2; |
3863dbce | 945 | store3: sbi r3, r4, 2; |
7db29dde MS |
946 | lbui r3, r5, 3; |
947 | brid ret_from_exc; | |
3863dbce | 948 | store4: sbi r3, r4, 3; /* Delay slot */ |
7db29dde MS |
949 | ex_shw_vm: |
950 | /* Store the lower half-word, byte-by-byte into destination address */ | |
951 | lbui r3, r5, 2; | |
3863dbce | 952 | store5: sbi r3, r4, 0; |
7db29dde MS |
953 | lbui r3, r5, 3; |
954 | brid ret_from_exc; | |
3863dbce | 955 | store6: sbi r3, r4, 1; /* Delay slot */ |
7db29dde | 956 | ex_sw_end_vm: /* Exception handling of store word, ends. */ |
3863dbce MS |
957 | |
958 | /* We have to prevent cases that get/put_user macros get unaligned pointer | |
959 | * to bad page area. We have to find out which origin instruction caused it | |
960 | * and called fixup for that origin instruction not instruction in unaligned | |
961 | * handler */ | |
962 | ex_unaligned_fixup: | |
963 | ori r5, r7, 0 /* setup pointer to pt_regs */ | |
964 | lwi r6, r7, PT_PC; /* faulting address is one instruction above */ | |
965 | addik r6, r6, -4 /* for finding proper fixup */ | |
966 | swi r6, r7, PT_PC; /* a save back it to PT_PC */ | |
967 | addik r7, r0, SIGSEGV | |
968 | /* call bad_page_fault for finding aligned fixup, fixup address is saved | |
969 | * in PT_PC which is used as return address from exception */ | |
970 | la r15, r0, ret_from_exc-8 /* setup return address */ | |
971 | brid bad_page_fault | |
972 | nop | |
973 | ||
974 | /* We prevent all load/store because it could failed any attempt to access */ | |
975 | .section __ex_table,"a"; | |
976 | .word load1,ex_unaligned_fixup; | |
977 | .word load2,ex_unaligned_fixup; | |
978 | .word load3,ex_unaligned_fixup; | |
979 | .word load4,ex_unaligned_fixup; | |
980 | .word load5,ex_unaligned_fixup; | |
981 | .word store1,ex_unaligned_fixup; | |
982 | .word store2,ex_unaligned_fixup; | |
983 | .word store3,ex_unaligned_fixup; | |
984 | .word store4,ex_unaligned_fixup; | |
985 | .word store5,ex_unaligned_fixup; | |
986 | .word store6,ex_unaligned_fixup; | |
987 | .previous; | |
7db29dde MS |
988 | .end _unaligned_data_exception |
989 | #endif /* CONFIG_MMU */ | |
990 | ||
c4df4bc1 MS |
991 | ex_handler_unhandled: |
992 | /* FIXME add handle function for unhandled exception - dump register */ | |
993 | bri 0 | |
994 | ||
7db29dde MS |
995 | /* |
996 | * hw_exception_handler Jump Table | |
997 | * - Contains code snippets for each register that caused the unalign exception | |
998 | * - Hence exception handler is NOT self-modifying | |
999 | * - Separate table for load exceptions and store exceptions. | |
1000 | * - Each table is of size: (8 * 32) = 256 bytes | |
1001 | */ | |
1002 | ||
c4df4bc1 MS |
1003 | .section .text |
1004 | .align 4 | |
1005 | lw_table: | |
1006 | lw_r0: R3_TO_LWREG (0); | |
1007 | lw_r1: LWREG_NOP; | |
1008 | lw_r2: R3_TO_LWREG (2); | |
1009 | lw_r3: R3_TO_LWREG_V (3); | |
1010 | lw_r4: R3_TO_LWREG_V (4); | |
1011 | lw_r5: R3_TO_LWREG_V (5); | |
1012 | lw_r6: R3_TO_LWREG_V (6); | |
1013 | lw_r7: R3_TO_LWREG (7); | |
1014 | lw_r8: R3_TO_LWREG (8); | |
1015 | lw_r9: R3_TO_LWREG (9); | |
1016 | lw_r10: R3_TO_LWREG (10); | |
1017 | lw_r11: R3_TO_LWREG (11); | |
1018 | lw_r12: R3_TO_LWREG (12); | |
1019 | lw_r13: R3_TO_LWREG (13); | |
1020 | lw_r14: R3_TO_LWREG (14); | |
1021 | lw_r15: R3_TO_LWREG (15); | |
1022 | lw_r16: R3_TO_LWREG (16); | |
1023 | lw_r17: LWREG_NOP; | |
1024 | lw_r18: R3_TO_LWREG (18); | |
1025 | lw_r19: R3_TO_LWREG (19); | |
1026 | lw_r20: R3_TO_LWREG (20); | |
1027 | lw_r21: R3_TO_LWREG (21); | |
1028 | lw_r22: R3_TO_LWREG (22); | |
1029 | lw_r23: R3_TO_LWREG (23); | |
1030 | lw_r24: R3_TO_LWREG (24); | |
1031 | lw_r25: R3_TO_LWREG (25); | |
1032 | lw_r26: R3_TO_LWREG (26); | |
1033 | lw_r27: R3_TO_LWREG (27); | |
1034 | lw_r28: R3_TO_LWREG (28); | |
1035 | lw_r29: R3_TO_LWREG (29); | |
1036 | lw_r30: R3_TO_LWREG (30); | |
7db29dde MS |
1037 | #ifdef CONFIG_MMU |
1038 | lw_r31: R3_TO_LWREG_V (31); | |
1039 | #else | |
c4df4bc1 | 1040 | lw_r31: R3_TO_LWREG (31); |
7db29dde | 1041 | #endif |
c4df4bc1 MS |
1042 | |
1043 | sw_table: | |
1044 | sw_r0: SWREG_TO_R3 (0); | |
1045 | sw_r1: SWREG_NOP; | |
1046 | sw_r2: SWREG_TO_R3 (2); | |
1047 | sw_r3: SWREG_TO_R3_V (3); | |
1048 | sw_r4: SWREG_TO_R3_V (4); | |
1049 | sw_r5: SWREG_TO_R3_V (5); | |
1050 | sw_r6: SWREG_TO_R3_V (6); | |
1051 | sw_r7: SWREG_TO_R3 (7); | |
1052 | sw_r8: SWREG_TO_R3 (8); | |
1053 | sw_r9: SWREG_TO_R3 (9); | |
1054 | sw_r10: SWREG_TO_R3 (10); | |
1055 | sw_r11: SWREG_TO_R3 (11); | |
1056 | sw_r12: SWREG_TO_R3 (12); | |
1057 | sw_r13: SWREG_TO_R3 (13); | |
1058 | sw_r14: SWREG_TO_R3 (14); | |
1059 | sw_r15: SWREG_TO_R3 (15); | |
1060 | sw_r16: SWREG_TO_R3 (16); | |
1061 | sw_r17: SWREG_NOP; | |
1062 | sw_r18: SWREG_TO_R3 (18); | |
1063 | sw_r19: SWREG_TO_R3 (19); | |
1064 | sw_r20: SWREG_TO_R3 (20); | |
1065 | sw_r21: SWREG_TO_R3 (21); | |
1066 | sw_r22: SWREG_TO_R3 (22); | |
1067 | sw_r23: SWREG_TO_R3 (23); | |
1068 | sw_r24: SWREG_TO_R3 (24); | |
1069 | sw_r25: SWREG_TO_R3 (25); | |
1070 | sw_r26: SWREG_TO_R3 (26); | |
1071 | sw_r27: SWREG_TO_R3 (27); | |
1072 | sw_r28: SWREG_TO_R3 (28); | |
1073 | sw_r29: SWREG_TO_R3 (29); | |
1074 | sw_r30: SWREG_TO_R3 (30); | |
7db29dde MS |
1075 | #ifdef CONFIG_MMU |
1076 | sw_r31: SWREG_TO_R3_V (31); | |
1077 | #else | |
c4df4bc1 | 1078 | sw_r31: SWREG_TO_R3 (31); |
7db29dde MS |
1079 | #endif |
1080 | ||
1081 | #ifdef CONFIG_MMU | |
1082 | lw_table_vm: | |
1083 | lw_r0_vm: R3_TO_LWREG_VM (0); | |
1084 | lw_r1_vm: R3_TO_LWREG_VM_V (1); | |
1085 | lw_r2_vm: R3_TO_LWREG_VM_V (2); | |
1086 | lw_r3_vm: R3_TO_LWREG_VM_V (3); | |
1087 | lw_r4_vm: R3_TO_LWREG_VM_V (4); | |
1088 | lw_r5_vm: R3_TO_LWREG_VM_V (5); | |
1089 | lw_r6_vm: R3_TO_LWREG_VM_V (6); | |
1090 | lw_r7_vm: R3_TO_LWREG_VM_V (7); | |
1091 | lw_r8_vm: R3_TO_LWREG_VM_V (8); | |
1092 | lw_r9_vm: R3_TO_LWREG_VM_V (9); | |
1093 | lw_r10_vm: R3_TO_LWREG_VM_V (10); | |
1094 | lw_r11_vm: R3_TO_LWREG_VM_V (11); | |
1095 | lw_r12_vm: R3_TO_LWREG_VM_V (12); | |
1096 | lw_r13_vm: R3_TO_LWREG_VM_V (13); | |
1097 | lw_r14_vm: R3_TO_LWREG_VM (14); | |
1098 | lw_r15_vm: R3_TO_LWREG_VM_V (15); | |
1099 | lw_r16_vm: R3_TO_LWREG_VM (16); | |
1100 | lw_r17_vm: R3_TO_LWREG_VM_V (17); | |
1101 | lw_r18_vm: R3_TO_LWREG_VM_V (18); | |
1102 | lw_r19_vm: R3_TO_LWREG_VM (19); | |
1103 | lw_r20_vm: R3_TO_LWREG_VM (20); | |
1104 | lw_r21_vm: R3_TO_LWREG_VM (21); | |
1105 | lw_r22_vm: R3_TO_LWREG_VM (22); | |
1106 | lw_r23_vm: R3_TO_LWREG_VM (23); | |
1107 | lw_r24_vm: R3_TO_LWREG_VM (24); | |
1108 | lw_r25_vm: R3_TO_LWREG_VM (25); | |
1109 | lw_r26_vm: R3_TO_LWREG_VM (26); | |
1110 | lw_r27_vm: R3_TO_LWREG_VM (27); | |
1111 | lw_r28_vm: R3_TO_LWREG_VM (28); | |
1112 | lw_r29_vm: R3_TO_LWREG_VM (29); | |
1113 | lw_r30_vm: R3_TO_LWREG_VM (30); | |
1114 | lw_r31_vm: R3_TO_LWREG_VM_V (31); | |
1115 | ||
1116 | sw_table_vm: | |
1117 | sw_r0_vm: SWREG_TO_R3_VM (0); | |
1118 | sw_r1_vm: SWREG_TO_R3_VM_V (1); | |
1119 | sw_r2_vm: SWREG_TO_R3_VM_V (2); | |
1120 | sw_r3_vm: SWREG_TO_R3_VM_V (3); | |
1121 | sw_r4_vm: SWREG_TO_R3_VM_V (4); | |
1122 | sw_r5_vm: SWREG_TO_R3_VM_V (5); | |
1123 | sw_r6_vm: SWREG_TO_R3_VM_V (6); | |
1124 | sw_r7_vm: SWREG_TO_R3_VM_V (7); | |
1125 | sw_r8_vm: SWREG_TO_R3_VM_V (8); | |
1126 | sw_r9_vm: SWREG_TO_R3_VM_V (9); | |
1127 | sw_r10_vm: SWREG_TO_R3_VM_V (10); | |
1128 | sw_r11_vm: SWREG_TO_R3_VM_V (11); | |
1129 | sw_r12_vm: SWREG_TO_R3_VM_V (12); | |
1130 | sw_r13_vm: SWREG_TO_R3_VM_V (13); | |
1131 | sw_r14_vm: SWREG_TO_R3_VM (14); | |
1132 | sw_r15_vm: SWREG_TO_R3_VM_V (15); | |
1133 | sw_r16_vm: SWREG_TO_R3_VM (16); | |
1134 | sw_r17_vm: SWREG_TO_R3_VM_V (17); | |
1135 | sw_r18_vm: SWREG_TO_R3_VM_V (18); | |
1136 | sw_r19_vm: SWREG_TO_R3_VM (19); | |
1137 | sw_r20_vm: SWREG_TO_R3_VM (20); | |
1138 | sw_r21_vm: SWREG_TO_R3_VM (21); | |
1139 | sw_r22_vm: SWREG_TO_R3_VM (22); | |
1140 | sw_r23_vm: SWREG_TO_R3_VM (23); | |
1141 | sw_r24_vm: SWREG_TO_R3_VM (24); | |
1142 | sw_r25_vm: SWREG_TO_R3_VM (25); | |
1143 | sw_r26_vm: SWREG_TO_R3_VM (26); | |
1144 | sw_r27_vm: SWREG_TO_R3_VM (27); | |
1145 | sw_r28_vm: SWREG_TO_R3_VM (28); | |
1146 | sw_r29_vm: SWREG_TO_R3_VM (29); | |
1147 | sw_r30_vm: SWREG_TO_R3_VM (30); | |
1148 | sw_r31_vm: SWREG_TO_R3_VM_V (31); | |
1149 | #endif /* CONFIG_MMU */ | |
c4df4bc1 MS |
1150 | |
1151 | /* Temporary data structures used in the handler */ | |
1152 | .section .data | |
1153 | .align 4 | |
1154 | ex_tmp_data_loc_0: | |
1155 | .byte 0 | |
1156 | ex_tmp_data_loc_1: | |
1157 | .byte 0 | |
1158 | ex_tmp_data_loc_2: | |
1159 | .byte 0 | |
1160 | ex_tmp_data_loc_3: | |
1161 | .byte 0 | |
1162 | ex_reg_op: | |
1163 | .byte 0 |